[PATCH 0/2] i2c: designware: Fix stuck master on multi-master buses

[PATCH 0/2] i2c: designware: Fix stuck master on multi-master buses

[Sarah Maedel]

Since v7.0, the DesignWare controller used for IPMI SSIF on Ampere
Altra (DW_apb_i2c 1.20a) can get stuck after "spurious STOP detected"
errors, and stays unusable until a power cycle.

Patch 1 limits the spurious STOP check to controllers without
IC_EMPTYFIFO_HOLD_MASTER, as suggested by David LaPorte [1].

Patch 2 lets __i2c_dw_disable() abort a stuck master on configurations
without IC_STAT_FOR_CLK_STRETCH, where it otherwise never recovers.

Patch 2 was tested on Altra by forcing the stuck state through
/dev/mem. With both patches applied, IPMI commands in a loop no
longer hang the controller on a Gigabyte and an ASRock Rack Altra
server.

Both patches were prepared with the help of an AI coding assistant
(Claude Opus 5.5). I reviewed them and tested them as described above.

[1] https://lore.kernel.org/all/20260505232244.71807-1-dalaport@amazon.com/

Sarah Maedel (2):
  i2c: designware: Only check for spurious STOP without
    EMPTYFIFO_HOLD_MASTER
  i2c: designware: Abort stuck master when disabling times out

 drivers/i2c/busses/i2c-designware-common.c | 19 +++++++++++++++++++
 drivers/i2c/busses/i2c-designware-master.c |  7 +++++--
 2 files changed, 24 insertions(+), 2 deletions(-)


base-commit: b3dfbde62cf1981c4638939c159dfd087b7a72e9
-- 
2.47.3

[PATCH 1/2] i2c: designware: Only check for spurious STOP without EMPTYFIFO_HOLD_MASTER

[Sarah Maedel]

Commit 560072246088 ("i2c: designware: Support of controller with
IC_EMPTYFIFO_HOLD_MASTER disabled") fails a transfer when STOP_DET is
seen while a read or write is still in progress. This is meant to catch
Tx FIFO underruns on controllers without IC_EMPTYFIFO_HOLD_MASTER_EN,
but the check is applied to all controllers.

Controllers with IC_EMPTYFIFO_HOLD_MASTER_EN hold SCL on an empty Tx
FIFO and can't underrun, but on a multi-master bus they also see
STOP_DET for other masters' transactions. The driver then disables the
adapter while the controller is still busy with the transfer. On
DW_apb_i2c 1.20a (Ampere Altra, IPMI SSIF shared with the BMC) this
leaves the master stuck with IC_ENABLE_STATUS set, and all following
transfers fail with "timeout waiting for bus ready".

Limit the check to controllers without IC_EMPTYFIFO_HOLD_MASTER, as
suggested by David LaPorte.

Fixes: 560072246088 ("i2c: designware: Support of controller with IC_EMPTYFIFO_HOLD_MASTER disabled")
Cc: stable@vger.kernel.org # v7.0+
Suggested-by: David LaPorte <dalaport@amazon.com>
Link: https://lore.kernel.org/all/20260505232244.71807-1-dalaport@amazon.com/
Signed-off-by: Sarah Maedel <sarah.maedel@hetzner-cloud.de>
---
 drivers/i2c/busses/i2c-designware-master.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c
index 7e1d9a2e7733..d7d99c7b6ef2 100644
--- a/drivers/i2c/busses/i2c-designware-master.c
+++ b/drivers/i2c/busses/i2c-designware-master.c
@@ -675,8 +675,11 @@ static void i2c_dw_process_transfer(struct dw_i2c_dev *dev, unsigned int stat)
 	if (stat & DW_IC_INTR_TX_EMPTY)
 		i2c_dw_xfer_msg(dev);
 
-	/* Abort if we detect a STOP in the middle of a read or a write */
-	if ((stat & DW_IC_INTR_STOP_DET) &&
+	/*
+	 * Abort if we detect a STOP in the middle of a read or a write on a
+	 * controller that doesn't hold SCL on an empty Tx FIFO.
+	 */
+	if (!dev->emptyfifo_hold_master && (stat & DW_IC_INTR_STOP_DET) &&
 	    (dev->status & (STATUS_READ_IN_PROGRESS | STATUS_WRITE_IN_PROGRESS))) {
 		dev_err(dev->dev, "spurious STOP detected\n");
 		dev->rx_outstanding = 0;
-- 
2.47.3

[PATCH 2/2] i2c: designware: Abort stuck master when disabling times out

[Sarah Maedel]

__i2c_dw_disable() only aborts the current transfer if MST_ON_HOLD or
MASTER_HOLD_TX_FIFO_EMPTY is set. These bits only exist with
IC_STAT_FOR_CLK_STRETCH, so on other configurations a master left
holding the bus can't be disabled: IC_ENABLE_STATUS stays set and
IC_STATUS keeps reporting MST_ACTIVITY.

If the master is still active once the disable loop has timed out,
abort the transfer and try again. Also disable the adapter from
i2c_dw_wait_bus_not_busy() when bus recovery didn't help, so the next
transfer recovers the controller.

Tested on Ampere Altra by putting the controller into this state
through /dev/mem (a write without STOP, then clearing IC_ENABLE).

Signed-off-by: Sarah Maedel <sarah.maedel@hetzner-cloud.de>
---
 drivers/i2c/busses/i2c-designware-common.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c
index a1eca6cd4b75..2e8de0f6c1ed 100644
--- a/drivers/i2c/busses/i2c-designware-common.c
+++ b/drivers/i2c/busses/i2c-designware-common.c
@@ -643,6 +643,7 @@ void __i2c_dw_disable(struct dw_i2c_dev *dev)
 	if (dev->mode == DW_IC_SLAVE && (ic_stats & DW_IC_STATUS_SLAVE_ACTIVITY))
 		abort_needed = true;
 
+retry:
 	if (abort_needed) {
 		if (!(enable & DW_IC_ENABLE_ENABLE)) {
 			regmap_write(dev->map, DW_IC_ENABLE, DW_IC_ENABLE_ENABLE);
@@ -684,6 +685,19 @@ void __i2c_dw_disable(struct dw_i2c_dev *dev)
 		usleep_range(25, 250);
 	} while (timeout--);
 
+	/*
+	 * Without IC_STAT_FOR_CLK_STRETCH the hold status bits above don't
+	 * exist, so a stuck master is only noticed here.
+	 */
+	regmap_read(dev->map, DW_IC_STATUS, &ic_stats);
+	if (!abort_needed && (ic_stats & DW_IC_STATUS_MASTER_ACTIVITY)) {
+		dev_warn(dev->dev, "controller stuck active, aborting\n");
+		regmap_read(dev->map, DW_IC_ENABLE, &enable);
+		abort_needed = true;
+		timeout = 100;
+		goto retry;
+	}
+
 	dev_warn(dev->dev, "timeout in disabling adapter\n");
 }
 
@@ -764,6 +778,11 @@ int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
 		i2c_recover_bus(&dev->adapter);
 
 		regmap_read(dev->map, DW_IC_STATUS, &status);
+		if (status & DW_IC_STATUS_MASTER_ACTIVITY) {
+			/* Disabling aborts a master stuck on the bus */
+			__i2c_dw_disable(dev);
+			regmap_read(dev->map, DW_IC_STATUS, &status);
+		}
 		if (!(status & DW_IC_STATUS_ACTIVITY))
 			ret = 0;
 	}
-- 
2.47.3