From: Florian Fainelli <f.fainelli@gmail.com>
To: linux-mips@vger.kernel.org
Cc: macro@orcam.me.uk, Florian Fainelli <f.fainelli@gmail.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH] MIPS: SiByte: Add missing sb1_cache_error() prototype
Date: Tue, 10 Nov 2026 14:36:49 -0800 [thread overview]
Message-ID: <20261110223651.2698860-1-f.fainelli@gmail.com> (raw)
Fixes the following warning:
arch/mips/mm/cerr-sb1.c:165:17: warning: no previous prototype for ‘sb1_cache_error’ [-Wmissing-prototypes]
165 | asmlinkage void sb1_cache_error(void)
| ^~~~~~~~~~~~~~~
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/mips/include/asm/sibyte/sb1250.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/include/asm/sibyte/sb1250.h b/arch/mips/include/asm/sibyte/sb1250.h
index de4b352256c8..e42b3c9f4b53 100644
--- a/arch/mips/include/asm/sibyte/sb1250.h
+++ b/arch/mips/include/asm/sibyte/sb1250.h
@@ -32,6 +32,8 @@ extern unsigned int soc_type;
extern unsigned int periph_rev;
extern unsigned int zbbus_mhz;
+void sb1_cache_error(void);
+
extern void sb1250_mask_irq(int cpu, int irq);
extern void sb1250_unmask_irq(int cpu, int irq);
--
2.53.0
reply other threads:[~2026-11-10 22:36 UTC|newest]
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