* [PATCH v7 0/3] Fix VFCT matching after PCI bus renumbering
@ 2026-11-12 21:54 Mario Limonciello
2026-11-12 21:54 ` [PATCH v7 1/3] PCI: Cache bridge firmware secondary bus number Mario Limonciello
2026-11-12 21:54 ` [PATCH v7 2/3] drm/amdgpu: Match VFCT using initial PCI " Mario Limonciello
0 siblings, 2 replies; 3+ messages in thread
From: Mario Limonciello @ 2026-11-12 21:54 UTC (permalink / raw)
To: Bjorn Helgaas, Alex Deucher, Christian König
Cc: Oz Tiram, linux-pci, linux-kernel, amd-gfx, dri-devel,
Mario Limonciello, Reza Nikzad Chaleshori
amdgpu and radeon pick the VFCT image for a GPU by comparing the PCI bus
number recorded by the BIOS at POST with the device's bus number. When
the kernel renumbers buses (e.g. pci=realloc), the runtime number no
longer matches the one in VFCT.
commit 11c141672045f ("drm/amdgpu: Fix VFCT bus number matching with soft
filter") and its radeon counterpart worked around this by accepting an
entry whenever everything but the bus number matched. That picks the
wrong image when a system has two identical GPUs.
Instead, have the PCI core remember the secondary bus number the
firmware assigned to each bridge, and make amdgpu and radeon match the
VFCT bus number against it again, using the bridge above the GPU. The
value is captured once, when the bridge windows are first read, so
renumbering and later rescans don't overwrite it.
Patch 1 adds the cached firmware secondary bus number to struct pci_dev.
Patches 2 and 3 convert amdgpu and radeon to use it and drop the soft
filter.
Link: https://lore.kernel.org/linux-pci/20261015124843.203905-1-mario.limonciello@amd.com/
Link: https://lore.kernel.org/amd-gfx/20261019194106.2796150-1-alexander.deucher@amd.com/
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
Changes in v7:
- Reword the cover letter and the PCI patch to describe the current design:
the firmware secondary bus number is cached on the bridge pci_dev when its
bridge windows are first read, and amdgpu/radeon match VFCT against it.
- No code changes.
- Link to v6: https://patch.msgid.link/20261111-vfct-regression-v6-0-393797bbb6e3@amd.com
Changes in v6:
- Capture the firmware secondary bus number when reading bridge windows and
ignore unconfigured values so rescans cannot replace it with runtime data
(Sashiko).
- No change needed in the VFCT consumers; they continue to read the cached
value from the upstream bridge.
- Link to v5: https://patch.msgid.link/20261110-vfct-regression-v5-0-f49fae981bf3@amd.com
Changes in v5:
- Record the firmware secondary bus number only on the bridge struct pci_dev,
guard it with a validity bit, and keep it across rescans (Bjorn, Lijo).
- Drop pci_bus::number_initial and have amdgpu/radeon read the saved bridge
number when matching VFCT entries.
Changes in v4:
- Retain secondary bus bus number for a bridge across rescans, and the child bus is initialized
from it during allocation, before registration callbacks run. (Sashiko)
- Rename variable to clarify it's for bridges (Lijo)
- Link to v3: https://patch.msgid.link/20261026-vfct-regression-v3-0-fe9586ed6978@amd.com
Changes in v3:
- Preserve the firmware bus number across bridge renumbering, capturing the
secondary bus number before pci_scan_bridge_extend() clears it.
- Adjust member name in all patches
- Add tags
- Link to v2: https://patch.msgid.link/20261020-vfct-regression-v2-0-d2394d11450a@amd.com
Changes in v2:
- pci_alloc_dev(NULL) remains safe.
- For buses behind a reassigned bridge, the PCI core now saves the firmware secondary bus
number before clearing the bridge configuration and carries it into the newly allocated bus.
Devices discovered there inherit that original number.
- Add changes for radeon too.
- Link to v1: https://patch.msgid.link/20261019-vfct-regression-v1-0-5a63ddd378dd@amd.com
---
Mario Limonciello (3):
PCI: Cache bridge firmware secondary bus number
drm/amdgpu: Match VFCT using initial PCI bus number
drm/radeon: Match VFCT using initial PCI bus number
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 23 ++++++++++-------------
drivers/gpu/drm/radeon/radeon_bios.c | 25 +++++++++++--------------
drivers/pci/probe.c | 16 ++++++++++++++--
include/linux/pci.h | 4 ++++
4 files changed, 39 insertions(+), 29 deletions(-)
---
base-commit: c03c1a14507dfaf8b856c2608f9ac216021fc222
change-id: 20261019-vfct-regression-2142fc52852a
Best regards,
--
Mario Limonciello <mario.limonciello@amd.com>
^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH v7 1/3] PCI: Cache bridge firmware secondary bus number
2026-11-12 21:54 [PATCH v7 0/3] Fix VFCT matching after PCI bus renumbering Mario Limonciello
@ 2026-11-12 21:54 ` Mario Limonciello
2026-11-12 21:54 ` [PATCH v7 2/3] drm/amdgpu: Match VFCT using initial PCI " Mario Limonciello
1 sibling, 0 replies; 3+ messages in thread
From: Mario Limonciello @ 2026-11-12 21:54 UTC (permalink / raw)
To: Bjorn Helgaas, Alex Deucher, Christian König
Cc: Oz Tiram, linux-pci, linux-kernel, amd-gfx, dri-devel, Mario Limonciello
Drivers such as amdgpu and radeon need the bus number firmware assigned
to a device to match it against firmware tables like VFCT. The PCI core
may renumber buses (e.g. with pci=realloc), after which the runtime
number no longer reflects what firmware programmed.
Record the firmware secondary bus number on the bridge's struct pci_dev
the first time pci_read_bridge_windows() reads the bridge's bus numbers,
which happens before any renumbering. Devices behind the bridge can then
retrieve the original bus number via their upstream bridge.
Only store the value if it is usable: ignore unconfigured (0) and 0xff
secondaries. Use a separate "sampled" flag so that later rescans, which
would read the renumbered runtime value, never overwrite the cached
number, and a "valid" flag so users can tell whether anything was
recorded.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/pci/probe.c | 16 ++++++++++++++--
include/linux/pci.h | 4 ++++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 27008e2ea5afc..f20a4b8f7a23b 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -505,14 +505,26 @@ static void pci_read_bridge_mmio_pref(struct pci_dev *dev, struct resource *res,
static void pci_read_bridge_windows(struct pci_dev *bridge)
{
u32 buses;
+ u8 secondary;
+ u8 subordinate;
u16 io;
u32 pmem, tmp;
struct resource res;
pci_read_config_dword(bridge, PCI_PRIMARY_BUS, &buses);
res.flags = IORESOURCE_BUS;
- res.start = FIELD_GET(PCI_SECONDARY_BUS_MASK, buses);
- res.end = FIELD_GET(PCI_SUBORDINATE_BUS_MASK, buses);
+ secondary = FIELD_GET(PCI_SECONDARY_BUS_MASK, buses);
+ subordinate = FIELD_GET(PCI_SUBORDINATE_BUS_MASK, buses);
+ res.start = secondary;
+ res.end = subordinate;
+
+ if (!bridge->fw_sec_bus_sampled) {
+ bridge->fw_sec_bus_sampled = true;
+ if (secondary > 0 && secondary < 0xff) {
+ bridge->fw_sec_busnr = secondary;
+ bridge->fw_sec_bus_valid = true;
+ }
+ }
pci_info(bridge, "PCI bridge to %pR%s\n", &res,
bridge->transparent ? " (subtractive decode)" : "");
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 5ffcf5ce8c966..045157488b8e7 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -363,6 +363,8 @@ struct pci_dev {
struct pci_slot *slot; /* Physical slot this device is in */
unsigned int devfn; /* Encoded device & function index */
+ /* Firmware secondary bus number saved across bridge scan passes */
+ unsigned char fw_sec_busnr;
unsigned short vendor;
unsigned short device;
unsigned short subsystem_vendor;
@@ -414,6 +416,8 @@ struct pci_dev {
unsigned int pme_poll:1; /* Poll device's PME status bit */
unsigned int pinned:1; /* Whether this dev is pinned */
unsigned int config_rrs_sv:1; /* Config RRS software visibility */
+ unsigned int fw_sec_bus_valid:1; /* Firmware secondary bus number usable */
+ unsigned int fw_sec_bus_sampled:1; /* Firmware secondary bus number captured */
unsigned int imm_ready:1; /* Supports Immediate Readiness */
unsigned int d1_support:1; /* Low power state D1 is supported */
unsigned int d2_support:1; /* Low power state D2 is supported */
--
2.43.0
^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH v7 2/3] drm/amdgpu: Match VFCT using initial PCI bus number
2026-11-12 21:54 [PATCH v7 0/3] Fix VFCT matching after PCI bus renumbering Mario Limonciello
2026-11-12 21:54 ` [PATCH v7 1/3] PCI: Cache bridge firmware secondary bus number Mario Limonciello
@ 2026-11-12 21:54 ` Mario Limonciello
1 sibling, 0 replies; 3+ messages in thread
From: Mario Limonciello @ 2026-11-12 21:54 UTC (permalink / raw)
To: Bjorn Helgaas, Alex Deucher, Christian König
Cc: Oz Tiram, linux-pci, linux-kernel, amd-gfx, dri-devel,
Mario Limonciello, Reza Nikzad Chaleshori
VFCT records the PCI bus number from BIOS POST. The current bus number
can change after PCI core renumbers the bus, while accepting a mismatch
based only on device identity can select the wrong VFCT image when
matching devices are present. Compare against the bus number captured
from the firmware bus assignment before bridge renumbering.
Reported-by: Reza Nikzad Chaleshori <rezanikzadch@gmail.com>
Closes: https://lore.kernel.org/amd-gfx/20261014080523.186533-1-rezanikzadch@gmail.com/
Fixes: 11c141672045f ("drm/amdgpu: Fix VFCT bus number matching with soft filter")
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 23 ++++++++++-------------
1 file changed, 10 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index 08ed1eb695586..0ee4c6462c4d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -386,16 +386,17 @@ static bool amdgpu_read_disabled_bios(struct amdgpu_device *adev)
* VFCT entries contain the PCI bus number as recorded during BIOS POST.
* On systems where the kernel renumbers PCI buses (e.g. pci=realloc or
* resource conflicts), the runtime bus number may differ from the POST
- * value. Match by device identity (vendor + device + function) and use
- * the bus number as a preference: exact bus match is preferred, but when
- * the bus numbers disagree we accept the entry if the device identity
- * matches.
+ * value. Match using the bus number captured when the device was
+ * discovered, before any bus renumbering.
*
* Returns: 0 on match, -ENODEV on no match
*/
static int amdgpu_acpi_vfct_match(struct amdgpu_device *adev,
VFCT_IMAGE_HEADER *vhdr)
{
+ struct pci_dev *bridge = adev->pdev->bus->self;
+ unsigned char initial_bus;
+
/* Vendor and device IDs must always match */
if (vhdr->VendorID != adev->pdev->vendor ||
vhdr->DeviceID != adev->pdev->device)
@@ -405,16 +406,12 @@ static int amdgpu_acpi_vfct_match(struct amdgpu_device *adev,
vhdr->PCIFunction != PCI_FUNC(adev->pdev->devfn))
return -ENODEV;
- /* Exact bus number match - preferred */
- if (vhdr->PCIBus == adev->pdev->bus->number)
- return 0;
+ if (bridge && bridge->fw_sec_bus_valid)
+ initial_bus = bridge->fw_sec_busnr;
+ else
+ initial_bus = adev->pdev->bus->number;
- /* Bus mismatch but device identity matches (PCI renumbering case) */
- dev_notice(adev->dev,
- "VFCT bus number mismatch: table %u != runtime %u, matching by device identity (vendor 0x%04x device 0x%04x)\n",
- vhdr->PCIBus, adev->pdev->bus->number,
- adev->pdev->vendor, adev->pdev->device);
- return 0;
+ return vhdr->PCIBus == initial_bus ? 0 : -ENODEV;
}
static bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev)
--
2.43.0
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2026-11-12 23:42 UTC | newest]
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2026-11-12 21:54 [PATCH v7 0/3] Fix VFCT matching after PCI bus renumbering Mario Limonciello
2026-11-12 21:54 ` [PATCH v7 1/3] PCI: Cache bridge firmware secondary bus number Mario Limonciello
2026-11-12 21:54 ` [PATCH v7 2/3] drm/amdgpu: Match VFCT using initial PCI " Mario Limonciello
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