* [PATCH v5 1/4] dt-bindings: PCI: qcom: document the Shikra PCIe controller
2026-11-12 8:33 [PATCH v5 0/4] PCI: qcom: add Shikra PCIe and M.2 Wi-Fi/BT support Linghui Wu
@ 2026-11-12 8:33 ` Linghui Wu
2026-11-12 8:33 ` [PATCH v5 2/4] PCI: qcom: add support for " Linghui Wu
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Linghui Wu @ 2026-11-12 8:33 UTC (permalink / raw)
To: Bjorn Helgaas, Manivannan Sadhasivam, Bjorn Andersson
Cc: Lorenzo Pieralisi, Krzysztof Wilczyński, Konrad Dybcio,
Abel Vesa, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Dmitry Baryshkov, Sushrut Shree Trivedi, Miaoqing Pan,
Hangtian Zhu, Shuai Zhang, Cheng Jiang, Wei Deng, linux-pci,
linux-arm-msm, devicetree, linux-kernel
From: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
Add a dedicated schema for the PCIe controller found on Shikra.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
.../devicetree/bindings/arm/qcom-soc.yaml | 1 +
.../bindings/pci/qcom,pcie-shikra.yaml | 192 ++++++++++++++++++
2 files changed, 193 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-shikra.yaml
diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml
index 179aadc86a9f..72e0f1a824c6 100644
--- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml
@@ -43,6 +43,7 @@ properties:
- pattern: "^qcom,sar[0-9]+[a-z]?-.*$"
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
- pattern: "^qcom,(eliza|kaanapali|kuno|glymur|hawi|mahua|maili|milos|nord|shikra)-.+$"
+ - const: qcom,pcie-shikra
# Legacy namings - variations of existing patterns/compatibles are OK,
# but do not add completely new entries to these:
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-shikra.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-shikra.yaml
new file mode 100644
index 000000000000..69463dae9f18
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-shikra.yaml
@@ -0,0 +1,192 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-shikra.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Shikra PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description:
+ Qualcomm Shikra SoC PCIe root complex controller is based on the Synopsys
+ DesignWare PCIe IP.
+
+properties:
+ compatible:
+ const: qcom,pcie-shikra
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 11
+ maxItems: 11
+
+ clock-names:
+ items:
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: sleep # PCIe Sleep clock
+ - const: throttle_core # PCIe throttle core clock
+ - const: throttle_xo # PCIe throttle XO core clock
+ - const: qmip # QMIP PCIe AHB clock
+ - const: ddrss # PCIE MEMNOC clock
+ - const: tile # AXI SYS NoC clock
+
+ interrupts:
+ minItems: 8
+ maxItems: 9
+
+ interrupt-names:
+ minItems: 8
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+ - const: global
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci # PCIe core reset
+
+required:
+ - power-domains
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,shikra-gcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,shikra.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie: pcie@45e8000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-shikra";
+ reg = <0x0 0x045e8000 0x0 0x3000>,
+ <0x0 0x60000000 0x0 0xf1d>,
+ <0x0 0x60000f20 0x0 0xa8>,
+ <0x0 0x60001000 0x0 0x1000>,
+ <0x0 0x60100000 0x0 0x100000>,
+ <0x0 0x045eb000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+ bus-range = <0x00 0xff>;
+
+ linux,pci-domain = <0>;
+ num-lanes = <1>;
+
+ interrupts = <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>,
+ <0 0 0 2 &intc GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>,
+ <0 0 0 3 &intc GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>,
+ <0 0 0 4 &intc GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_PCIE_AUX_CLK>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_PCIE_SLEEP_CLK>,
+ <&gcc GCC_PCIE_THROTTLE_CORE_CLK>,
+ <&gcc GCC_PCIE_THROTTLE_XO_CLK>,
+ <&gcc GCC_QMIP_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_DDRSS_MEMNOC_PCIE_SF_CLK>,
+ <&gcc GCC_PCIE_TILE_AXI_SYS_NOC_CLK>;
+
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "sleep",
+ "throttle_core",
+ "throttle_xo",
+ "qmip",
+ "ddrss",
+ "tile";
+ assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&system_noc MASTER_PCIE2_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
+ <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_PCIE2_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ iommu-map = <0x0 &apps_smmu 0x800 0x1>,
+ <0x100 &apps_smmu 0x801 0x1>;
+
+ resets = <&gcc GCC_PCIE_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc GCC_PCIE_GDSC>;
+
+ max-link-speed = <2>;
+ };
+
+ };
--
2.43.0
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v5 2/4] PCI: qcom: add support for the Shikra PCIe controller
2026-11-12 8:33 [PATCH v5 0/4] PCI: qcom: add Shikra PCIe and M.2 Wi-Fi/BT support Linghui Wu
2026-11-12 8:33 ` [PATCH v5 1/4] dt-bindings: PCI: qcom: document the Shikra PCIe controller Linghui Wu
@ 2026-11-12 8:33 ` Linghui Wu
2026-11-12 8:33 ` [PATCH v5 3/4] arm64: dts: qcom: shikra: add PCIe PHY and controller nodes Linghui Wu
2026-11-12 8:33 ` [PATCH v5 4/4] arm64: dts: qcom: shikra-iqs: add M.2 Wi-Fi and Bluetooth overlay Linghui Wu
3 siblings, 0 replies; 5+ messages in thread
From: Linghui Wu @ 2026-11-12 8:33 UTC (permalink / raw)
To: Bjorn Helgaas, Manivannan Sadhasivam, Bjorn Andersson
Cc: Lorenzo Pieralisi, Krzysztof Wilczyński, Konrad Dybcio,
Abel Vesa, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Dmitry Baryshkov, Sushrut Shree Trivedi, Miaoqing Pan,
Hangtian Zhu, Shuai Zhang, Cheng Jiang, Wei Deng, linux-pci,
linux-arm-msm, devicetree, linux-kernel
From: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
Add support for the PCIe controller found on the Qualcomm Shikra platform.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index eba1b2cb30f0..7573c509d7ce 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -2623,6 +2623,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-sc8280xp", .data = &cfg_sc8280xp },
{ .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
{ .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
+ { .compatible = "qcom,pcie-shikra", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },
--
2.43.0
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v5 3/4] arm64: dts: qcom: shikra: add PCIe PHY and controller nodes
2026-11-12 8:33 [PATCH v5 0/4] PCI: qcom: add Shikra PCIe and M.2 Wi-Fi/BT support Linghui Wu
2026-11-12 8:33 ` [PATCH v5 1/4] dt-bindings: PCI: qcom: document the Shikra PCIe controller Linghui Wu
2026-11-12 8:33 ` [PATCH v5 2/4] PCI: qcom: add support for " Linghui Wu
@ 2026-11-12 8:33 ` Linghui Wu
2026-11-12 8:33 ` [PATCH v5 4/4] arm64: dts: qcom: shikra-iqs: add M.2 Wi-Fi and Bluetooth overlay Linghui Wu
3 siblings, 0 replies; 5+ messages in thread
From: Linghui Wu @ 2026-11-12 8:33 UTC (permalink / raw)
To: Bjorn Helgaas, Manivannan Sadhasivam, Bjorn Andersson
Cc: Lorenzo Pieralisi, Krzysztof Wilczyński, Konrad Dybcio,
Abel Vesa, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Dmitry Baryshkov, Sushrut Shree Trivedi, Miaoqing Pan,
Hangtian Zhu, Shuai Zhang, Cheng Jiang, Wei Deng, linux-pci,
linux-arm-msm, devicetree, linux-kernel
From: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
Shikra supports a single PCIe instance with a 5 GT/s x1 lane. Add the
PCIe controller and PHY nodes for this instance.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 158 +++++++++++++++++++++++++++
1 file changed, 158 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 0a95ad5a5582..fa9b0d41a576 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -1285,6 +1285,164 @@ rng: rng@4454000 {
reg = <0x0 0x04454000 0x0 0x1000>;
};
+ pcie: pcie@45e8000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-shikra";
+ reg = <0x0 0x045e8000 0x0 0x3000>,
+ <0x0 0x60000000 0x0 0xf1d>,
+ <0x0 0x60000f20 0x0 0xa8>,
+ <0x0 0x60001000 0x0 0x1000>,
+ <0x0 0x60100000 0x0 0x100000>,
+ <0x0 0x045eb000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+ bus-range = <0x00 0xff>;
+
+ linux,pci-domain = <0>;
+ num-lanes = <1>;
+
+ interrupts = <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-parent = <&intc>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ interrupt-map = <0 0 0 1 &intc 0 0 0 499 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 500 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 501 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 502 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ #interrupt-cells = <1>;
+
+ clocks = <&gcc GCC_PCIE_AUX_CLK>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_PCIE_SLEEP_CLK>,
+ <&gcc GCC_PCIE_THROTTLE_CORE_CLK>,
+ <&gcc GCC_PCIE_THROTTLE_XO_CLK>,
+ <&gcc GCC_QMIP_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_DDRSS_MEMNOC_PCIE_SF_CLK>,
+ <&gcc GCC_PCIE_TILE_AXI_SYS_NOC_CLK>;
+
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "sleep",
+ "throttle_core",
+ "throttle_xo",
+ "qmip",
+ "ddrss",
+ "tile";
+ assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&system_noc MASTER_PCIE2_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
+ <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_PCIE2_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ iommu-map = <0x0 &apps_smmu 0x800 0x1>,
+ <0x100 &apps_smmu 0x801 0x1>;
+
+ resets = <&gcc GCC_PCIE_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc GCC_PCIE_GDSC>;
+
+ max-link-speed = <2>;
+
+ operating-points-v2 = <&pcie_opp_table>;
+
+ status = "disabled";
+
+ pcie_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* GEN 1 x1 */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmpd_opp_nom>;
+ opp-peak-kBps = <250000 1>;
+ opp-level = <1>;
+ };
+
+ /* GEN 2 x1 */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ opp-peak-kBps = <500000 1>;
+ opp-level = <2>;
+ };
+ };
+
+ pcie_port0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ bus-range = <0x01 0x8>;
+
+ phys = <&pcie_phy>;
+ };
+ };
+ pcie_phy: phy@45ee000 {
+ compatible = "qcom,shikra-qmp-gen2x1-pcie-phy";
+ reg = <0x0 0x045ee000 0x0 0x1000>;
+
+ clocks = <&gcc GCC_PCIE_AUX_CLK>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_EN>,
+ <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
+ <&gcc GCC_PCIE_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+
+ resets = <&gcc GCC_PCIE_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
rpm_msg_ram: sram@45f0000 {
compatible = "qcom,rpm-msg-ram", "mmio-sram";
reg = <0x0 0x045f0000 0x0 0x7000>;
--
2.43.0
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v5 4/4] arm64: dts: qcom: shikra-iqs: add M.2 Wi-Fi and Bluetooth overlay
2026-11-12 8:33 [PATCH v5 0/4] PCI: qcom: add Shikra PCIe and M.2 Wi-Fi/BT support Linghui Wu
` (2 preceding siblings ...)
2026-11-12 8:33 ` [PATCH v5 3/4] arm64: dts: qcom: shikra: add PCIe PHY and controller nodes Linghui Wu
@ 2026-11-12 8:33 ` Linghui Wu
3 siblings, 0 replies; 5+ messages in thread
From: Linghui Wu @ 2026-11-12 8:33 UTC (permalink / raw)
To: Bjorn Helgaas, Manivannan Sadhasivam, Bjorn Andersson
Cc: Lorenzo Pieralisi, Krzysztof Wilczyński, Konrad Dybcio,
Abel Vesa, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Dmitry Baryshkov, Sushrut Shree Trivedi, Miaoqing Pan,
Hangtian Zhu, Shuai Zhang, Cheng Jiang, Wei Deng, linux-pci,
linux-arm-msm, devicetree, linux-kernel, Linghui Wu
Add an overlay for M.2 Key-E Wi-Fi and Bluetooth modules on the
Qualcomm Shikra IQS EVK.
The Shikra product design supports either the onboard Apache WCN3988
path or the M.2 HSP Cologne path at a time. The overlay describes the
board after hardware rework selects the M.2 path. Disable the inherited
onboard Wi-Fi and Bluetooth nodes when this overlay is selected.
Describe the PCIe and UART connections through the M.2 connector, the
3.3 V supply, the W_DISABLE signals and the PCIe reset signal.
The series has been validated on Shikra hardware.
Link: https://lore.kernel.org/r/20261102045815.2938940-1-linghui.wu@oss.qualcomm.com
Co-developed-by: Wei Deng <wei.deng@oss.qualcomm.com>
Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
Signed-off-by: Linghui Wu <linghui.wu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/Makefile | 2 +
.../dts/qcom/shikra-iqs-evk-m2-wifi-bt.dtso | 122 ++++++++++++++++++
2 files changed, 124 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/shikra-iqs-evk-m2-wifi-bt.dtso
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 8329c06b60a3..037dbe8a39ce 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -410,10 +410,12 @@ dtb-$(CONFIG_ARCH_QCOM) += shikra-iqs-evk.dtb
shikra-cqm-evk-imx577-camera-dtbs := shikra-cqm-evk.dtb shikra-cqm-cqs-evk-imx577-camera.dtbo
shikra-cqs-evk-imx577-camera-dtbs := shikra-cqs-evk.dtb shikra-cqm-cqs-evk-imx577-camera.dtbo
shikra-iqs-evk-imx577-camera-dtbs := shikra-iqs-evk.dtb shikra-iqs-evk-imx577-camera.dtbo
+shikra-iqs-evk-m2-wifi-bt-dtbs := shikra-iqs-evk.dtb shikra-iqs-evk-m2-wifi-bt.dtbo
dtb-$(CONFIG_ARCH_QCOM) += shikra-cqm-evk-imx577-camera.dtb
dtb-$(CONFIG_ARCH_QCOM) += shikra-cqs-evk-imx577-camera.dtb
dtb-$(CONFIG_ARCH_QCOM) += shikra-iqs-evk-imx577-camera.dtb
+dtb-$(CONFIG_ARCH_QCOM) += shikra-iqs-evk-m2-wifi-bt.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb
diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk-m2-wifi-bt.dtso b/arch/arm64/boot/dts/qcom/shikra-iqs-evk-m2-wifi-bt.dtso
new file mode 100644
index 000000000000..ef0f197a53f8
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk-m2-wifi-bt.dtso
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+&{/} {
+ m2_keye_3p3: regulator-m2-keye-3p3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_3P3_KEYE";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&expander3 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ wifi-bt-connector {
+ compatible = "pcie-m2-e-connector";
+
+ vpcie3v3-supply = <&m2_keye_3p3>;
+ w-disable1-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
+ w-disable2-gpios = <&tlmm 60 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ m2_e_pcie_ep: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&pcie_port0_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ m2_e_uart_ep: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&uart8_ep>;
+ };
+ };
+ };
+ };
+};
+
+&{/wcn3988-pmu} {
+ status = "disabled";
+};
+
+&pcie {
+ iommu-map = <0x0 &apps_smmu 0x0800 0x0 0x1>,
+ <0x100 &apps_smmu 0x0801 0x0 0x1>;
+ pinctrl-0 = <&pcie_default_state>;
+ pinctrl-names = "default";
+ vddpe-3v3-supply = <&m2_keye_3p3>;
+ wake-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&pcie_phy {
+ vdda-phy-supply = <&pm8150_l12>;
+ vdda-pll-supply = <&pm8150_l9>;
+
+ status = "okay";
+};
+
+&pcie_port0 {
+ compatible = "pciclass,0604";
+ reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>;
+
+ port {
+ pcie_port0_ep: endpoint {
+ remote-endpoint = <&m2_e_pcie_ep>;
+ };
+ };
+};
+
+&uart8 {
+ bluetooth {
+ status = "disabled";
+ };
+
+ port {
+ uart8_ep: endpoint {
+ remote-endpoint = <&m2_e_uart_ep>;
+ };
+ };
+};
+
+&tlmm {
+ pcie_default_state: pcie-default-state {
+ clkreq-pins {
+ pins = "gpio117";
+ function = "pcie0_clk_req_n";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio119";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+};
+
+&wifi {
+ status = "disabled";
+};
--
2.43.0
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