[PATCH v3 0/2] ARM: dts: zynq: Add ALINX AX7Z020B development board

[PATCH v3 0/2] ARM: dts: zynq: Add ALINX AX7Z020B development board

[Pufan Jin]

Add devicetree support for the ALINX AX7Z020B board, built around the
ALINX AC7Z020 system on module with a Zynq-7000 (XC7Z020-2CLG400I) SoC.

Changes in v3:
- Drop the vendor website Link: tags (Krzysztof Kozlowski).
- Drop the empty bootargs property (Krzysztof Kozlowski).
- Rename the USB PHY node from phy0 to phy, as there is only one USB PHY
  on the board (Krzysztof Kozlowski).
- Keep the explicit mdio node under gem0, as requested during the v1
  review and reviewed by Andrew Lunn in v2.  dtc W=1 flags the parent
  node's inherited #address-cells/#size-cells.  DT schema validation
  reports the same Zynq-7000 diagnostics as zynq-zybo-z7.  The MDIO
  layout was also verified on hardware.
- Sort I2C child nodes by address and reorder status/reg properties.
- Add Krzysztof's Acked-by to patch 1.

The "alinx" vendor prefix is already queued in linux-next as commit
1f06cd374a60 ("dt-bindings: vendor-prefixes: Add ALINX vendor prefix"),
so it is not part of this series.

Tested on hardware before the DTS style reordering: SD boot, UART
console, SD card, GbE (900+ Mbps and LED hardware offload), dual CAN,
I2C, QSPI and XADC.

Pufan Jin (2):
  dt-bindings: soc: xilinx: Add ALINX AX7Z020B board
  ARM: dts: zynq: Add ALINX AX7Z020B development board

 .../bindings/soc/xilinx/xilinx.yaml           |   5 +
 arch/arm/boot/dts/xilinx/Makefile             |   1 +
 .../boot/dts/xilinx/zynq-alinx-ac7z020.dtsi   |  71 +++++++++
 .../boot/dts/xilinx/zynq-alinx-ax7z020b.dts   | 146 ++++++++++++++++++
 4 files changed, 223 insertions(+)
 create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi
 create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts

Range-diff against v2:
1:  f44b8dc6e6 ! 1:  ca50a01108 dt-bindings: soc: xilinx: Add ALINX AX7Z020B board
    @@ Commit message
         Document the ALINX AX7Z020B development board, built around the ALINX
         AC7Z020 system on module.
     
    -    Link: https://www.alinx.com/
         Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
    +    Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
     
      ## Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml ##
     @@ Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml: properties:
2:  a985ee80d4 ! 2:  477061f136 ARM: dts: zynq: Add ALINX AX7Z020B development board
    @@ Commit message
         always accessible from the PS, so expose these channels via the
         driver's xlnx,channels property.
     
    -    Link: https://www.alinx.com/
         Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
     
      ## arch/arm/boot/dts/xilinx/Makefile ##
    @@ arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi (new)
     +
     +&qspi {
     +	bootph-all;
    -+	status = "okay";
     +	num-cs = <1>;
     +
    ++	status = "okay";
    ++
     +	flash@0 {
     +		compatible = "jedec,spi-nor";
     +		reg = <0>;
    @@ arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi (new)
     +			#size-cells = <1>;
     +
     +			partition@0 {
    -+				label = "boot";
     +				reg = <0x00000000 0x00500000>;
    ++				label = "boot";
     +			};
     +
     +			partition@500000 {
    -+				label = "bootenv";
     +				reg = <0x00500000 0x00020000>;
    ++				label = "bootenv";
     +			};
     +
     +			partition@520000 {
    -+				label = "image";
     +				reg = <0x00520000 0x00a80000>;
    ++				label = "image";
     +			};
     +
     +			partition@fa0000 {
    -+				label = "spare";
     +				reg = <0x00fa0000 0x01060000>;
    ++				label = "spare";
     +			};
     +		};
     +	};
    @@ arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts (new)
     +	};
     +
     +	chosen {
    -+		bootargs = "";
     +		stdout-path = "serial0:115200n8";
     +	};
     +
    -+	usb_phy0: phy0 {
    ++	usb_phy0: phy {
     +		compatible = "usb-nop-xceiv";
     +		#phy-cells = <0>;
     +		reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
    @@ arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts (new)
     +};
     +
     +&gem0 {
    -+	status = "okay";
     +	phy-mode = "rgmii-id";
     +	phy-handle = <&ethernet_phy>;
     +
    ++	status = "okay";
    ++
     +	mdio {
     +		#address-cells = <1>;
     +		#size-cells = <0>;
    @@ arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts (new)
     +};
     +
     +&i2c0 {
    -+	status = "okay";
     +	clock-frequency = <100000>;
     +
    ++	status = "okay";
    ++
    ++	temperature-sensor@48 {
    ++		compatible = "national,lm75";
    ++		reg = <0x48>;
    ++	};
    ++
     +	eeprom@50 {
     +		compatible = "atmel,24c04";
     +		reg = <0x50>;
    @@ arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts (new)
     +		compatible = "dallas,ds1338";
     +		reg = <0x68>;
     +	};
    -+
    -+	temperature-sensor@48 {
    -+		compatible = "national,lm75";
    -+		reg = <0x48>;
    -+	};
     +};
     +
     +&sdhci0 {
     +	bootph-all;
    -+	status = "okay";
     +	disable-wp;
    ++
    ++	status = "okay";
     +};
     +
     +&uart0 {
    @@ arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts (new)
     +
     +&uart1 {
     +	bootph-all;
    ++
     +	status = "okay";
     +};
     +
     +&usb0 {
    -+	status = "okay";
     +	dr_mode = "host";
     +	usb-phy = <&usb_phy0>;
    ++
    ++	status = "okay";
     +};

-- 
2.56.0

[PATCH v3 1/2] dt-bindings: soc: xilinx: Add ALINX AX7Z020B board

[Pufan Jin]

Document the ALINX AX7Z020B development board, built around the ALINX
AC7Z020 system on module.

Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
index c9f99e0df2..e3bd3d7660 100644
--- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
+++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
@@ -34,6 +34,11 @@ properties:
               - xlnx,zynq-zc770-xm013
           - const: xlnx,zynq-7000
 
+      - items:
+          - const: alinx,ax7z020b
+          - const: alinx,ac7z020
+          - const: xlnx,zynq-7000
+
       - items:
           - const: avnet,zynq-microzed
           - const: xlnx,zynq-microzed
-- 
2.56.0

[PATCH v3 2/2] ARM: dts: zynq: Add ALINX AX7Z020B development board

[Pufan Jin]

Add devicetree support for the ALINX AX7Z020B development board.
The board is built around the ALINX AC7Z020 system on module with a
Zynq-7000 (XC7Z020-2CLG400I) SoC, 1 GB DDR3 SDRAM and 32 MB QSPI
flash, and provides Gigabit Ethernet (JLSemi JL2121 PHY), USB 2.0
host, MicroSD slot, dual CAN buses (SN65HVD232 transceivers on
MIO 10-13), I2C RTC/EEPROM/LM75 and the serial console on UART1.
DevCFG FPGA manager is also enabled.

The two SMA AD inputs and the spare differential pair are wired to
XADC aux channels VAUX1, VAUX9 and VAUX12. The XADC hard macro is
always accessible from the PS, so expose these channels via the
driver's xlnx,channels property.

Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
---
 arch/arm/boot/dts/xilinx/Makefile             |   1 +
 .../boot/dts/xilinx/zynq-alinx-ac7z020.dtsi   |  71 +++++++++
 .../boot/dts/xilinx/zynq-alinx-ax7z020b.dts   | 146 ++++++++++++++++++
 3 files changed, 218 insertions(+)
 create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi
 create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts

diff --git a/arch/arm/boot/dts/xilinx/Makefile b/arch/arm/boot/dts/xilinx/Makefile
index 9233e539b1..5c4bcd9492 100644
--- a/arch/arm/boot/dts/xilinx/Makefile
+++ b/arch/arm/boot/dts/xilinx/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_ZYNQ) += \
+	zynq-alinx-ax7z020b.dtb \
 	zynq-cc108.dtb \
 	zynq-ebaz4205.dtb \
 	zynq-microzed.dtb \
diff --git a/arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi b/arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi
new file mode 100644
index 0000000000..d60e58657b
--- /dev/null
+++ b/arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS for ALINX AC7Z020 System on Module
+ *
+ * Copyright (C) 2026 Pufan Jin <cyan2254650260@gmail.com>
+ */
+
+#include "zynq-7000.dtsi"
+
+/ {
+	compatible = "alinx,ac7z020", "xlnx,zynq-7000";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x40000000>;
+	};
+
+	pmu@f8891000 {
+		interrupt-affinity = <&cpu0>, <&cpu1>;
+	};
+};
+
+&clkc {
+	ps-clk-frequency = <33333333>;
+};
+
+&devcfg {
+	status = "okay";
+};
+
+&qspi {
+	bootph-all;
+	num-cs = <1>;
+
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				reg = <0x00000000 0x00500000>;
+				label = "boot";
+			};
+
+			partition@500000 {
+				reg = <0x00500000 0x00020000>;
+				label = "bootenv";
+			};
+
+			partition@520000 {
+				reg = <0x00520000 0x00a80000>;
+				label = "image";
+			};
+
+			partition@fa0000 {
+				reg = <0x00fa0000 0x01060000>;
+				label = "spare";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts b/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts
new file mode 100644
index 0000000000..f232371a51
--- /dev/null
+++ b/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS for ALINX AX7Z020B Development Board
+ *
+ * Copyright (C) 2026 Pufan Jin <cyan2254650260@gmail.com>
+ */
+
+/dts-v1/;
+#include "zynq-alinx-ac7z020.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "ALINX AX7Z020B Development Board";
+	compatible = "alinx,ax7z020b", "alinx,ac7z020", "xlnx,zynq-7000";
+
+	aliases {
+		ethernet0 = &gem0;
+		serial0 = &uart1;
+		serial1 = &uart0;
+		mmc0 = &sdhci0;
+		spi0 = &qspi;
+		i2c0 = &i2c0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	usb_phy0: phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&adc {
+	xlnx,channels {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* AD1: XADC_AD1P/N, E17/D18 */
+		channel@2 {
+			reg = <2>;
+		};
+
+		/* AD9: XADC_AD9P/N, E18/E19 */
+		channel@a {
+			reg = <10>;
+		};
+
+		/* Spare pair: XADC_AD12P/N, F19/F20 */
+		channel@d {
+			reg = <13>;
+		};
+	};
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&gem0 {
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethernet_phy: ethernet-phy@1 {
+			reg = <1>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					color = <LED_COLOR_ID_GREEN>;
+					function = LED_FUNCTION_LAN;
+					default-state = "keep";
+				};
+
+				led@1 {
+					reg = <1>;
+					color = <LED_COLOR_ID_YELLOW>;
+					function = LED_FUNCTION_ACTIVITY;
+					default-state = "keep";
+				};
+			};
+		};
+	};
+};
+
+&i2c0 {
+	clock-frequency = <100000>;
+
+	status = "okay";
+
+	temperature-sensor@48 {
+		compatible = "national,lm75";
+		reg = <0x48>;
+	};
+
+	eeprom@50 {
+		compatible = "atmel,24c04";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+
+	rtc@68 {
+		compatible = "dallas,ds1338";
+		reg = <0x68>;
+	};
+};
+
+&sdhci0 {
+	bootph-all;
+	disable-wp;
+
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	bootph-all;
+
+	status = "okay";
+};
+
+&usb0 {
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
+
+	status = "okay";
+};
-- 
2.56.0