Re: [PATCH 13/24] PCI: dwc: Add ZTE ZX279128S host controller driver

[Navid Ghahremani <ghahramani.navid@gmail.com>]

Hi Stefan,

Stefan Dösinger wrote:
> If this is a clock control it would be better to write a clock driver that
> manages the crm2 region and exposes a proper clock handle.

That is done since v2. crm2 has its own clock and reset provider and
the PCIe driver uses the clock and reset handles.

> For the phy parts that are part of topcrm: drivers/phy has PCIe PHY drivers.

The PHY setup moved into a PHY driver with #phy-cells on topcrm, so the
PCIe driver doesn't write topcrm registers anymore.

> By and large the zx279128s_pcie_init_crm has a bad code smell: It looks like
> an LLM translation of ZTE's code to me without understanding what the
> registers actually do.

That is fair. There is no public register documentation for this SoC,
so that function followed ZTE's code, and I got part of it wrong.
Agustin found that two of the writes went to the wrong block and had no
effect, see the v2 11/24 thread. For several of the PHY writes I only
have ZTE's values and no explanation yet. I will try to work them out
before the PCIe series, and the patch will say which values are just
copied from ZTE.

Best regards,
Navid