* [PATCH RFC 01/15] dt-bindings: i2c: qcom,i2c-cci: Add Hawi compatible
2026-09-23 11:02 [PATCH RFC 00/15] Add CAMSS and S5KJN5 sensor support for Qualcomm Hawi and Maili Nihal Kumar Gupta
@ 2026-09-23 11:02 ` Nihal Kumar Gupta
2026-09-23 11:02 ` [PATCH RFC 02/15] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add Hawi and Maili compatibles Nihal Kumar Gupta
` (13 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Nihal Kumar Gupta @ 2026-09-23 11:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma, Nihal Kumar Gupta
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Document the Camera Control Interface (CCI) compatible for the Qualcomm
Hawi platform. Like other recent platforms it requires two clocks, so
add it to the corresponding clocks constraint as well.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
index 1e8def25ec0ec1ef6b34859709d10a2a36fe36f5..b2b4d4bcf780792515ec153c873bace1764fb3e3 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
@@ -27,6 +27,7 @@ properties:
- items:
- enum:
- qcom,glymur-cci
+ - qcom,hawi-cci
- qcom,kaanapali-cci
- qcom,milos-cci
- qcom,qcm2290-cci
@@ -137,6 +138,7 @@ allOf:
contains:
enum:
- qcom,glymur-cci
+ - qcom,hawi-cci
- qcom,kaanapali-cci
- qcom,qcm2290-cci
- qcom,qcs8300-cci
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH RFC 02/15] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add Hawi and Maili compatibles
2026-09-23 11:02 [PATCH RFC 00/15] Add CAMSS and S5KJN5 sensor support for Qualcomm Hawi and Maili Nihal Kumar Gupta
2026-09-23 11:02 ` [PATCH RFC 01/15] dt-bindings: i2c: qcom,i2c-cci: Add Hawi compatible Nihal Kumar Gupta
@ 2026-09-23 11:02 ` Nihal Kumar Gupta
2026-09-23 12:11 ` Bryan O'Donoghue
2026-09-23 11:02 ` [PATCH RFC 03/15] dt-bindings: media: Add CAMSS device for Hawi Nihal Kumar Gupta
` (12 subsequent siblings)
14 siblings, 1 reply; 24+ messages in thread
From: Nihal Kumar Gupta @ 2026-09-23 11:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma, Nihal Kumar Gupta
Hawi and Maili integrate the same CSIPHY IP as Kaanapali with an
identical register interface. Add qcom,hawi-csi2-phy and
qcom,maili-csi2-phy falling back to qcom,kaanapali-csi2-phy.
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
.../devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
index 24ca06b97656077cf168e72b2a32f493d9c06af2..84d70e3e5783980bc76807869f00e7d112a046ae 100644
--- a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
@@ -16,9 +16,15 @@ description:
properties:
compatible:
- enum:
- - qcom,kaanapali-csi2-phy
- - qcom,x1e80100-csi2-phy
+ oneOf:
+ - enum:
+ - qcom,kaanapali-csi2-phy
+ - qcom,x1e80100-csi2-phy
+ - items:
+ - enum:
+ - qcom,hawi-csi2-phy
+ - qcom,maili-csi2-phy
+ - const: qcom,kaanapali-csi2-phy
reg:
maxItems: 1
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH RFC 02/15] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add Hawi and Maili compatibles
2026-09-23 11:02 ` [PATCH RFC 02/15] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add Hawi and Maili compatibles Nihal Kumar Gupta
@ 2026-09-23 12:11 ` Bryan O'Donoghue
0 siblings, 0 replies; 24+ messages in thread
From: Bryan O'Donoghue @ 2026-09-23 12:11 UTC (permalink / raw)
To: Nihal Kumar Gupta, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma
On 23/09/2026 12:02, Nihal Kumar Gupta wrote:
> Hawi and Maili integrate the same CSIPHY IP as Kaanapali with an
> identical register interface. Add qcom,hawi-csi2-phy and
> qcom,maili-csi2-phy falling back to qcom,kaanapali-csi2-phy.
>
> Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
> ---
> .../devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
> index 24ca06b97656077cf168e72b2a32f493d9c06af2..84d70e3e5783980bc76807869f00e7d112a046ae 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
> @@ -16,9 +16,15 @@ description:
>
> properties:
> compatible:
> - enum:
> - - qcom,kaanapali-csi2-phy
> - - qcom,x1e80100-csi2-phy
> + oneOf:
> + - enum:
> + - qcom,kaanapali-csi2-phy
> + - qcom,x1e80100-csi2-phy
> + - items:
> + - enum:
> + - qcom,hawi-csi2-phy
> + - qcom,maili-csi2-phy
> + - const: qcom,kaanapali-csi2-phy
>
> reg:
> maxItems: 1
>
> --
> 2.34.1
>
I don't think you should depend on kaanapali unless you have a good
reason to.
---
bod
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH RFC 03/15] dt-bindings: media: Add CAMSS device for Hawi
2026-09-23 11:02 [PATCH RFC 00/15] Add CAMSS and S5KJN5 sensor support for Qualcomm Hawi and Maili Nihal Kumar Gupta
2026-09-23 11:02 ` [PATCH RFC 01/15] dt-bindings: i2c: qcom,i2c-cci: Add Hawi compatible Nihal Kumar Gupta
2026-09-23 11:02 ` [PATCH RFC 02/15] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add Hawi and Maili compatibles Nihal Kumar Gupta
@ 2026-09-23 11:02 ` Nihal Kumar Gupta
2026-09-23 11:02 ` [PATCH RFC 04/15] dt-bindings: media: Add CAMSS device for Maili Nihal Kumar Gupta
` (11 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Nihal Kumar Gupta @ 2026-09-23 11:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma, Nihal Kumar Gupta
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add bindings for Camera Subsystem (CAMSS) on the Qualcomm Hawi platform.
The Hawi platform provides:
- 6 x CSIPHY (CSI Physical Layer)
- 3 x TPG (Test Pattern Generator)
- 3 x CSID (CSI Decoder)
- 2 x CSID Lite
- 3 x VFE (Video Front End), 5 RDI per VFE
- 2 x VFE Lite, 4 RDI per VFE Lite
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Co-developed-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
.../devicetree/bindings/media/qcom,hawi-camss.yaml | 305 +++++++++++++++++++++
1 file changed, 305 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,hawi-camss.yaml b/Documentation/devicetree/bindings/media/qcom,hawi-camss.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..5bf0dca3d24621bfc4a09feb8e5037a925869751
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,hawi-camss.yaml
@@ -0,0 +1,305 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,hawi-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Hawi Camera Subsystem (CAMSS)
+
+maintainers:
+ - Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,hawi-camss
+
+ reg:
+ maxItems: 13
+
+ reg-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csitpg0
+ - const: csitpg1
+ - const: csitpg2
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ clocks:
+ maxItems: 26
+
+ clock-names:
+ items:
+ - const: camnoc_nrt_axi
+ - const: camnoc_rt_axi
+ - const: camnoc_dcd_xo
+ - const: cpas_ahb
+ - const: cpas_fast_ahb
+ - const: cpas_mnoc_hf
+ - const: cpas_mnoc_sf
+ - const: cpas_vfe0
+ - const: cpas_vfe1
+ - const: cpas_vfe2
+ - const: cpas_vfe_lite
+ - const: csid
+ - const: csid_csiphy_rx
+ - const: gcc_axi_hf
+ - const: gcc_axi_sf
+ - const: vfe0
+ - const: vfe0_fast_ahb
+ - const: vfe1
+ - const: vfe1_fast_ahb
+ - const: vfe2
+ - const: vfe2_fast_ahb
+ - const: vfe_lite
+ - const: vfe_lite_ahb
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+ - const: qdss_debug_xo
+
+ interrupts:
+ maxItems: 10
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_mnoc
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ items:
+ - description: IFE0 GDSC - Global Distributed Switch Controller for IFE0.
+ - description: IFE1 GDSC - Global Distributed Switch Controller for IFE1.
+ - description: IFE2 GDSC - Global Distributed Switch Controller for IFE2.
+ - description: Titan GDSC - Global Distributed Switch Controller for the entire camss.
+
+ power-domain-names:
+ items:
+ - const: ife0
+ - const: ife1
+ - const: ife2
+ - const: top
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ patternProperties:
+ "^port@[0-5]$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input ports for receiving CSI data on CSIPHY 0-5.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,hawi-gcc.h>
+ #include <dt-bindings/clock/qcom,hawi-camcc.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,hawi-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isp@9253000 {
+ compatible = "qcom,hawi-camss";
+
+ reg = <0x0 0x09253000 0x0 0x5e80>,
+ <0x0 0x09263000 0x0 0x5e80>,
+ <0x0 0x09273000 0x0 0x5e80>,
+ <0x0 0x092d3000 0x0 0x3880>,
+ <0x0 0x092e7000 0x0 0x3880>,
+ <0x0 0x093fd000 0x0 0x400>,
+ <0x0 0x093fe000 0x0 0x400>,
+ <0x0 0x093ff000 0x0 0x400>,
+ <0x0 0x09151000 0x0 0x20000>,
+ <0x0 0x09171000 0x0 0x20000>,
+ <0x0 0x09191000 0x0 0x20000>,
+ <0x0 0x092dc000 0x0 0x6800>,
+ <0x0 0x092f0000 0x0 0x6800>;
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csitpg0",
+ "csitpg1",
+ "csitpg2",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_DCD_XO_CLK>,
+ <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TITAN_MNOC_HF_CLK>,
+ <&camcc CAM_CC_TITAN_MNOC_SF_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
+ clock-names = "camnoc_nrt_axi",
+ "camnoc_rt_axi",
+ "camnoc_dcd_xo",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_mnoc_hf",
+ "cpas_mnoc_sf",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe2",
+ "cpas_vfe_lite",
+ "csid",
+ "csid_csiphy_rx",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "qdss_debug_xo";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc";
+
+ iommus = <&apps_smmu 0x1800 0x00>;
+
+ power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
+ <&camcc CAM_CC_TFE_1_GDSC>,
+ <&camcc CAM_CC_TFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ camss_csiphy0_ep: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csiphy0_out>;
+ };
+ };
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH RFC 04/15] dt-bindings: media: Add CAMSS device for Maili
2026-09-23 11:02 [PATCH RFC 00/15] Add CAMSS and S5KJN5 sensor support for Qualcomm Hawi and Maili Nihal Kumar Gupta
` (2 preceding siblings ...)
2026-09-23 11:02 ` [PATCH RFC 03/15] dt-bindings: media: Add CAMSS device for Hawi Nihal Kumar Gupta
@ 2026-09-23 11:02 ` Nihal Kumar Gupta
2026-09-23 11:02 ` [PATCH RFC 05/15] media: qcom: camss: Add Hawi compatible camss driver Nihal Kumar Gupta
` (10 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Nihal Kumar Gupta @ 2026-09-23 11:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma, Nihal Kumar Gupta
Maili shares the same IP as Hawi. The only difference is
Hawi has six CSIPHY while Maili has five.
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
Documentation/devicetree/bindings/media/qcom,hawi-camss.yaml | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/qcom,hawi-camss.yaml b/Documentation/devicetree/bindings/media/qcom,hawi-camss.yaml
index 5bf0dca3d24621bfc4a09feb8e5037a925869751..d1d53d6f024cbf7d2a0f2525aa4040260353b200 100644
--- a/Documentation/devicetree/bindings/media/qcom,hawi-camss.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,hawi-camss.yaml
@@ -4,17 +4,22 @@
$id: http://devicetree.org/schemas/media/qcom,hawi-camss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Hawi Camera Subsystem (CAMSS)
+title: Qualcomm Hawi and Maili Camera Subsystem (CAMSS)
maintainers:
- Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
+ - Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
description:
The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
properties:
compatible:
- const: qcom,hawi-camss
+ oneOf:
+ - const: qcom,hawi-camss
+ - items:
+ - const: qcom,maili-camss
+ - const: qcom,hawi-camss
reg:
maxItems: 13
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH RFC 05/15] media: qcom: camss: Add Hawi compatible camss driver
2026-09-23 11:02 [PATCH RFC 00/15] Add CAMSS and S5KJN5 sensor support for Qualcomm Hawi and Maili Nihal Kumar Gupta
` (3 preceding siblings ...)
2026-09-23 11:02 ` [PATCH RFC 04/15] dt-bindings: media: Add CAMSS device for Maili Nihal Kumar Gupta
@ 2026-09-23 11:02 ` Nihal Kumar Gupta
2026-09-23 12:30 ` Bryan O'Donoghue
2026-09-23 11:02 ` [PATCH RFC 06/15] media: qcom: camss: vfe: Add support for VFE 1190 Nihal Kumar Gupta
` (9 subsequent siblings)
14 siblings, 1 reply; 24+ messages in thread
From: Nihal Kumar Gupta @ 2026-09-23 11:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma, Nihal Kumar Gupta
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add support for Hawi in the camss driver. Hawi reuses the CSIPHY
resource table from Kaanapali and the TPG resource table from
X1E80100. The CSID and VFE resource tables are Hawi-specific.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss.c | 259 ++++++++++++++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
2 files changed, 260 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index b862f067936c481408e1e8e1660c8aaf71b065a4..d0cb66ea850e33783912722ef60c97c2148d0ad5 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -4476,6 +4476,249 @@ static const struct resources_icc icc_res_sa8775p[] = {
},
};
+static const struct camss_subdev_resources vfe_res_hawi[] = {
+ /* VFE0 - TFE Full */
+ {
+ .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
+ "vfe0_fast_ahb", "vfe0", "cpas_vfe0",
+ "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo",
+ "cpas_mnoc_hf", "cpas_mnoc_sf" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 238200000, 397000000, 440000000, 480000000,
+ 630000000, 750000000, 833000000 },
+ { 0 },
+ { 171428571, 240000000, 300000000, 400000000,
+ 480000000, 600000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .reg_update_after_csid_config = true,
+ .has_pd = true,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE1 - TFE Full */
+ {
+ .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
+ "vfe1_fast_ahb", "vfe1", "cpas_vfe1",
+ "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo",
+ "cpas_mnoc_hf", "cpas_mnoc_sf" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 238200000, 397000000, 440000000, 480000000,
+ 630000000, 750000000, 833000000 },
+ { 0 },
+ { 171428571, 240000000, 300000000, 400000000,
+ 480000000, 600000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .reg_update_after_csid_config = true,
+ .has_pd = true,
+ .pd_name = "ife1",
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE2 - TFE Full */
+ {
+ .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
+ "vfe2_fast_ahb", "vfe2", "cpas_vfe2",
+ "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo",
+ "cpas_mnoc_hf", "cpas_mnoc_sf" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 238200000, 397000000, 440000000, 480000000,
+ 630000000, 750000000, 833000000 },
+ { 0 },
+ { 171428571, 240000000, 300000000, 400000000,
+ 480000000, 600000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe2" },
+ .interrupt = { "vfe2" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .reg_update_after_csid_config = true,
+ .has_pd = true,
+ .pd_name = "ife2",
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE3 - IFE Lite */
+ {
+ .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
+ "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
+ "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo",
+ "cpas_mnoc_hf", "cpas_mnoc_sf" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 400000000, 480000000 },
+ { 0 },
+ { 171428571, 240000000, 300000000, 400000000,
+ 480000000, 600000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .reg_update_after_csid_config = true,
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE4 - IFE Lite */
+ {
+ .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
+ "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
+ "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo",
+ "cpas_mnoc_hf", "cpas_mnoc_sf" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 400000000, 480000000 },
+ { 0 },
+ { 171428571, 240000000, 300000000, 400000000,
+ 480000000, 600000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .reg_update_after_csid_config = true,
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+};
+
+static const struct camss_subdev_resources csid_res_hawi[] = {
+ /* CSID0 */
+ {
+ .clock = { "csid", "csid_csiphy_rx" },
+ .clock_rate = { { 480000000 },
+ { 480000000 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_gen4,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .clock = { "csid", "csid_csiphy_rx" },
+ .clock_rate = { { 480000000 },
+ { 480000000 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_gen4,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID2 */
+ {
+ .clock = { "csid", "csid_csiphy_rx" },
+ .clock_rate = { { 480000000 },
+ { 480000000 } },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_gen4,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE0 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 480000000 },
+ { 480000000 } },
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_gen4,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE1 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 480000000 },
+ { 480000000 } },
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_gen4,
+ .formats = &csid_formats_gen2
+ }
+ }
+};
+
+static const struct resources_icc icc_res_hawi[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 38400,
+ .icc_bw_tbl.peak = 76800,
+ },
+ {
+ .name = "hf_mnoc",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_x1e80100[] = {
/* CSIPHY0 */
{
@@ -6116,6 +6359,21 @@ static const struct camss_resources sm8650_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_sm8650),
};
+static const struct camss_resources hawi_resources = {
+ .version = CAMSS_HAWI,
+ .pd_name = "top",
+ .csiphy_res = csiphy_res_kaanapali,
+ .tpg_res = tpg_res_x1e80100,
+ .csid_res = csid_res_hawi,
+ .vfe_res = vfe_res_hawi,
+ .icc_res = icc_res_hawi,
+ .icc_path_num = ARRAY_SIZE(icc_res_hawi),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali),
+ .tpg_num = ARRAY_SIZE(tpg_res_x1e80100),
+ .csid_num = ARRAY_SIZE(csid_res_hawi),
+ .vfe_num = ARRAY_SIZE(vfe_res_hawi),
+};
+
static const struct camss_resources x1e80100_resources = {
.version = CAMSS_X1E80100,
.pd_name = "top",
@@ -6151,6 +6409,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
+ { .compatible = "qcom,hawi-camss", .data = &hawi_resources },
{ .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
{ }
};
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index fadba57c5efaacb39ed3a55b107111528fd3182b..a92aea37c016db8066de392c40405303b74575fc 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -96,6 +96,7 @@ enum camss_version {
CAMSS_8550,
CAMSS_8650,
CAMSS_8775P,
+ CAMSS_HAWI,
CAMSS_KAANAPALI,
CAMSS_X1E80100,
};
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH RFC 05/15] media: qcom: camss: Add Hawi compatible camss driver
2026-09-23 11:02 ` [PATCH RFC 05/15] media: qcom: camss: Add Hawi compatible camss driver Nihal Kumar Gupta
@ 2026-09-23 12:30 ` Bryan O'Donoghue
2026-09-24 6:01 ` Nihal Kumar Gupta
0 siblings, 1 reply; 24+ messages in thread
From: Bryan O'Donoghue @ 2026-09-23 12:30 UTC (permalink / raw)
To: Nihal Kumar Gupta, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma
On 23/09/2026 12:02, Nihal Kumar Gupta wrote:
> From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>
> Add support for Hawi in the camss driver. Hawi reuses the CSIPHY
> resource table from Kaanapali and the TPG resource table from
> X1E80100. The CSID and VFE resource tables are Hawi-specific.
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
Missing Co-Developed-by:
> ---
> drivers/media/platform/qcom/camss/camss.c | 259 ++++++++++++++++++++++++++++++
> drivers/media/platform/qcom/camss/camss.h | 1 +
> 2 files changed, 260 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index b862f067936c481408e1e8e1660c8aaf71b065a4..d0cb66ea850e33783912722ef60c97c2148d0ad5 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -4476,6 +4476,249 @@ static const struct resources_icc icc_res_sa8775p[] = {
> },
> };
>
> +static const struct camss_subdev_resources vfe_res_hawi[] = {
> + /* VFE0 - TFE Full */
> + {
> + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
> + "vfe0_fast_ahb", "vfe0", "cpas_vfe0",
> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo",
> + "cpas_mnoc_hf", "cpas_mnoc_sf" },
> + .clock_rate = { { 0 },
> + { 0 },
> + { 0 },
> + { 0 },
> + { 238200000, 397000000, 440000000, 480000000,
> + 630000000, 750000000, 833000000 },
> + { 0 },
> + { 171428571, 240000000, 300000000, 400000000,
> + 480000000, 600000000 },
> + { 0 },
> + { 0 },
> + { 0 },
> + { 0 } },
> + .reg = { "vfe0" },
> + .interrupt = { "vfe0" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
You should only have to set is_lite = true when it is true.
> + .reg_update_after_csid_config = true,
> + .has_pd = true,
> + .pd_name = "ife0",
> + .hw_ops = &vfe_ops_gen4,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE1 - TFE Full */
> + {
> + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
> + "vfe1_fast_ahb", "vfe1", "cpas_vfe1",
> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo",
> + "cpas_mnoc_hf", "cpas_mnoc_sf" },
> + .clock_rate = { { 0 },
> + { 0 },
> + { 0 },
> + { 0 },
> + { 238200000, 397000000, 440000000, 480000000,
> + 630000000, 750000000, 833000000 },
> + { 0 },
> + { 171428571, 240000000, 300000000, 400000000,
> + 480000000, 600000000 },
> + { 0 },
> + { 0 },
> + { 0 },
> + { 0 } },
> + .reg = { "vfe1" },
> + .interrupt = { "vfe1" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
> + .reg_update_after_csid_config = true,
> + .has_pd = true,
> + .pd_name = "ife1",
> + .hw_ops = &vfe_ops_gen4,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE2 - TFE Full */
> + {
> + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
> + "vfe2_fast_ahb", "vfe2", "cpas_vfe2",
> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo",
> + "cpas_mnoc_hf", "cpas_mnoc_sf" },
> + .clock_rate = { { 0 },
> + { 0 },
> + { 0 },
> + { 0 },
> + { 238200000, 397000000, 440000000, 480000000,
> + 630000000, 750000000, 833000000 },
> + { 0 },
> + { 171428571, 240000000, 300000000, 400000000,
> + 480000000, 600000000 },
> + { 0 },
> + { 0 },
> + { 0 },
> + { 0 } },
> + .reg = { "vfe2" },
> + .interrupt = { "vfe2" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
> + .reg_update_after_csid_config = true,
> + .has_pd = true,
> + .pd_name = "ife2",
> + .hw_ops = &vfe_ops_gen4,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE3 - IFE Lite */
> + {
> + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
> + "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo",
> + "cpas_mnoc_hf", "cpas_mnoc_sf" },
> + .clock_rate = { { 0 },
> + { 0 },
> + { 0 },
> + { 0 },
> + { 200000000, 400000000, 480000000 },
> + { 0 },
> + { 171428571, 240000000, 300000000, 400000000,
> + 480000000, 600000000 },
> + { 0 },
> + { 0 },
> + { 0 },
> + { 0 } },
> + .reg = { "vfe_lite0" },
> + .interrupt = { "vfe_lite0" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .reg_update_after_csid_config = true,
> + .hw_ops = &vfe_ops_gen4,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE4 - IFE Lite */
> + {
> + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
> + "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo",
> + "cpas_mnoc_hf", "cpas_mnoc_sf" },
> + .clock_rate = { { 0 },
> + { 0 },
> + { 0 },
> + { 0 },
> + { 200000000, 400000000, 480000000 },
> + { 0 },
> + { 171428571, 240000000, 300000000, 400000000,
> + 480000000, 600000000 },
> + { 0 },
> + { 0 },
> + { 0 },
> + { 0 } },
> + .reg = { "vfe_lite1" },
> + .interrupt = { "vfe_lite1" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .reg_update_after_csid_config = true,
> + .hw_ops = &vfe_ops_gen4,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> +};
> +
> +static const struct camss_subdev_resources csid_res_hawi[] = {
> + /* CSID0 */
> + {
> + .clock = { "csid", "csid_csiphy_rx" },
> + .clock_rate = { { 480000000 },
> + { 480000000 } },
> + .reg = { "csid0" },
> + .interrupt = { "csid0" },
> + .csid = {
> + .is_lite = false,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .hw_ops = &csid_ops_gen4,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID1 */
> + {
> + .clock = { "csid", "csid_csiphy_rx" },
> + .clock_rate = { { 480000000 },
> + { 480000000 } },
> + .reg = { "csid1" },
> + .interrupt = { "csid1" },
> + .csid = {
> + .is_lite = false,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .hw_ops = &csid_ops_gen4,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID2 */
> + {
> + .clock = { "csid", "csid_csiphy_rx" },
> + .clock_rate = { { 480000000 },
> + { 480000000 } },
> + .reg = { "csid2" },
> + .interrupt = { "csid2" },
> + .csid = {
> + .is_lite = false,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .hw_ops = &csid_ops_gen4,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID_LITE0 */
> + {
> + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
> + .clock_rate = { { 480000000 },
> + { 480000000 } },
> + .reg = { "csid_lite0" },
> + .interrupt = { "csid_lite0" },
> + .csid = {
> + .is_lite = true,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .hw_ops = &csid_ops_gen4,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID_LITE1 */
> + {
> + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
> + .clock_rate = { { 480000000 },
> + { 480000000 } },
> + .reg = { "csid_lite1" },
> + .interrupt = { "csid_lite1" },
> + .csid = {
> + .is_lite = true,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .hw_ops = &csid_ops_gen4,
> + .formats = &csid_formats_gen2
> + }
> + }
> +};
> +
> +static const struct resources_icc icc_res_hawi[] = {
> + {
> + .name = "ahb",
> + .icc_bw_tbl.avg = 38400,
> + .icc_bw_tbl.peak = 76800,
> + },
> + {
> + .name = "hf_mnoc",
> + .icc_bw_tbl.avg = 2097152,
> + .icc_bw_tbl.peak = 2097152,
> + },
> +};
> +
> static const struct camss_subdev_resources csiphy_res_x1e80100[] = {
> /* CSIPHY0 */
> {
> @@ -6116,6 +6359,21 @@ static const struct camss_resources sm8650_resources = {
> .vfe_num = ARRAY_SIZE(vfe_res_sm8650),
> };
>
> +static const struct camss_resources hawi_resources = {
> + .version = CAMSS_HAWI,
> + .pd_name = "top",
> + .csiphy_res = csiphy_res_kaanapali,
> + .tpg_res = tpg_res_x1e80100,
> + .csid_res = csid_res_hawi,
> + .vfe_res = vfe_res_hawi,
> + .icc_res = icc_res_hawi,
> + .icc_path_num = ARRAY_SIZE(icc_res_hawi),
> + .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali),
> + .tpg_num = ARRAY_SIZE(tpg_res_x1e80100),
> + .csid_num = ARRAY_SIZE(csid_res_hawi),
> + .vfe_num = ARRAY_SIZE(vfe_res_hawi),
> +};
> +
> static const struct camss_resources x1e80100_resources = {
> .version = CAMSS_X1E80100,
> .pd_name = "top",
> @@ -6151,6 +6409,7 @@ static const struct of_device_id camss_dt_match[] = {
> { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
> { .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
> { .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
> + { .compatible = "qcom,hawi-camss", .data = &hawi_resources },
> { .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
> { }
> };
> diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
> index fadba57c5efaacb39ed3a55b107111528fd3182b..a92aea37c016db8066de392c40405303b74575fc 100644
> --- a/drivers/media/platform/qcom/camss/camss.h
> +++ b/drivers/media/platform/qcom/camss/camss.h
> @@ -96,6 +96,7 @@ enum camss_version {
> CAMSS_8550,
> CAMSS_8650,
> CAMSS_8775P,
> + CAMSS_HAWI,
> CAMSS_KAANAPALI,
> CAMSS_X1E80100,
> };
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH RFC 05/15] media: qcom: camss: Add Hawi compatible camss driver
2026-09-23 12:30 ` Bryan O'Donoghue
@ 2026-09-24 6:01 ` Nihal Kumar Gupta
2026-09-24 9:34 ` Bryan O'Donoghue
0 siblings, 1 reply; 24+ messages in thread
From: Nihal Kumar Gupta @ 2026-09-24 6:01 UTC (permalink / raw)
To: Bryan O'Donoghue, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma
On 23-09-2026 18:00, Bryan O'Donoghue wrote:
>> Add support for Hawi in the camss driver. Hawi reuses the CSIPHY
>> resource table from Kaanapali and the TPG resource table from
>> X1E80100. The CSID and VFE resource tables are Hawi-specific.
>>
>> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>> Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
>
> Missing Co-Developed-by:
>
Co-developed-by: is for authorship only (submitting-patches.rst). I didn't co-write this patch —
Signed-off-by: alone is correct here.
For patches where I actually co-authored the code, I've already added the Co-developed-by: tag.
>> ---
...
>> + { 0 } },
>> + .reg = { "vfe0" },
>> + .interrupt = { "vfe0" },
>> + .vfe = {
>> + .line_num = 3,
>> + .is_lite = false,
>
> You should only have to set is_lite = true when it is true.
>
ACK
>> + .reg_update_after_csid_config = true,
>> + .has_pd = true,
>> + .pd_name = "ife0",
>> + .hw_ops = &vfe_ops_gen4,
>> + .formats_rdi = &vfe_formats_rdi_845,
>> + .formats_pix = &vfe_formats_pix_845
>> + }
>> + },
>> + /* VFE1 - TFE Full */
---
Regards,
Nihal Kumar Gupta
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH RFC 05/15] media: qcom: camss: Add Hawi compatible camss driver
2026-09-24 6:01 ` Nihal Kumar Gupta
@ 2026-09-24 9:34 ` Bryan O'Donoghue
0 siblings, 0 replies; 24+ messages in thread
From: Bryan O'Donoghue @ 2026-09-24 9:34 UTC (permalink / raw)
To: Nihal Kumar Gupta, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma
On 24/09/2026 07:01, Nihal Kumar Gupta wrote:
>>> Signed-off-by: Hangxiang Ma<hangxiang.ma@oss.qualcomm.com>
>>> Signed-off-by: Nihal Kumar Gupta<nihal.gupta@oss.qualcomm.com>
>> Missing Co-Developed-by:
>>
> Co-developed-by: is for authorship only (submitting-patches.rst). I didn't co-write this patch —
> Signed-off-by: alone is correct here.
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
Fine. I missed the From:
---
bod
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH RFC 06/15] media: qcom: camss: vfe: Add support for VFE 1190
2026-09-23 11:02 [PATCH RFC 00/15] Add CAMSS and S5KJN5 sensor support for Qualcomm Hawi and Maili Nihal Kumar Gupta
` (4 preceding siblings ...)
2026-09-23 11:02 ` [PATCH RFC 05/15] media: qcom: camss: Add Hawi compatible camss driver Nihal Kumar Gupta
@ 2026-09-23 11:02 ` Nihal Kumar Gupta
2026-09-23 11:02 ` [PATCH RFC 07/15] arm64: dts: qcom: hawi: Add CAMSS and CSIPHY nodes for Hawi Nihal Kumar Gupta
` (8 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Nihal Kumar Gupta @ 2026-09-23 11:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma, Nihal Kumar Gupta
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add support for the Video Front End (VFE) on Hawi SoC. VFE gen4
has support for VFE 1190.
VFE 1190 uses a different bus write master register layout from the
VFE 1080/980 variants: the per-write-master register block has a
0x200 stride based at 0x1000, and several individual registers sit at
different offsets. Parameterize the bus register macros on the VFE
version so the gen4 driver can serve VFE 1080, 980 and 1190.
This change limits Hawi VFE output lines to 3 for now as constrained by
the CAMSS driver framework.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss-vfe-gen4.c | 49 ++++++++++++++--------
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
2 files changed, 34 insertions(+), 17 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-vfe-gen4.c b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c
index d73d70898710a2127c606ac8459a1d8c747a2f7c..eece3c8698e66d739dd870d79b549dbba8e52ad1 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe-gen4.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c
@@ -13,36 +13,51 @@
#include "camss.h"
#include "camss-vfe.h"
-/* VFE-gen4 Bus Register Base Addresses */
-#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000)
+#define IS_VFE_1190(vfe) ((vfe)->camss->res->version == CAMSS_HAWI)
+
+#define BUS_REG_BASE_1080 (vfe_is_lite(vfe) ? 0x800 : 0x1000)
-#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
+/* VFE-gen4 Bus Register Base Addresses */
+#define BUS_REG_BASE_1190 (0x800)
+#define BUS_REG_BASE (IS_VFE_1190(vfe) ? BUS_REG_BASE_1190 : \
+ BUS_REG_BASE_1080)
+
+#define BUS_REG_OFFSET_1080(n) (0x500 + (n) * 0x100)
+#define BUS_REG_OFFSET_1190(n) (0x1000 + (n) * 0x200)
+#define BUS_REG_OFFSET(n) (IS_VFE_1190(vfe) ? \
+ BUS_REG_OFFSET_1190(n) : \
+ BUS_REG_OFFSET_1080(n))
+
+#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + \
+ (IS_VFE_1190(vfe) ? 0x4 : 0x8))
#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
-#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0x128)
+#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + \
+ (IS_VFE_1190(vfe) ? 0x144 : 0x128))
-#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x500 + (n) * 0x100)
+#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + BUS_REG_OFFSET(n))
#define WM_CFG_EN BIT(0)
#define WM_VIR_FRM_EN BIT(1)
#define WM_CFG_MODE BIT(16)
-#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x504 + (n) * 0x100)
-#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x508 + (n) * 0x100)
-#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x50C + (n) * 0x100)
+#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0x4)
+#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0x8)
+#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0xC)
#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF)
-#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x514 + (n) * 0x100)
+#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0x14)
#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF)
-#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x518 + (n) * 0x100)
+#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0x18)
-#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x530 + (n) * 0x100)
-#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x534 + (n) * 0x100)
+#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0x30)
+#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0x34)
/* VFE lite has no such registers */
-#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x538 + (n) * 0x100)
-#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x53C + (n) * 0x100)
-
-#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x560 + (n) * 0x100)
-#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x564 + (n) * 0x100)
+#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0x38)
+#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0x3C)
+#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + \
+ (IS_VFE_1190(vfe) ? 0x64 : 0x60))
+#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + \
+ (IS_VFE_1190(vfe) ? 0x68 : 0x64))
/*
* IFE write master client IDs
*
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 826ab85a44a14e611ff9918f6c8de40edf483fb8..92dbd59477ad6cfe2d2e7e663397dde0271a5c16 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -353,6 +353,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_8550:
case CAMSS_8650:
case CAMSS_8775P:
+ case CAMSS_HAWI:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
switch (sink_code) {
@@ -2017,6 +2018,7 @@ static int vfe_bpl_align_rdi(struct vfe_device *vfe)
case CAMSS_8550:
case CAMSS_8650:
case CAMSS_8775P:
+ case CAMSS_HAWI:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
ret = 16;
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH RFC 07/15] arm64: dts: qcom: hawi: Add CAMSS and CSIPHY nodes for Hawi
2026-09-23 11:02 [PATCH RFC 00/15] Add CAMSS and S5KJN5 sensor support for Qualcomm Hawi and Maili Nihal Kumar Gupta
` (5 preceding siblings ...)
2026-09-23 11:02 ` [PATCH RFC 06/15] media: qcom: camss: vfe: Add support for VFE 1190 Nihal Kumar Gupta
@ 2026-09-23 11:02 ` Nihal Kumar Gupta
2026-09-23 12:40 ` Bryan O'Donoghue
2026-09-23 11:02 ` [PATCH RFC 08/15] arm64: dts: qcom: hawi: Add CCI definitions " Nihal Kumar Gupta
` (7 subsequent siblings)
14 siblings, 1 reply; 24+ messages in thread
From: Nihal Kumar Gupta @ 2026-09-23 11:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma, Nihal Kumar Gupta
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add dtsi to describe the Hawi CAMSS and CSIPHY block
3 x TPG
3 x CSID
2 x CSID Lite
3 x IFE
2 x IFE Lite
6 x CSIPHY
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Co-developed-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hawi.dtsi | 463 +++++++++++++++++++++++++++++++++++++
1 file changed, 463 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hawi.dtsi b/arch/arm64/boot/dts/qcom/hawi.dtsi
index c7ae8133b9cdc88133f6dccdf87bfa8bc88677e1..2e3286f29d7d6ed007289b5e04fcda34dec93039 100644
--- a/arch/arm64/boot/dts/qcom/hawi.dtsi
+++ b/arch/arm64/boot/dts/qcom/hawi.dtsi
@@ -548,6 +548,28 @@ soccp_smp2p_in: slave-kernel {
};
};
+ csiphy_mxc_opp_table: opp-table-mxc {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1_1>,
+ <&rpmhpd_opp_low_svs_d1_1>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_low_svs_d0>;
+ };
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_nom>;
+ };
+ };
+
soc@0 {
compatible = "simple-bus";
@@ -3865,6 +3887,447 @@ lpass_ag_noc: interconnect@8f40000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ camss: isp@9253000 {
+ compatible = "qcom,hawi-camss";
+
+ reg = <0x0 0x09253000 0x0 0x5e80>,
+ <0x0 0x09263000 0x0 0x5e80>,
+ <0x0 0x09273000 0x0 0x5e80>,
+ <0x0 0x092d3000 0x0 0x3880>,
+ <0x0 0x092e7000 0x0 0x3880>,
+ <0x0 0x093fd000 0x0 0x400>,
+ <0x0 0x093fe000 0x0 0x400>,
+ <0x0 0x093ff000 0x0 0x400>,
+ <0x0 0x09151000 0x0 0x20000>,
+ <0x0 0x09171000 0x0 0x20000>,
+ <0x0 0x09191000 0x0 0x20000>,
+ <0x0 0x092dc000 0x0 0x6800>,
+ <0x0 0x092f0000 0x0 0x6800>;
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csitpg0",
+ "csitpg1",
+ "csitpg2",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_DCD_XO_CLK>,
+ <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TITAN_MNOC_HF_CLK>,
+ <&camcc CAM_CC_TITAN_MNOC_SF_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
+ clock-names = "camnoc_nrt_axi",
+ "camnoc_rt_axi",
+ "camnoc_dcd_xo",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_mnoc_hf",
+ "cpas_mnoc_sf",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe2",
+ "cpas_vfe_lite",
+ "csid",
+ "csid_csiphy_rx",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "qdss_debug_xo";
+
+ interrupts = <GIC_ESPI 665 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 667 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 495 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 669 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 440 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 497 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 500 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 521 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 670 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 441 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc";
+
+ iommus = <&apps_smmu 0x1800 0x00>;
+
+ power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
+ <&camcc CAM_CC_TFE_1_GDSC>,
+ <&camcc CAM_CC_TFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ camss_csiphy0_inep: endpoint {
+ remote-endpoint = <&csiphy0_out_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ camss_csiphy1_inep: endpoint {
+ remote-endpoint = <&csiphy1_out_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ camss_csiphy2_inep: endpoint {
+ remote-endpoint = <&csiphy2_out_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ camss_csiphy3_inep: endpoint {
+ remote-endpoint = <&csiphy3_out_ep>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ camss_csiphy4_inep: endpoint {
+ remote-endpoint = <&csiphy4_out_ep>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ camss_csiphy5_inep: endpoint {
+ remote-endpoint = <&csiphy5_out_ep>;
+ };
+ };
+ };
+ };
+
+ csiphy0: phy@9523000 {
+ compatible = "qcom,hawi-csi2-phy", "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x09523000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_ESPI 541 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy0_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy0_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy0_inep>;
+ };
+ };
+ };
+ };
+
+ csiphy1: phy@9525000 {
+ compatible = "qcom,hawi-csi2-phy", "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x09525000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_ESPI 542 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy1_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy1_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy1_inep>;
+ };
+ };
+ };
+ };
+
+ csiphy2: phy@9527000 {
+ compatible = "qcom,hawi-csi2-phy", "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x09527000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_ESPI 543 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy2_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy2_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy2_inep>;
+ };
+ };
+ };
+ };
+
+ csiphy3: phy@9529000 {
+ compatible = "qcom,hawi-csi2-phy", "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x09529000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_ESPI 512 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy3_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy3_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy3_inep>;
+ };
+ };
+ };
+ };
+
+ csiphy4: phy@952b000 {
+ compatible = "qcom,hawi-csi2-phy", "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x0952b000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_ESPI 186 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy4_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy4_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy4_inep>;
+ };
+ };
+ };
+ };
+
+ csiphy5: phy@952d000 {
+ compatible = "qcom,hawi-csi2-phy", "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x0952d000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY5_CLK>,
+ <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_ESPI 153 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy5_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy5_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy5_inep>;
+ };
+ };
+ };
+ };
+
camcc: clock-controller@956d000 {
compatible = "qcom,hawi-camcc";
reg = <0x0 0x0956d000 0x0 0x80000>;
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH RFC 07/15] arm64: dts: qcom: hawi: Add CAMSS and CSIPHY nodes for Hawi
2026-09-23 11:02 ` [PATCH RFC 07/15] arm64: dts: qcom: hawi: Add CAMSS and CSIPHY nodes for Hawi Nihal Kumar Gupta
@ 2026-09-23 12:40 ` Bryan O'Donoghue
0 siblings, 0 replies; 24+ messages in thread
From: Bryan O'Donoghue @ 2026-09-23 12:40 UTC (permalink / raw)
To: Nihal Kumar Gupta, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma
On 23/09/2026 12:02, Nihal Kumar Gupta wrote:
> + compatible = "qcom,hawi-csi2-phy", "qcom,kaanapali-csi2-phy";
OK, this is why you depend on Kaanapali.
---
bod
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH RFC 08/15] arm64: dts: qcom: hawi: Add CCI definitions for Hawi
2026-09-23 11:02 [PATCH RFC 00/15] Add CAMSS and S5KJN5 sensor support for Qualcomm Hawi and Maili Nihal Kumar Gupta
` (6 preceding siblings ...)
2026-09-23 11:02 ` [PATCH RFC 07/15] arm64: dts: qcom: hawi: Add CAMSS and CSIPHY nodes for Hawi Nihal Kumar Gupta
@ 2026-09-23 11:02 ` Nihal Kumar Gupta
2026-09-23 12:42 ` Bryan O'Donoghue
2026-09-23 11:02 ` [PATCH RFC 09/15] arm64: dts: qcom: hawi: Add camera MCLK pinctrl " Nihal Kumar Gupta
` (6 subsequent siblings)
14 siblings, 1 reply; 24+ messages in thread
From: Nihal Kumar Gupta @ 2026-09-23 11:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma, Nihal Kumar Gupta
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Qualcomm Hawi SoC has three Camera Control Interface (CCI). Each
controller contains two I2C hosts.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hawi.dtsi | 194 +++++++++++++++++++++++++++++++++++++
1 file changed, 194 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hawi.dtsi b/arch/arm64/boot/dts/qcom/hawi.dtsi
index 2e3286f29d7d6ed007289b5e04fcda34dec93039..bc7adf10bd4653cf50527a1ebb38518c66dba900 100644
--- a/arch/arm64/boot/dts/qcom/hawi.dtsi
+++ b/arch/arm64/boot/dts/qcom/hawi.dtsi
@@ -4064,6 +4064,116 @@ camss_csiphy5_inep: endpoint {
};
};
+ cci0: cci@941b000 {
+ compatible = "qcom,hawi-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0941b000 0x0 0x1000>;
+
+ interrupts = <GIC_ESPI 490 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>;
+ clock-names = "ahb",
+ "cci";
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ pinctrl-0 = <&cci0_0_default>, <&cci0_1_default>;
+ pinctrl-1 = <&cci0_0_sleep>, <&cci0_1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@941c000 {
+ compatible = "qcom,hawi-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0941c000 0x0 0x1000>;
+
+ interrupts = <GIC_ESPI 491 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>;
+ clock-names = "ahb",
+ "cci";
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ pinctrl-0 = <&cci1_0_default>, <&cci1_1_default>;
+ pinctrl-1 = <&cci1_0_sleep>, <&cci1_1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci2: cci@941d000 {
+ compatible = "qcom,hawi-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0941d000 0x0 0x1000>;
+
+ interrupts = <GIC_ESPI 492 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_2_CLK>;
+ clock-names = "ahb",
+ "cci";
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ pinctrl-0 = <&cci2_0_default>, <&cci2_1_default>;
+ pinctrl-1 = <&cci2_0_sleep>, <&cci2_1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci2_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci2_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
csiphy0: phy@9523000 {
compatible = "qcom,hawi-csi2-phy", "qcom,kaanapali-csi2-phy";
reg = <0x0 0x09523000 0x0 0x2000>;
@@ -4602,6 +4712,90 @@ tlmm: pinctrl@f100000 {
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
+ cci0_0_default: cci0-0-default-state {
+ pins = "gpio109", "gpio110";
+ function = "cci_i2c0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci0_0_sleep: cci0-0-sleep-state {
+ pins = "gpio109", "gpio110";
+ function = "cci_i2c0";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci0_1_default: cci0-1-default-state {
+ pins = "gpio111", "gpio112";
+ function = "cci_i2c1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci0_1_sleep: cci0-1-sleep-state {
+ pins = "gpio111", "gpio112";
+ function = "cci_i2c1";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci1_0_default: cci1-0-default-state {
+ pins = "gpio113", "gpio114";
+ function = "cci_i2c2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci1_0_sleep: cci1-0-sleep-state {
+ pins = "gpio113", "gpio114";
+ function = "cci_i2c2";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci1_1_default: cci1-1-default-state {
+ pins = "gpio107", "gpio160";
+ function = "cci_i2c3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci1_1_sleep: cci1-1-sleep-state {
+ pins = "gpio107", "gpio160";
+ function = "cci_i2c3";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci2_0_default: cci2-0-default-state {
+ pins = "gpio108", "gpio149";
+ function = "cci_i2c4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci2_0_sleep: cci2-0-sleep-state {
+ pins = "gpio108", "gpio149";
+ function = "cci_i2c4";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci2_1_default: cci2-1-default-state {
+ pins = "gpio115", "gpio116";
+ function = "cci_i2c5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci2_1_sleep: cci2-1-sleep-state {
+ pins = "gpio115", "gpio116";
+ function = "cci_i2c5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
qup_i2c8_data_clk: qup-i2c8-data-clk-state {
/* SDA, SCL */
pins = "gpio0", "gpio1";
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH RFC 08/15] arm64: dts: qcom: hawi: Add CCI definitions for Hawi
2026-09-23 11:02 ` [PATCH RFC 08/15] arm64: dts: qcom: hawi: Add CCI definitions " Nihal Kumar Gupta
@ 2026-09-23 12:42 ` Bryan O'Donoghue
0 siblings, 0 replies; 24+ messages in thread
From: Bryan O'Donoghue @ 2026-09-23 12:42 UTC (permalink / raw)
To: Nihal Kumar Gupta, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma
On 23/09/2026 12:02, Nihal Kumar Gupta wrote:
> Signed-off-by: Hangxiang Ma<hangxiang.ma@oss.qualcomm.com>
> Signed-off-by: Nihal Kumar Gupta<nihal.gupta@oss.qualcomm.com>
Fix your Co-Developed-by and Signed-off-by chain
---
bod
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH RFC 09/15] arm64: dts: qcom: hawi: Add camera MCLK pinctrl for Hawi
2026-09-23 11:02 [PATCH RFC 00/15] Add CAMSS and S5KJN5 sensor support for Qualcomm Hawi and Maili Nihal Kumar Gupta
` (7 preceding siblings ...)
2026-09-23 11:02 ` [PATCH RFC 08/15] arm64: dts: qcom: hawi: Add CCI definitions " Nihal Kumar Gupta
@ 2026-09-23 11:02 ` Nihal Kumar Gupta
2026-09-23 11:02 ` [PATCH RFC 10/15] arm64: dts: qcom: hawi-mtp: Enable camera subsystem for Hawi MTP Nihal Kumar Gupta
` (5 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Nihal Kumar Gupta @ 2026-09-23 11:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma, Nihal Kumar Gupta
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Define pinctrl definitions to enable camera master clocks on Hawi.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hawi.dtsi | 56 ++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hawi.dtsi b/arch/arm64/boot/dts/qcom/hawi.dtsi
index bc7adf10bd4653cf50527a1ebb38518c66dba900..85a9faad59fc0387ebf4d7565fd08dd7acce1f26 100644
--- a/arch/arm64/boot/dts/qcom/hawi.dtsi
+++ b/arch/arm64/boot/dts/qcom/hawi.dtsi
@@ -4712,6 +4712,62 @@ tlmm: pinctrl@f100000 {
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
+ cam0_default: cam0-default-state {
+ pins = "gpio89";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam1_default: cam1-default-state {
+ pins = "gpio90";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam2_default: cam2-default-state {
+ pins = "gpio91";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam3_default: cam3-default-state {
+ pins = "gpio92";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam4_default: cam4-default-state {
+ pins = "gpio93";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam5_default: cam5-default-state {
+ pins = "gpio94";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam6_default: cam6-default-state {
+ pins = "gpio95";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam7_default: cam7-default-state {
+ pins = "gpio96";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
cci0_0_default: cci0-0-default-state {
pins = "gpio109", "gpio110";
function = "cci_i2c0";
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH RFC 10/15] arm64: dts: qcom: hawi-mtp: Enable camera subsystem for Hawi MTP
2026-09-23 11:02 [PATCH RFC 00/15] Add CAMSS and S5KJN5 sensor support for Qualcomm Hawi and Maili Nihal Kumar Gupta
` (8 preceding siblings ...)
2026-09-23 11:02 ` [PATCH RFC 09/15] arm64: dts: qcom: hawi: Add camera MCLK pinctrl " Nihal Kumar Gupta
@ 2026-09-23 11:02 ` Nihal Kumar Gupta
2026-09-23 12:44 ` Bryan O'Donoghue
2026-09-23 11:02 ` [PATCH RFC 11/15] arm64: dts: qcom: maili: Add support for cambistmclkcc and camcc Nihal Kumar Gupta
` (4 subsequent siblings)
14 siblings, 1 reply; 24+ messages in thread
From: Nihal Kumar Gupta @ 2026-09-23 11:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma, Nihal Kumar Gupta
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Enable the camera subsystem on the Hawi MTP along with the S5KJN5 sensor
connected to CSIPHY2 through I2C0 CCI1. Add the camera master clock and
sensor reset pin states on the TLMM GPIOs.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Co-developed-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hawi-mtp.dts | 62 +++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hawi-mtp.dts b/arch/arm64/boot/dts/qcom/hawi-mtp.dts
index 7709582491f9d426886a6afced6d3706b629e620..183c0c7a7595703113cb709b0e9f39ea5dc339b1 100644
--- a/arch/arm64/boot/dts/qcom/hawi-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/hawi-mtp.dts
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/media/video-interfaces.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
@@ -781,6 +782,60 @@ vreg_l7n_3p3: ldo7 {
};
};
+&camss {
+ status = "okay";
+};
+
+&camss_csiphy2_inep {
+ data-lanes = <1 2 3 4>;
+};
+
+&cci0 {
+ status = "okay";
+};
+
+&cci0_i2c1 {
+ camera@10 {
+ compatible = "samsung,s5kjn5";
+ reg = <0x10>;
+ reset-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&cam2_default &cam2_reset>;
+ pinctrl-names = "default";
+
+ clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
+ assigned-clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ afvdd-supply = <&vreg_l5m_2p8>;
+ vdda-supply = <&vreg_l7m_2p2>;
+ vddd-supply = <&vreg_l1m_1p0>;
+ vddio-supply = <&vreg_l4n_1p8>;
+ vddio1p2-supply = <&vreg_l2n_1p2>;
+
+ port {
+ s5kjn5_ep: endpoint {
+ link-frequencies = /bits/ 64 <1248000000>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csiphy2_in_ep>;
+ };
+ };
+ };
+};
+
+&csiphy2 {
+ vdda-0p9-supply = <&vreg_l1i_0p8>;
+ vdda-1p2-supply = <&vreg_l3d_1p2>;
+
+ status = "okay";
+};
+
+&csiphy2_in_ep {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&s5kjn5_ep>;
+};
+
&pcie0 {
status = "okay";
};
@@ -937,6 +992,13 @@ &tlmm {
<119 2>, /* SoCCP */
<144 2>; /* CXM UART */
+ cam2_reset: cam2-reset-state {
+ pins = "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
key_vol_up_default: key-vol-up-default-state {
pins = "gpio101";
function = "gpio";
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH RFC 10/15] arm64: dts: qcom: hawi-mtp: Enable camera subsystem for Hawi MTP
2026-09-23 11:02 ` [PATCH RFC 10/15] arm64: dts: qcom: hawi-mtp: Enable camera subsystem for Hawi MTP Nihal Kumar Gupta
@ 2026-09-23 12:44 ` Bryan O'Donoghue
0 siblings, 0 replies; 24+ messages in thread
From: Bryan O'Donoghue @ 2026-09-23 12:44 UTC (permalink / raw)
To: Nihal Kumar Gupta, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma
On 23/09/2026 12:02, Nihal Kumar Gupta wrote:
> +
> +&csiphy2_in_ep {
> + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
> + clock-lanes = <0>;
> + data-lanes = <1 2 3 4>;
> + remote-endpoint = <&s5kjn5_ep>;
> +};
> +
Drop the clock-lanes part its not current.
---
bod
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH RFC 11/15] arm64: dts: qcom: maili: Add support for cambistmclkcc and camcc
2026-09-23 11:02 [PATCH RFC 00/15] Add CAMSS and S5KJN5 sensor support for Qualcomm Hawi and Maili Nihal Kumar Gupta
` (9 preceding siblings ...)
2026-09-23 11:02 ` [PATCH RFC 10/15] arm64: dts: qcom: hawi-mtp: Enable camera subsystem for Hawi MTP Nihal Kumar Gupta
@ 2026-09-23 11:02 ` Nihal Kumar Gupta
2026-09-23 11:02 ` [PATCH RFC 12/15] arm64: dts: qcom: maili: Add CAMSS and CSIPHY nodes for Maili Nihal Kumar Gupta
` (3 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Nihal Kumar Gupta @ 2026-09-23 11:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma, Nihal Kumar Gupta, Taniya Das
From: Taniya Das <taniya.das@oss.qualcomm.com>
Add the device nodes for the cambistmclkcc and camcc on Qualcomm
Maili SoC.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/maili.dtsi | 43 +++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/maili.dtsi b/arch/arm64/boot/dts/qcom/maili.dtsi
index 886d307e536be6152906e344289d5b3fb290f0a4..fb404d6c3e92ed95ecd01782c389096fae402701 100644
--- a/arch/arm64/boot/dts/qcom/maili.dtsi
+++ b/arch/arm64/boot/dts/qcom/maili.dtsi
@@ -3,9 +3,11 @@
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
+#include <dt-bindings/clock/qcom,hawi-camcc.h>
#include <dt-bindings/clock/qcom,hawi-gcc.h>
#include <dt-bindings/clock/qcom,hawi-gpucc.h>
#include <dt-bindings/clock/qcom,hawi-tcsrcc.h>
+#include <dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h>
#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h>
#include <dt-bindings/clock/qcom,maili-videocc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
@@ -2038,6 +2040,25 @@ pcie_anoc: interconnect@16c0000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ cambistmclkcc: clock-controller@1760000 {
+ compatible = "qcom,maili-cambistmclkcc",
+ "qcom,kaanapali-cambistmclkcc";
+ reg = <0x0 0x01760000 0x0 0x6000>;
+
+ clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MX>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
mmss_noc: interconnect@1780000 {
compatible = "qcom,maili-mmss-noc";
reg = <0x0 0x01780000 0x0 0x5f800>;
@@ -4037,6 +4058,28 @@ lpass_ag_noc: interconnect@8f40000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ camcc: clock-controller@956d000 {
+ compatible = "qcom,maili-camcc";
+ reg = <0x0 0x0956d000 0x0 0x80000>;
+
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+
+ interconnects = <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ALWAYS>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
usb: usb@a600000 {
compatible = "qcom,maili-dwc3", "qcom,snps-dwc3";
reg = <0x0 0x0a600000 0x0 0xfc100>;
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH RFC 12/15] arm64: dts: qcom: maili: Add CAMSS and CSIPHY nodes for Maili
2026-09-23 11:02 [PATCH RFC 00/15] Add CAMSS and S5KJN5 sensor support for Qualcomm Hawi and Maili Nihal Kumar Gupta
` (10 preceding siblings ...)
2026-09-23 11:02 ` [PATCH RFC 11/15] arm64: dts: qcom: maili: Add support for cambistmclkcc and camcc Nihal Kumar Gupta
@ 2026-09-23 11:02 ` Nihal Kumar Gupta
2026-09-23 11:02 ` [PATCH RFC 13/15] arm64: dts: qcom: maili: Add camera MCLK pinctrl " Nihal Kumar Gupta
` (2 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Nihal Kumar Gupta @ 2026-09-23 11:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma, Nihal Kumar Gupta
Maili uses the same CAMSS IP as Hawi with five CSIPHY instances
instead of six. Add CAMSS and CSIPHY nodes reusing the Hawi-compatible
driver.
5 x CSIPHY
3 x TPG
3 x CSID
2 x CSID Lite
3 x IFE
2 x IFE Lite
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/maili.dtsi | 412 ++++++++++++++++++++++++++++++++++++
1 file changed, 412 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/maili.dtsi b/arch/arm64/boot/dts/qcom/maili.dtsi
index fb404d6c3e92ed95ecd01782c389096fae402701..8d5d64a23642cbde51ecb6c7377a5eed355f0d65 100644
--- a/arch/arm64/boot/dts/qcom/maili.dtsi
+++ b/arch/arm64/boot/dts/qcom/maili.dtsi
@@ -537,6 +537,28 @@ smp2p_soccp_in: slave-kernel {
};
};
+ csiphy_mxc_opp_table: opp-table-mxc {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1_1>,
+ <&rpmhpd_opp_low_svs_d1_1>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_low_svs_d0>;
+ };
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_nom>;
+ };
+ };
+
soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
@@ -4058,6 +4080,396 @@ lpass_ag_noc: interconnect@8f40000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ camss: isp@9253000 {
+ compatible = "qcom,maili-camss", "qcom,hawi-camss";
+
+ reg = <0x0 0x09253000 0x0 0x5e80>,
+ <0x0 0x09263000 0x0 0x5e80>,
+ <0x0 0x09273000 0x0 0x5e80>,
+ <0x0 0x092d3000 0x0 0x3880>,
+ <0x0 0x092e7000 0x0 0x3880>,
+ <0x0 0x093fd000 0x0 0x400>,
+ <0x0 0x093fe000 0x0 0x400>,
+ <0x0 0x093ff000 0x0 0x400>,
+ <0x0 0x09151000 0x0 0x20000>,
+ <0x0 0x09171000 0x0 0x20000>,
+ <0x0 0x09191000 0x0 0x20000>,
+ <0x0 0x092dc000 0x0 0x6800>,
+ <0x0 0x092f0000 0x0 0x6800>;
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csitpg0",
+ "csitpg1",
+ "csitpg2",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_DCD_XO_CLK>,
+ <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TITAN_MNOC_HF_CLK>,
+ <&camcc CAM_CC_TITAN_MNOC_SF_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
+ clock-names = "camnoc_nrt_axi",
+ "camnoc_rt_axi",
+ "camnoc_dcd_xo",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_mnoc_hf",
+ "cpas_mnoc_sf",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe2",
+ "cpas_vfe_lite",
+ "csid",
+ "csid_csiphy_rx",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "qdss_debug_xo";
+
+ interrupts = <GIC_ESPI 665 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 667 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 495 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 669 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 440 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 497 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 500 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 521 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 670 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 441 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc";
+
+ iommus = <&apps_smmu 0x1800 0x00>;
+
+ power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
+ <&camcc CAM_CC_TFE_1_GDSC>,
+ <&camcc CAM_CC_TFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ camss_csiphy0_inep: endpoint {
+ remote-endpoint = <&csiphy0_out_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ camss_csiphy1_inep: endpoint {
+ remote-endpoint = <&csiphy1_out_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ camss_csiphy2_inep: endpoint {
+ remote-endpoint = <&csiphy2_out_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ camss_csiphy3_inep: endpoint {
+ remote-endpoint = <&csiphy3_out_ep>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ camss_csiphy4_inep: endpoint {
+ remote-endpoint = <&csiphy4_out_ep>;
+ };
+ };
+ };
+ };
+
+ csiphy0: phy@9523000 {
+ compatible = "qcom,maili-csi2-phy", "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x09523000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_ESPI 541 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy0_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy0_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy0_inep>;
+ };
+ };
+ };
+ };
+
+ csiphy1: phy@9525000 {
+ compatible = "qcom,maili-csi2-phy", "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x09525000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_ESPI 542 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy1_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy1_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy1_inep>;
+ };
+ };
+ };
+ };
+
+ csiphy2: phy@9527000 {
+ compatible = "qcom,maili-csi2-phy", "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x09527000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_ESPI 543 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy2_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy2_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy2_inep>;
+ };
+ };
+ };
+ };
+
+ csiphy3: phy@9529000 {
+ compatible = "qcom,maili-csi2-phy", "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x09529000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_ESPI 512 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy3_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy3_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy3_inep>;
+ };
+ };
+ };
+ };
+
+ csiphy4: phy@952b000 {
+ compatible = "qcom,maili-csi2-phy", "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x0952b000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_ESPI 186 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy4_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy4_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy4_inep>;
+ };
+ };
+ };
+ };
+
camcc: clock-controller@956d000 {
compatible = "qcom,maili-camcc";
reg = <0x0 0x0956d000 0x0 0x80000>;
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH RFC 13/15] arm64: dts: qcom: maili: Add camera MCLK pinctrl for Maili
2026-09-23 11:02 [PATCH RFC 00/15] Add CAMSS and S5KJN5 sensor support for Qualcomm Hawi and Maili Nihal Kumar Gupta
` (11 preceding siblings ...)
2026-09-23 11:02 ` [PATCH RFC 12/15] arm64: dts: qcom: maili: Add CAMSS and CSIPHY nodes for Maili Nihal Kumar Gupta
@ 2026-09-23 11:02 ` Nihal Kumar Gupta
2026-09-23 11:02 ` [PATCH RFC 14/15] arm64: dts: qcom: maili-mtp: Enable S5KJN5 camera for Maili MTP Nihal Kumar Gupta
2026-09-23 11:02 ` [PATCH RFC 15/15] arm64: defconfig: Enable S5KJN5 camera sensor for Qualcomm boards Nihal Kumar Gupta
14 siblings, 0 replies; 24+ messages in thread
From: Nihal Kumar Gupta @ 2026-09-23 11:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma, Nihal Kumar Gupta
Define pinctrl definitions to enable camera master clocks on Maili.
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/maili.dtsi | 42 +++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/maili.dtsi b/arch/arm64/boot/dts/qcom/maili.dtsi
index 8d5d64a23642cbde51ecb6c7377a5eed355f0d65..a73e0548f9ae32f64b3429c05187f9529bead616 100644
--- a/arch/arm64/boot/dts/qcom/maili.dtsi
+++ b/arch/arm64/boot/dts/qcom/maili.dtsi
@@ -5748,6 +5748,48 @@ qup_spi0_cs: qup-spi0-cs-state {
bias-disable;
};
+ mclk0_default: mclk0-default-state {
+ pins = "gpio95";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ mclk1_default: mclk1-default-state {
+ pins = "gpio90";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ mclk2_default: mclk2-default-state {
+ pins = "gpio91";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ mclk3_default: mclk3-default-state {
+ pins = "gpio92";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ mclk4_default: mclk4-default-state {
+ pins = "gpio93";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ mclk5_default: mclk5-default-state {
+ pins = "gpio94";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
};
sram@14680000 {
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH RFC 14/15] arm64: dts: qcom: maili-mtp: Enable S5KJN5 camera for Maili MTP
2026-09-23 11:02 [PATCH RFC 00/15] Add CAMSS and S5KJN5 sensor support for Qualcomm Hawi and Maili Nihal Kumar Gupta
` (12 preceding siblings ...)
2026-09-23 11:02 ` [PATCH RFC 13/15] arm64: dts: qcom: maili: Add camera MCLK pinctrl " Nihal Kumar Gupta
@ 2026-09-23 11:02 ` Nihal Kumar Gupta
2026-09-23 11:02 ` [PATCH RFC 15/15] arm64: defconfig: Enable S5KJN5 camera sensor for Qualcomm boards Nihal Kumar Gupta
14 siblings, 0 replies; 24+ messages in thread
From: Nihal Kumar Gupta @ 2026-09-23 11:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma, Nihal Kumar Gupta
Qualcomm Maili MTP carries a Samsung S5KJN5 rear camera sensor on
QUP I2C9, connected to CSIPHY2 via 4-lane CSI-2 D-PHY.
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/maili-mtp.dts | 64 ++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/maili-mtp.dts b/arch/arm64/boot/dts/qcom/maili-mtp.dts
index 1fdc91e03271c40640910b57f3187311b6077ea9..f8582a21d1b4f58113c6f2d1a26e4d673016894a 100644
--- a/arch/arm64/boot/dts/qcom/maili-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/maili-mtp.dts
@@ -8,6 +8,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/media/video-interfaces.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "maili.dtsi"
@@ -743,6 +744,62 @@ vreg_l7n_3p3: ldo7 {
};
};
+&camss {
+ status = "okay";
+};
+
+&camss_csiphy2_inep {
+ data-lanes = <1 2 3 4>;
+};
+
+&csiphy2 {
+ vdda-0p9-supply = <&vreg_l1d_0p9>;
+ vdda-1p2-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&csiphy2_in_ep {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&s5kjn5_ep>;
+};
+
+&i2c9 {
+ clock-frequency = <400000>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ status = "okay";
+
+ camera@10 {
+ compatible = "samsung,s5kjn5";
+ reg = <0x10>;
+
+ reset-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&mclk2_default &cam2_reset_default>;
+ pinctrl-names = "default";
+
+ clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
+ assigned-clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ afvdd-supply = <&vreg_l5m_2p8>;
+ vdda-supply = <&vreg_l7m_2p2>;
+ vddd-supply = <&vreg_l1m_1p0>;
+ vddio-supply = <&vreg_l4n_1p8>;
+ vddio1p2-supply = <&vreg_l2n_1p2>;
+
+ port {
+ s5kjn5_ep: endpoint {
+ link-frequencies = /bits/ 64 <1248000000>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csiphy2_in_ep>;
+ };
+ };
+ };
+};
+
&pcie0 {
status = "okay";
};
@@ -906,6 +963,13 @@ &tlmm {
<119 2>, /* SoCCP */
<144 2>, /* CXM UART */
<211 1>; /* NFC Secure IO */
+
+ cam2_reset_default: cam2-reset-default-state {
+ pins = "gpio3";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
};
&uart7 {
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH RFC 15/15] arm64: defconfig: Enable S5KJN5 camera sensor for Qualcomm boards
2026-09-23 11:02 [PATCH RFC 00/15] Add CAMSS and S5KJN5 sensor support for Qualcomm Hawi and Maili Nihal Kumar Gupta
` (13 preceding siblings ...)
2026-09-23 11:02 ` [PATCH RFC 14/15] arm64: dts: qcom: maili-mtp: Enable S5KJN5 camera for Maili MTP Nihal Kumar Gupta
@ 2026-09-23 11:02 ` Nihal Kumar Gupta
2026-09-23 12:48 ` Bryan O'Donoghue
14 siblings, 1 reply; 24+ messages in thread
From: Nihal Kumar Gupta @ 2026-09-23 11:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma, Nihal Kumar Gupta
Enable the S5KJN5 driver which is used for the camera sensor on the
Qualcomm Hawi and Maili MTP boards.
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5217de386edc5e32289e453288db0bd9449d4c6f..fa35db683bb253e83af6bb25f702e3127761c086 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -960,6 +960,7 @@ CONFIG_VIDEO_IMX412=m
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
CONFIG_VIDEO_S5KJN1=m
+CONFIG_VIDEO_S5KJN5=m
CONFIG_AUXDISPLAY=y
CONFIG_SEG_LED_GPIO=m
CONFIG_DRM=m
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH RFC 15/15] arm64: defconfig: Enable S5KJN5 camera sensor for Qualcomm boards
2026-09-23 11:02 ` [PATCH RFC 15/15] arm64: defconfig: Enable S5KJN5 camera sensor for Qualcomm boards Nihal Kumar Gupta
@ 2026-09-23 12:48 ` Bryan O'Donoghue
0 siblings, 0 replies; 24+ messages in thread
From: Bryan O'Donoghue @ 2026-09-23 12:48 UTC (permalink / raw)
To: Nihal Kumar Gupta, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam, Hangxiang Ma, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Suresh Vankadara, Vikram Sharma
On 23/09/2026 12:02, Nihal Kumar Gupta wrote:
> Enable the S5KJN5 driver which is used for the camera sensor on the
> Qualcomm Hawi and Maili MTP boards.
>
> Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
> ---
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 5217de386edc5e32289e453288db0bd9449d4c6f..fa35db683bb253e83af6bb25f702e3127761c086 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -960,6 +960,7 @@ CONFIG_VIDEO_IMX412=m
> CONFIG_VIDEO_OV5640=m
> CONFIG_VIDEO_OV5645=m
> CONFIG_VIDEO_S5KJN1=m
> +CONFIG_VIDEO_S5KJN5=m
> CONFIG_AUXDISPLAY=y
> CONFIG_SEG_LED_GPIO=m
> CONFIG_DRM=m
>
> --
> 2.34.1
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 24+ messages in thread