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From: "guanghuifeng@linux.alibaba.com" <guanghuifeng@linux.alibaba.com>
To: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
	linux-kernel@vger.kernel.org, iommu@lists.linux.dev,
	joro@8bytes.org, jgg@nvidia.com
Cc: yi.l.liu@intel.com, kevin.tian@intel.com, nicolinc@nvidia.com,
	vasant.hegde@amd.com, jon.grimm@amd.com, santosh.shukla@amd.com,
	Sairaj.K@amd.com, jay.chen@amd.com, wvw@google.com,
	wnliu@google.com, dantuluris@google.com, chriscli@google.com,
	kpsingh@google.com, alejandro.j.jimenez@oracle.com,
	joao.m.martins@oracle.com
Subject: Re: [PATCH 23/24] iommu/amd: Assign per-vIOMMU translate device ID
Date: Wed, 19 Aug 2026 18:18:36 +0800	[thread overview]
Message-ID: <23d80e6f-b4dc-45f9-856f-fb21b1905304@linux.alibaba.com> (raw)
In-Reply-To: <20260727132913.22475-24-suravee.suthikulpanit@amd.com>


在 2026/7/27 21:29, Suravee Suthikulpanit 写道:
> Allocate one translate-device-id per IOMMUFD vIOMMU instance from the
> per-segment pool on init.  Program translation DTE and VFctrl TransDevID
> after MMIO reset; clear both on init error and destroy.
>
> Add per-vIOMMU trans_devid_lock to serialize DTE and VFctrl updates
> during teardown.
>
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> ---
>   drivers/iommu/amd/amd_iommu_types.h |  7 ++++++
>   drivers/iommu/amd/iommufd.c         | 35 +++++++++++++++++++++++++++++
>   drivers/iommu/amd/viommu.c          |  2 ++
>   3 files changed, 44 insertions(+)
>
> diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
> index f288a7b384d0..39cf2c588106 100644
> --- a/drivers/iommu/amd/amd_iommu_types.h
> +++ b/drivers/iommu/amd/amd_iommu_types.h
> @@ -559,6 +559,13 @@ struct amd_iommu_viommu {
>   	u64 *domid_table;
>   	u16 trans_devid;
>   
> +	/*
> +	 * Serializes translate-device-id hardware changes (DTE, VFctrl) and
> +	 * coordinates with pool relocation during PCI attach.  Lock ordering:
> +	 * pci_seg->trans_devid_mutex, then trans_devid_lock.
> +	 */
> +	struct mutex trans_devid_lock;
> +
>   	/* Offset for mmap() of guest VF MMIO; set after iommufd_viommu_alloc_mmap(). */
>   	unsigned long vfmmio_mmap_offset;
>   };
> diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c
> index 7e070f72f02e..43575af59bba 100644
> --- a/drivers/iommu/amd/iommufd.c
> +++ b/drivers/iommu/amd/iommufd.c
> @@ -48,11 +48,15 @@ int amd_iommufd_viommu_init(struct iommufd_viommu *viommu, struct iommu_domain *
>   	int ret;
>   	phys_addr_t page_base;
>   	unsigned long flags;
> +	u16 trans_devid;
> +	bool trans_devid_allocated = false;
> +	bool trans_dte_set = false;
>   	struct iommu_viommu_amd data = {};
>   	struct protection_domain *pdom = to_pdomain(parent);
>   	struct amd_iommu *iommu = container_of(viommu->iommu_dev, struct amd_iommu, iommu);
>   	struct amd_iommu_viommu *aviommu = container_of(viommu, struct amd_iommu_viommu, core);
>   
> +	mutex_init(&aviommu->trans_devid_lock);
>   	xa_init_flags(&aviommu->gdomid_array, XA_FLAGS_ALLOC1);
>   	aviommu->parent = pdom;
>   
> @@ -81,9 +85,22 @@ int amd_iommufd_viommu_init(struct iommufd_viommu *viommu, struct iommu_domain *
>   
>   	data.out_vfmmio_mmap_offset = aviommu->vfmmio_mmap_offset;
>   
> +	ret = amd_iommu_trans_devid_alloc(iommu->pci_seg, aviommu);
> +	if (ret < 0)
> +		goto err_trans_devid;
> +	trans_devid = ret;
> +	trans_devid_allocated = true;
> +	aviommu->trans_devid = trans_devid;
> +
>   	/* Reset vIOMMU MMIOs to initialize the vIOMMU */
>   	iommu_reset_vmmio(iommu, aviommu->gid);
>   
> +	ret = amd_iommu_set_translate_dte(viommu);
> +	if (ret)
> +		goto err_init;
> +	trans_dte_set = true;
> +	amd_iommu_update_vfctrl_mmio_translate_devid(iommu, aviommu->gid, trans_devid);
> +
>   	ret = amd_viommu_init_one(iommu, aviommu);
>   	if (ret)
>   		goto err_init;
> @@ -102,6 +119,18 @@ int amd_iommufd_viommu_init(struct iommufd_viommu *viommu, struct iommu_domain *
>   
>   	return 0;
>   err_init:
> +	if (trans_dte_set) {
> +		mutex_lock(&aviommu->trans_devid_lock);
> +		amd_iommu_update_vfctrl_mmio_translate_devid(iommu, aviommu->gid, 0);
> +		amd_iommu_clear_translate_dte(iommu, trans_devid);
> +		mutex_unlock(&aviommu->trans_devid_lock);
> +	}
> +	if (trans_devid_allocated) {
> +		mutex_lock(&aviommu->trans_devid_lock);
> +		amd_iommu_trans_devid_free(iommu->pci_seg, trans_devid, aviommu);
> +		mutex_unlock(&aviommu->trans_devid_lock);
> +	}
> +err_trans_devid:
>   	iommufd_viommu_destroy_mmap(&aviommu->core, aviommu->vfmmio_mmap_offset);
>   err_mmap:
>   	amd_iommu_gid_free(iommu, aviommu->gid);
> @@ -124,6 +153,12 @@ static void amd_iommufd_viommu_destroy(struct iommufd_viommu *viommu)
>   	xa_destroy(&aviommu->gdomid_array);
>   	iommufd_viommu_destroy_mmap(&aviommu->core, aviommu->vfmmio_mmap_offset);
>   	amd_viommu_uninit_one(iommu, aviommu);
> +
> +	mutex_lock(&aviommu->trans_devid_lock);
> +	amd_iommu_update_vfctrl_mmio_translate_devid(iommu, aviommu->gid, 0);
> +	amd_iommu_clear_translate_dte(iommu, aviommu->trans_devid);
> +	amd_iommu_trans_devid_free(iommu->pci_seg, aviommu->trans_devid, aviommu);
> +	mutex_unlock(&aviommu->trans_devid_lock);
>   	amd_iommu_gid_free(iommu, aviommu->gid);
>   }

The comment states "pci_seg->trans_devid_mutex, then trans_devid_lock"
as the lock ordering. However, examining the actual code paths:

In amd_iommufd_viommu_destroy():
   mutex_lock(&aviommu->trans_devid_lock);          /* viommu lock first */
   ...
   amd_iommu_trans_devid_free(...);                  /* takes seg_mutex 
inside */
   mutex_unlock(&aviommu->trans_devid_lock);

In amd_iommu_trans_devid_free():
   mutex_lock(&pci_seg->trans_devid_mutex);          /* seg_mutex nested */

In trans_devid_relocate() (Patch 24):
   mutex_lock(&aviommu->trans_devid_lock);          /* viommu lock first */
   mutex_lock(&pci_seg->trans_devid_mutex);          /* seg_mutex second */

All paths consistently take trans_devid_lock first, then
trans_devid_mutex (nested). The actual ordering is the opposite of
what the comment describes:

   Actual:   trans_devid_lock -> trans_devid_mutex
   Comment:  trans_devid_mutex -> trans_devid_lock

The code is consistent and there is no deadlock risk, but the
comment should be corrected to avoid confusing future readers:

   * Lock ordering: trans_devid_lock, then pci_seg->trans_devid_mutex.



>   
> diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c
> index eb3f5217d856..ae4a6a2cae39 100644
> --- a/drivers/iommu/amd/viommu.c
> +++ b/drivers/iommu/amd/viommu.c
> @@ -501,6 +501,8 @@ void amd_viommu_uninit_one(struct amd_iommu *iommu, struct amd_iommu_viommu *avi
>   			       VIOMMU_DOMID_MAPPING_BASE,
>   			       VIOMMU_DOMID_MAPPING_ENTRY_SIZE,
>   			       aviommu->gid);
> +
> +	amd_iommu_update_vfctrl_mmio_translate_devid(iommu, aviommu->gid, 0);
>   	viommu_clear_mapping(iommu, aviommu);
>   }
>   

  reply	other threads:[~2026-08-19 10:18 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-27 13:28 [PATCH v4 00/24] iommu/amd: Introduce AMD Hardware-accelerated Virtualized IOMMU (vIOMMU) Support Suravee Suthikulpanit
2026-07-27 13:28 ` [PATCH 01/24] iommu/amd: Make amd_iommu_completion_wait() non-static Suravee Suthikulpanit
2026-08-05 17:01   ` Vasant Hegde
2026-07-27 13:28 ` [PATCH 02/24] iommu/amd: Introduce vIOMMU-specific events and event Suravee Suthikulpanit
2026-08-10  7:12   ` Vasant Hegde
2026-08-19  8:17   ` guanghuifeng
2026-07-27 13:28 ` [PATCH 03/24] iommu/amd: Detect and initialize AMD vIOMMU feature Suravee Suthikulpanit
2026-08-10  8:13   ` Vasant Hegde
2026-07-27 13:28 ` [PATCH 04/24] iommu/amd: Introduce IOMMUFD vIOMMU support for AMD Suravee Suthikulpanit
2026-07-27 13:28 ` [PATCH 05/24] iommu/amd: Allocate Guest IDs for IOMMUFD vIOMMU instances Suravee Suthikulpanit
2026-08-10  9:21   ` Vasant Hegde
2026-07-27 13:28 ` [PATCH 06/24] iommu/amd: Map vIOMMU VF and VF Control MMIO BARs Suravee Suthikulpanit
2026-08-10 10:00   ` Vasant Hegde
2026-08-19 13:18   ` guanghuifeng
2026-07-27 13:28 ` [PATCH 07/24] iommu/amd: Add support for AMD vIOMMU VF MMIO region Suravee Suthikulpanit
2026-08-10 10:49   ` Vasant Hegde
2026-07-27 13:28 ` [PATCH 08/24] iommu/amd: Introduce Reset vMMIO Command Suravee Suthikulpanit
2026-08-19  8:34   ` guanghuifeng
2026-07-27 13:28 ` [PATCH 09/24] iommu/amd: Introduce and map vIOMMU private IPA region Suravee Suthikulpanit
2026-07-27 13:28 ` [PATCH 10/24] iommu/amd: Pass iommu to device_flush_dte() Suravee Suthikulpanit
2026-08-10 11:07   ` Vasant Hegde
2026-07-27 13:29 ` [PATCH 11/24] iommu/amd: Export amd_iommu_alloc_dev_data() helper Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 12/24] iommu/amd: Pass iommu and devid to amd_iommu_make_clear_dte() Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 13/24] iommu/amd: Assign IOMMU Private Address domain to IOMMU Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 14/24] iommu/amd: Add per-VM private IPA alloc/map helpers Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 15/24] iommu/amd: Add helper functions to manage DevID / DomID mapping tables Suravee Suthikulpanit
2026-08-19 13:30   ` guanghuifeng
2026-07-27 13:29 ` [PATCH 16/24] iommu/amd: Introduce IOMMUFD vDevice support for AMD Suravee Suthikulpanit
2026-08-19 13:34   ` guanghuifeng
2026-07-27 13:29 ` [PATCH 17/24] iommu/amd: Introduce helper function for updating domain ID mapping table Suravee Suthikulpanit
2026-08-19 10:45   ` guanghuifeng
2026-07-27 13:29 ` [PATCH 18/24] iommu/amd: Introduce helper function for updating device " Suravee Suthikulpanit
2026-08-10 15:17   ` Vasant Hegde
2026-08-19 10:26   ` guanghuifeng
2026-07-27 13:29 ` [PATCH 19/24] iommu/amd: Add per-segment translate device ID pool Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 20/24] iommu/amd: Reserve translate-device-id for PCI requestor aliases Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 21/24] iommu/amd: Add translation DTE and VFctrl TransDevID helpers Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 22/24] iommu/amd: Add translate-device-id alloc/free with vIOMMU owner Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 23/24] iommu/amd: Assign per-vIOMMU translate device ID Suravee Suthikulpanit
2026-08-19 10:18   ` guanghuifeng [this message]
2026-07-27 13:29 ` [PATCH 24/24] iommu/amd: Relocate vIOMMU translate-device-id on PCI reserve Suravee Suthikulpanit
2026-08-19  9:42   ` guanghuifeng
2026-08-11  7:18 ` [PATCH v4 00/24] iommu/amd: Introduce AMD Hardware-accelerated Virtualized IOMMU (vIOMMU) Support Tian, Kevin

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