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From: David Woodhouse <dwmw2@infradead.org>
To: Linus Torvalds <torvalds@transmeta.com>
Cc: davidm@hpl.hp.com, Alan Cox <alan@lxorguk.ukuu.org.uk>,
	linux-kernel@vger.kernel.org, davidm@napali.hpl.hp.com
Subject: Re: adjust prefetch in free_one_pgd()
Date: Sat, 03 Aug 2002 23:03:49 +0100	[thread overview]
Message-ID: <24964.1028412229@redhat.com> (raw)
In-Reply-To: <Pine.LNX.4.44.0208031230400.9758-100000@home.transmeta.com>


torvalds@transmeta.com said:
>  I don't think that non-cache-coherency wrt DMA necessarily means that
> that is true, though. If you flush all CPU caches to memory before
> starting the DMA, and you invalidate the DMA'd memory range _after_
> the DMA finished, a "prefetch" on such an architecture is not a
> problem at all. 

OK -- assuming you actually do flush before the DMA and invalidate 
afterwards, that works. That's what I was missing; thanks :)

That's for a prefetch operation which doesn't mark the cache line 
dirty/owned. If you have random addresses used with 'write prefetch' 
operations, that's still going to be a problem.

--
dwmw2



  reply	other threads:[~2002-08-03 22:00 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2002-08-02  0:12 David Mosberger
2002-08-02 13:04 ` Alan Cox
2002-08-02 15:39   ` David Mosberger
2002-08-02 15:46     ` Linus Torvalds
2002-08-02 15:56       ` Dave Jones
2002-08-02 15:59         ` Linus Torvalds
2002-08-02 16:04           ` Dave Jones
2002-08-02 17:49       ` Alan Cox
2002-08-02 16:38         ` David Mosberger
2002-08-02 17:58           ` Alan Cox
2002-08-02 16:53             ` David Mosberger
2002-08-03 16:59       ` David Woodhouse
2002-08-03 17:22         ` Linus Torvalds
2002-08-03 17:39           ` David Woodhouse
2002-08-03 19:36             ` Linus Torvalds
2002-08-03 22:03               ` David Woodhouse [this message]
2002-08-03 22:40                 ` Linus Torvalds

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