Re: [PATCH v8 14/15] arm64: dts: cix: Add PCIe Root Complex on sky1

[Hans Zhang <hans.zhang@cixtech.com>]

On 2025/8/30 21:31, Manivannan Sadhasivam wrote:
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> On Tue, Aug 19, 2025 at 07:52:38PM GMT, hans.zhang@cixtech.com wrote:
>> From: Hans Zhang <hans.zhang@cixtech.com>
>>
>> Add pcie_x*_rc node to support Sky1 PCIe driver based on the
>> Cadence PCIe core.
>>
>> Supports Gen1/Gen2/Gen3/Gen4, 1/2/4/8 lane, MSI/MSI-x interrupts
>> using the ARM GICv3.
>>
>> Signed-off-by: Hans Zhang <hans.zhang@cixtech.com>
>> ---
>> Changes for v8:
>> - The rcsu register is split into two parts: rcsu_strap and rcsu_status.
>> ---
>>   arch/arm64/boot/dts/cix/sky1.dtsi | 126 ++++++++++++++++++++++++++++++
>>   1 file changed, 126 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
>> index 7dfe7677e649..26c325d8d934 100644
>> --- a/arch/arm64/boot/dts/cix/sky1.dtsi
>> +++ b/arch/arm64/boot/dts/cix/sky1.dtsi
>> @@ -288,6 +288,132 @@ mbox_ap2sfh: mailbox@80a0000 {
>>                        cix,mbox-dir = "tx";
>>                };
>>
>> +             pcie_x8_rc: pcie@a010000 {
>> +                     compatible = "cix,sky1-pcie-host";
>> +                     reg = <0x00 0x0a010000 0x00 0x10000>,
>> +                           <0x00 0x2c000000 0x00 0x4000000>,
>> +                           <0x00 0x0a000300 0x00 0x100>,
>> +                           <0x00 0x0a000400 0x00 0x100>,
>> +                           <0x00 0x60000000 0x00 0x00100000>;
>> +                     reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
>> +                     ranges = <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>,
>> +                              <0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>,
>> +                              <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>;
>> +                     #address-cells = <3>;
>> +                     #size-cells = <2>;
>> +                     bus-range = <0xc0 0xff>;
> 
> Isn't each controller in separate domain? Or as per the hw design, all
> controllers are under a single domain sharing the busses?
> 
Dear Mani,

Thank you very much for your reply.

No. The design of each of our controller ECAM is fixed in the hardware 
design. This can be reflected in DTS. The specific attribute is: "cfg".

Best regards,
Hans

> - Mani
> 
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