From: Hans Zhang <hans.zhang@cixtech.com>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com,
robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, mpillai@cadence.com,
fugang.duan@cixtech.com, guoyin.chen@cixtech.com,
peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v8 15/15] arm64: dts: cix: Enable PCIe on the Orion O6 board
Date: Mon, 1 Sep 2025 11:17:53 +0800 [thread overview]
Message-ID: <7abd8eb3-7ec1-474d-9595-f229cd2c9c68@cixtech.com> (raw)
In-Reply-To: <011b1e32-10e6-460a-bb9d-95235d926ed6@cixtech.com>
On 2025/9/1 11:14, Hans Zhang wrote:
>
>
> On 2025/8/30 21:33, Manivannan Sadhasivam wrote:
>> [Some people who received this message don't often get email from
>> mani@kernel.org. Learn why this is important at
>> https://aka.ms/LearnAboutSenderIdentification ]
>>
>> EXTERNAL EMAIL
>>
>> On Tue, Aug 19, 2025 at 07:52:39PM GMT, hans.zhang@cixtech.com wrote:
>>> From: Hans Zhang <hans.zhang@cixtech.com>
>>>
>>> Add PCIe RC support on Orion O6 board.
>>>
>>
>> So with this patch (and dependencies), the endpoints are detected and
>> usable?
>> Any limitation with not supporting the GPIO and pinctrl should be
>> documented in
>> the description.
>>
>
> Dear Mani,
>
> Thank you very much for your reply.
>
> We can rely on the initialization of bios. After the GPIO and pinctrl
> are upstream later, we will add them in.
>
> Just as I described in the change log of the cover letter, we can
> enumerate devices normally and use the network normally.
>
> Just as the first version of this driver also did not have GPIO,
> pinctrl. Moreover, Arnd also suggested that we could separate the upstream.
> drivers/pci/controller/dwc/pcie-amd-mdb.c
>
>
> This is the situation of running the latest linux kernel on our O6 board.
> root@cix-localhost:~# uname -a
> Linux cix-localhost 6.17.0-rc4-00015-g5aaae89e41ab #203 SMP PREEMPT Mon
> Sep 1 10:54:16 CST 2025 aarch64 GNU/Linux
> root@cix-localhost:~# lspci
> 0000:c0:00.0 PCI bridge: Device 1f6c:0001
> 0000:c1:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. Device
> 8126 (rev 01)
> 0001:90:00.0 PCI bridge: Device 1f6c:0001
> 0001:91:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd
> NVMe SSD Controller S4LV008[Pascal]
> 0002:60:00.0 PCI bridge: Device 1f6c:0001
> 0002:61:00.0 Network controller: Realtek Semiconductor Co., Ltd.
> RTL8852BE PCIe 802.11ax Wireless Network Controller
> 0003:00:00.0 PCI bridge: Device 1f6c:0001
> 0003:01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. Device
> 8126 (rev 01)
> 0004:30:00.0 PCI bridge: Device 1f6c:0001
> 0004:31:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. Device
> 8126 (rev 01)
>
>
Dear Mani,
In the next version, I will add it in the description.
Best regards,
Hans
>
> Best regards,
> Hans
>
>
>> - Mani
>>
>>> Signed-off-by: Hans Zhang <hans.zhang@cixtech.com>
>>> ---
>>> Dear Krzysztof,
>>>
>>> Due to the fact that the GPIO, PINCTRL and other modules of our
>>> platform are
>>> not yet ready for upstream. Attributes that PCIe depends on, such as
>>> reset-gpios
>>> and pinctrl*, have not been added for the time being. It will be
>>> added gradually
>>> in the future.
>>>
>>> The following are Arnd's previous comments. We can go to upsteam
>>> separately.
>>> https://lore.kernel.org/all/422deb4d-db29-48c1-b0c9-7915951df500@app.fastmail.com/
>>> ---
>>> arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 20 ++++++++++++++++++++
>>> 1 file changed, 20 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
>>> b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
>>> index d74964d53c3b..be3ec4f5d11e 100644
>>> --- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
>>> +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
>>> @@ -34,6 +34,26 @@ linux,cma {
>>>
>>> };
>>>
>>> +&pcie_x8_rc {
>>> + status = "okay";
>>> +};
>>> +
>>> +&pcie_x4_rc {
>>> + status = "okay";
>>> +};
>>> +
>>> +&pcie_x2_rc {
>>> + status = "okay";
>>> +};
>>> +
>>> +&pcie_x1_0_rc {
>>> + status = "okay";
>>> +};
>>> +
>>> +&pcie_x1_1_rc {
>>> + status = "okay";
>>> +};
>>> +
>>> &uart2 {
>>> status = "okay";
>>> };
>>> --
>>> 2.49.0
>>>
>>
>> --
>> மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2025-09-01 3:17 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-19 11:52 [PATCH v8 00/15] Enhance the PCIe controller driver for next generation controllers hans.zhang
2025-08-19 11:52 ` [PATCH v8 01/15] PCI: cadence: Add module support for platform controller driver hans.zhang
2025-08-19 11:52 ` [PATCH v8 02/15] PCI: cadence: Split PCIe controller header file hans.zhang
2025-08-19 11:52 ` [PATCH v8 03/15] PCI: cadence: Add register definitions for High Perf Architecture (HPA) hans.zhang
2025-08-19 17:36 ` ALOK TIWARI
2025-08-20 8:14 ` Manikandan Karunakaran Pillai
2025-08-19 11:52 ` [PATCH v8 04/15] PCI: cadence: Add helper functions for supporting " hans.zhang
2025-08-19 11:52 ` [PATCH v8 05/15] PCI: cadence: Move PCIe EP common functions to a separate file hans.zhang
2025-08-19 17:46 ` ALOK TIWARI
2025-08-19 11:52 ` [PATCH v8 06/15] PCI: cadence: Move PCIe RP " hans.zhang
2025-08-30 10:36 ` Manivannan Sadhasivam
2025-09-01 4:30 ` Manikandan Karunakaran Pillai
2025-08-19 11:52 ` [PATCH v8 07/15] PCI: cadence: Move PCIe controller common functions as " hans.zhang
2025-08-30 11:21 ` Manivannan Sadhasivam
2025-09-01 4:30 ` Manikandan Karunakaran Pillai
2025-08-19 11:52 ` [PATCH v8 08/15] PCI: cadence: Add support for High Perf Architecture (HPA) controller hans.zhang
2025-08-26 12:08 ` kernel test robot
2025-08-30 13:18 ` Manivannan Sadhasivam
2025-09-01 4:34 ` Manikandan Karunakaran Pillai
2025-08-19 11:52 ` [PATCH v8 09/15] PCI: cadence: Update PCIe platform to use register offsets passed hans.zhang
2025-08-19 11:52 ` [PATCH v8 10/15] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings hans.zhang
2025-08-20 7:23 ` Krzysztof Kozlowski
2025-08-19 11:52 ` [PATCH v8 11/15] PCI: Add Cix Technology Vendor and Device ID hans.zhang
2025-08-30 13:20 ` Manivannan Sadhasivam
2025-08-30 13:21 ` Manivannan Sadhasivam
2025-09-01 3:03 ` Hans Zhang
2025-08-19 11:52 ` [PATCH v8 12/15] PCI: sky1: Add PCIe host support for CIX Sky1 hans.zhang
2025-08-30 13:29 ` Manivannan Sadhasivam
2025-09-01 3:04 ` Hans Zhang
2025-08-19 11:52 ` [PATCH v8 13/15] MAINTAINERS: add entry for CIX Sky1 PCIe driver hans.zhang
2025-08-19 11:52 ` [PATCH v8 14/15] arm64: dts: cix: Add PCIe Root Complex on sky1 hans.zhang
2025-08-30 13:31 ` Manivannan Sadhasivam
2025-09-01 3:09 ` Hans Zhang
2025-08-19 11:52 ` [PATCH v8 15/15] arm64: dts: cix: Enable PCIe on the Orion O6 board hans.zhang
2025-08-30 13:33 ` Manivannan Sadhasivam
2025-09-01 3:14 ` Hans Zhang
2025-09-01 3:17 ` Hans Zhang [this message]
2025-08-30 13:38 ` [PATCH v8 00/15] Enhance the PCIe controller driver for next generation controllers Manivannan Sadhasivam
2025-09-01 4:28 ` Manikandan Karunakaran Pillai
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