[PATCH 0/2] gpio: aspeed: Fix lost interrupts from write-1-to-clear status bits

[PATCH 0/2] gpio: aspeed: Fix lost interrupts from write-1-to-clear status bits

[Billy Tsai]

The Aspeed GPIO interrupt status bits are write-1-to-clear on every
generation, but the driver updates them with read-modify-write helpers
that write a pending status bit back as 1. Each write therefore clears
interrupts that have not been handled yet.

Patch 1 fixes G4 (AST2400/AST2500/AST2600), where the status register
covers a 32-line bank. Acking one line clears every interrupt pending
in the bank, and an edge that latches after the handler has read the
status register is lost. This was observed on an AST2600 BMC with two
lines of the same bank toggling together at host power-off.

Patch 2 fixes G7 (AST2700), where each line's status bit sits in that
line's own control register. Updating any other field of the register
while the line's interrupt is pending clears it.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
Billy Tsai (2):
      gpio: aspeed: Clear only the acked line's G4 interrupt status
      gpio: aspeed: Preserve the pending G7 interrupt status on control writes

 drivers/gpio/gpio-aspeed.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)
---
base-commit: 65ba8f34ec886ec72b2c07ddc8cf3d815c32869d
change-id: 20261104-gpio-aspeed-irq-status-1fc21a4edfcf

Best regards,
-- 
Billy Tsai <billy_tsai@aspeedtech.com>

[PATCH 1/2] gpio: aspeed: Clear only the acked line's G4 interrupt status

[Billy Tsai]

The G4 interrupt status registers are write-1-to-clear: writing 0 to a
bit has no effect and writing 1 clears that line's status flag.
aspeed_gpio_irq_ack() clears a line's status through
aspeed_g4_reg_bit_set(), which reads the bank's status register, sets
the line's bit and writes the whole value back. That write clears every
interrupt pending in the 32-line bank, not just the acked one.

aspeed_gpio_irq_handler() reads each bank's status register once and
dispatches the lines that were set. If another line in the same bank
latches an edge after that read and before an ack in the bank, the ack
clears its status and the handler is never called for it, so the edge
is lost.

Write only the line's own bit when clearing the interrupt status on G4.

Fixes: 79fc9a2fcc45 ("gpio: aspeed: Create llops to handle hardware access")
Cc: stable@vger.kernel.org
Reported-by: Aaron Antone <aae@amazon.com>
Suggested-by: Aaron Antone <aae@amazon.com>
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
 drivers/gpio/gpio-aspeed.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
index dc53b2decb66..2482f2ff735d 100644
--- a/drivers/gpio/gpio-aspeed.c
+++ b/drivers/gpio/gpio-aspeed.c
@@ -1041,6 +1041,17 @@ static void aspeed_g4_reg_bit_set(struct aspeed_gpio *gpio, unsigned int offset,
 	void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg);
 	u32 temp;
 
+	/*
+	 * The interrupt status register is write-1-to-clear. Write only this
+	 * line's bit so that interrupts pending on the other lines of the bank
+	 * stay latched.
+	 */
+	if (reg == reg_irq_status) {
+		if (val)
+			iowrite32(GPIO_BIT(offset), addr);
+		return;
+	}
+
 	if (reg == reg_val)
 		temp = gpio->dcache[GPIO_BANK(offset)];
 	else

-- 
2.34.1

[PATCH 2/2] gpio: aspeed: Preserve the pending G7 interrupt status on control writes

[Billy Tsai]

On G7 each line has its own control register, and its interrupt status
bit (bit 12) is write-1-to-clear. aspeed_g7_reg_bit_set() updates a
field by reading the control register, replacing that field and writing
the value back. When the line's interrupt is pending, the status bit
reads as 1 and is written back as 1, so updating an unrelated field
such as the interrupt enable, trigger type, direction or debounce
selection also clears the pending interrupt.

Mask out the status bit when composing the value to write, so it is
written as 1 only when the status field itself is being set to ack the
interrupt.

Fixes: b2e861bd1eaf ("gpio: aspeed: Support G7 Aspeed gpio controller")
Cc: stable@vger.kernel.org
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
 drivers/gpio/gpio-aspeed.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
index 2482f2ff735d..6e834e83915b 100644
--- a/drivers/gpio/gpio-aspeed.c
+++ b/drivers/gpio/gpio-aspeed.c
@@ -1168,7 +1168,13 @@ static void aspeed_g7_reg_bit_set(struct aspeed_gpio *gpio, unsigned int offset,
 	u32 write_val;
 
 	if (mask) {
-		write_val = (ioread32(addr) & ~(mask)) | field_prep(mask, val);
+		/*
+		 * The interrupt status bit is write-1-to-clear. Keep it zero
+		 * unless it is the field being written, so that updating any
+		 * other field leaves a pending interrupt latched.
+		 */
+		write_val = ioread32(addr) & ~(mask | GPIO_G7_CTRL_IRQ_STS);
+		write_val |= field_prep(mask, val);
 		iowrite32(write_val, addr);
 	}
 }

-- 
2.34.1

Re: [PATCH 1/2] gpio: aspeed: Clear only the acked line's G4 interrupt status

[Andrew Jeffery]

On Wed, 2026-11-04 at 11:58 +0800, Billy Tsai wrote:
> The G4 interrupt status registers are write-1-to-clear: writing 0 to a
> bit has no effect and writing 1 clears that line's status flag.
> aspeed_gpio_irq_ack() clears a line's status through
> aspeed_g4_reg_bit_set(), which reads the bank's status register, sets
> the line's bit and writes the whole value back. That write clears every
> interrupt pending in the 32-line bank, not just the acked one.
> 
> aspeed_gpio_irq_handler() reads each bank's status register once and
> dispatches the lines that were set. If another line in the same bank
> latches an edge after that read and before an ack in the bank, the ack
> clears its status and the handler is never called for it, so the edge
> is lost.
> 
> Write only the line's own bit when clearing the interrupt status on G4.
> 
> Fixes: 79fc9a2fcc45 ("gpio: aspeed: Create llops to handle hardware access")
> Cc: stable@vger.kernel.org
> Reported-by: Aaron Antone <aae@amazon.com>
> Suggested-by: Aaron Antone <aae@amazon.com>

Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au>

Re: [PATCH 2/2] gpio: aspeed: Preserve the pending G7 interrupt status on control writes

[Andrew Jeffery]

On Wed, 2026-11-04 at 11:58 +0800, Billy Tsai wrote:
> On G7 each line has its own control register, and its interrupt status
> bit (bit 12) is write-1-to-clear. aspeed_g7_reg_bit_set() updates a
> field by reading the control register, replacing that field and writing
> the value back. When the line's interrupt is pending, the status bit
> reads as 1 and is written back as 1, so updating an unrelated field
> such as the interrupt enable, trigger type, direction or debounce
> selection also clears the pending interrupt.
> 
> Mask out the status bit when composing the value to write, so it is
> written as 1 only when the status field itself is being set to ack the
> interrupt.
> 
> Fixes: b2e861bd1eaf ("gpio: aspeed: Support G7 Aspeed gpio controller")
> Cc: stable@vger.kernel.org
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>

Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>

Re: [PATCH 0/2] gpio: aspeed: Fix lost interrupts from write-1-to-clear status bits

[Bartosz Golaszewski]

On Wed, 04 Nov 2026 11:58:34 +0800, Billy Tsai wrote:
> The Aspeed GPIO interrupt status bits are write-1-to-clear on every
> generation, but the driver updates them with read-modify-write helpers
> that write a pending status bit back as 1. Each write therefore clears
> interrupts that have not been handled yet.
> 
> Patch 1 fixes G4 (AST2400/AST2500/AST2600), where the status register
> covers a 32-line bank. Acking one line clears every interrupt pending
> in the bank, and an edge that latches after the handler has read the
> status register is lost. This was observed on an AST2600 BMC with two
> lines of the same bank toggling together at host power-off.
> 
> [...]

Applied, thanks!

[1/2] gpio: aspeed: Clear only the acked line's G4 interrupt status
      https://git.kernel.org/brgl/c/5d362564bd2982def7e80d7f1e756a97440c7adb
[2/2] gpio: aspeed: Preserve the pending G7 interrupt status on control writes
      https://git.kernel.org/brgl/c/18cc1d1ad94df8a6760fff2617d3d6923550cba0

Best regards,
-- 
Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>