[PATCH] arm64: dts: qcom: qcs6490-rb3gen2: Add SPI3 QUP core bandwidth OPP

[PATCH] arm64: dts: qcom: qcs6490-rb3gen2: Add SPI3 QUP core bandwidth OPP

[Viken Dadhaniya]

Short SPI transfers are sensitive to the bandwidth available on the QUP
core interconnect path. An insufficient vote delays Serial Engine
register and FIFO accesses, increasing command-dispatch latency.

Add a dedicated SPI3 OPP table with the valid 75 MHz and 100 MHz
source-clock and RPMh power-domain OPPs. Add a 100000 kBps average and
peak vote for the QUP core interconnect path. This improves MCP2518FD CAN
payload throughput by approximately 38%.

Limit the vote to SPI3 on RB3Gen2, where it serves the MCP2518FD CAN
controller and its frequent short SPI transfers. Other QUP/SPI instances
do not require this vote, so avoid raising their interconnect bandwidth
unnecessarily.

Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index 909039816a21..bbc16f5cb808 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -85,6 +85,24 @@ lt9611_1v2: lt9611-vdd12-regulator {
 		regulator-max-microvolt = <1200000>;
 	};
 
+	qup_spi3_opp_table: opp-table-spi3 {
+		compatible = "operating-points-v2";
+
+		opp-75000000 {
+			opp-hz = /bits/ 64 <75000000>;
+			required-opps = <&rpmhpd_opp_low_svs>;
+			opp-peak-kBps = <100000 0>;
+			opp-avg-kBps = <100000 0>;
+		};
+
+		opp-100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			required-opps = <&rpmhpd_opp_svs>;
+			opp-peak-kBps = <100000 0>;
+			opp-avg-kBps = <100000 0>;
+		};
+	};
+
 	reserved-memory {
 		xbl_mem: xbl@80700000 {
 			reg = <0x0 0x80700000 0x0 0x100000>;
@@ -1228,6 +1246,7 @@ platform {
 };
 
 &spi3 {
+	operating-points-v2 = <&qup_spi3_opp_table>;
 	status = "okay";
 
 	can@0 {

---
base-commit: 20a33c6b6cbe7e4805dfb6cd68816937443aa148
change-id: 20261025-qcs6490-spi3-opp-table-eae8724e9215

Best regards,
--  
Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>

Re: [PATCH] arm64: dts: qcom: qcs6490-rb3gen2: Add SPI3 QUP core bandwidth OPP

[Konrad Dybcio]

On 10/25/26 2:43 PM, Viken Dadhaniya wrote:
> Short SPI transfers are sensitive to the bandwidth available on the QUP
> core interconnect path. An insufficient vote delays Serial Engine
> register and FIFO accesses, increasing command-dispatch latency.
> 
> Add a dedicated SPI3 OPP table with the valid 75 MHz and 100 MHz
> source-clock and RPMh power-domain OPPs. Add a 100000 kBps average and
> peak vote for the QUP core interconnect path. This improves MCP2518FD CAN
> payload throughput by approximately 38%.
> 
> Limit the vote to SPI3 on RB3Gen2, where it serves the MCP2518FD CAN
> controller and its frequent short SPI transfers. Other QUP/SPI instances
> do not require this vote, so avoid raising their interconnect bandwidth
> unnecessarily.

You can solve the general problem OR you can do what this and
create more work down the line. What if I connect a MCP2518FD
on SPI4? SPI5? SPI6?

Konrad

Re: [PATCH] arm64: dts: qcom: qcs6490-rb3gen2: Add SPI3 QUP core bandwidth OPP

[Viken Dadhaniya]

On 10/26/2026 6:19 PM, Konrad Dybcio wrote:
> On 10/25/26 2:43 PM, Viken Dadhaniya wrote:
>> Short SPI transfers are sensitive to the bandwidth available on the QUP
>> core interconnect path. An insufficient vote delays Serial Engine
>> register and FIFO accesses, increasing command-dispatch latency.
>>
>> Add a dedicated SPI3 OPP table with the valid 75 MHz and 100 MHz
>> source-clock and RPMh power-domain OPPs. Add a 100000 kBps average and
>> peak vote for the QUP core interconnect path. This improves MCP2518FD CAN
>> payload throughput by approximately 38%.
>>
>> Limit the vote to SPI3 on RB3Gen2, where it serves the MCP2518FD CAN
>> controller and its frequent short SPI transfers. Other QUP/SPI instances
>> do not require this vote, so avoid raising their interconnect bandwidth
>> unnecessarily.
> 
> You can solve the general problem OR you can do what this and
> create more work down the line. What if I connect a MCP2518FD
> on SPI4? SPI5? SPI6?
> 
> Konrad

I understand the concern about supporting this on other SPI instances.
Moving the MCP2518FD would require a board wiring change and corresponding
DT updates, which could include its bandwidth requirement. On RB3Gen2,
it is connected to SPI3, so this patch scopes the vote to that instance.
Other tested SPI clients do not have KPI issues, which is why I kept
this change specific to the current board configuration.