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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: James Clark <james.clark@arm.com>,
	mathieu.poirier@linaro.org, coresight@lists.linaro.org
Cc: leo.yan@linaro.com, mike.leach@linaro.org,
	Leo Yan <leo.yan@linaro.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/1] coresight: no-op refactor to make INSTP0 check more idiomatic
Date: Thu, 3 Feb 2022 12:10:13 +0000	[thread overview]
Message-ID: <30df2340-c3b6-a5f2-5e7e-32eb89a51b68@arm.com> (raw)
In-Reply-To: <20220203115336.119735-2-james.clark@arm.com>

On 03/02/2022 11:53, James Clark wrote:
> The spec says this:
> 
>    P0 tracing support field. The permitted values are:
>        0b00  Tracing of load and store instructions as P0 elements is not
>              supported.
>        0b11  Tracing of load and store instructions as P0 elements is
>              supported, so TRCCONFIGR.INSTP0 is supported.
> 
>              All other values are reserved.
> 
> The value we are looking for is 0b11 so simplify this. The double read
> and && was a bit obfuscated.
> 
> Suggested-by: Suzuki Poulose <suzuki.poulose@arm.com>
> Signed-off-by: James Clark <james.clark@arm.com>

Thanks, Queued.

Cheers
Suzuki

      reply	other threads:[~2022-02-03 12:10 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-03 11:53 [PATCH 0/1] " James Clark
2022-02-03 11:53 ` [PATCH 1/1] " James Clark
2022-02-03 12:10   ` Suzuki K Poulose [this message]

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