From: James Clark <james.clark@arm.com>
To: suzuki.poulose@arm.com, mathieu.poirier@linaro.org,
coresight@lists.linaro.org
Cc: leo.yan@linaro.com, mike.leach@linaro.org,
James Clark <james.clark@arm.com>, Leo Yan <leo.yan@linaro.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 1/1] coresight: no-op refactor to make INSTP0 check more idiomatic
Date: Thu, 3 Feb 2022 11:53:35 +0000 [thread overview]
Message-ID: <20220203115336.119735-2-james.clark@arm.com> (raw)
In-Reply-To: <20220203115336.119735-1-james.clark@arm.com>
The spec says this:
P0 tracing support field. The permitted values are:
0b00 Tracing of load and store instructions as P0 elements is not
supported.
0b11 Tracing of load and store instructions as P0 elements is
supported, so TRCCONFIGR.INSTP0 is supported.
All other values are reserved.
The value we are looking for is 0b11 so simplify this. The double read
and && was a bit obfuscated.
Suggested-by: Suzuki Poulose <suzuki.poulose@arm.com>
Signed-off-by: James Clark <james.clark@arm.com>
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index bf18128cf5de..e2eebd865241 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -1091,7 +1091,7 @@ static void etm4_init_arch_data(void *info)
etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
/* INSTP0, bits[2:1] P0 tracing support field */
- if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
+ if (BMVAL(etmidr0, 1, 2) == 0b11)
drvdata->instrp0 = true;
else
drvdata->instrp0 = false;
--
2.28.0
next prev parent reply other threads:[~2022-02-03 11:54 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-03 11:53 [PATCH 0/1] " James Clark
2022-02-03 11:53 ` James Clark [this message]
2022-02-03 12:10 ` [PATCH 1/1] " Suzuki K Poulose
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