[PATCH net-next 0/4] net: Add Allwinner H616/H618 EMAC1 and AC300 EPHY support

[PATCH net-next 0/4] net: Add Allwinner H616/H618 EMAC1 and AC300 EPHY support

[Alastair D'Silva]

This series adds support for the secondary Ethernet MAC controller (EMAC1)
and the co-packaged AC300 Fast Ethernet Physical Layer (EPHY) found on
Allwinner H616 and H618 SoCs.

The Allwinner H616/H618 SoCs feature two EMAC instances: EMAC0 (typically
used with an external RGMII Gigabit PHY) and EMAC1 (Fast Ethernet,
connected internally to the co-packaged AC300 EPHY). EMAC1 uses a
dedicated clock control register in the syscon register space, which is
accessed via an offset index in the DT syscon property.

The AC300 is an integrated 10/100M (100BASE-TX / 10BASE-T) Fast Ethernet
PHY communicating over MDIO at address 16 + phy_addr. It requires
retrieving factory bandgap calibration data from the SID nvmem controller,
managing internal power rails and clocks, and optimizing transceiver signal
parameters.

To ensure reliable link establishment and MAC software reset with the
internal PHY, dwmac-sun8i is updated to defer MAC software reset until
sun8i_dwmac_init() after the internal PHY has powered on and begun
clock generation.

The series is structured as follows:
- Patch 1: DT binding for Allwinner AC300 EPHY.
- Patch 2: PHY driver for Allwinner AC300 EPHY.
- Patch 3: DT binding update for Allwinner H616 EMAC1 and syscon index.
- Patch 4: dwmac-sun8i driver support for H616 EMAC1 clock index and
           internal PHY deferred reset.

Testing:
- Tested on physical Mellow Fly-C5 hardware (Allwinner H618) running
  Armbian with sustained 100Mbps full-duplex network traffic (DHCP,
  iperf3, NFS rootfs).
- Device tree bindings validated with dt_binding_check.
- Separate SoC and board DTS additions will be submitted via the
  linux-sunxi tree.

Alastair D'Silva (4):
  dt-bindings: net: phy: Add Allwinner AC300 EPHY binding
  net: phy: Add Allwinner AC300 EPHY driver
  dt-bindings: net: allwinner,sun8i-a83t-emac: Add Allwinner H616 EMAC1
    and syscon index
  net: stmmac: dwmac-sun8i: Add Allwinner H616 EMAC clock index and
    internal PHY support

 .../net/allwinner,sun50i-h618-ac300-ephy.yaml |  79 +++++
 .../net/allwinner,sun8i-a83t-emac.yaml        |  14 +-
 .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c |  65 +++-
 drivers/net/phy/Kconfig                       |   9 +
 drivers/net/phy/Makefile                      |   1 +
 drivers/net/phy/ac300-phy.c                   | 331 ++++++++++++++++++
 6 files changed, 486 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun50i-h618-ac300-ephy.yaml
 create mode 100644 drivers/net/phy/ac300-phy.c

-- 
2.53.0

[PATCH net-next 1/4] dt-bindings: net: phy: Add Allwinner AC300 EPHY binding

[Alastair D'Silva]

Add device tree binding documentation for the Allwinner AC300
Fast Ethernet Physical Layer (EPHY) co-packaged on Allwinner
H616 and H618 SoCs.

Assisted-by: LLM
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
---

Notes:
    Tested on Mellow Fly-C5 (Allwinner H618) under Armbian with Linux 6.18 and
    7.x kernels, verifying schema validation with dt_binding_check.

 .../net/allwinner,sun50i-h618-ac300-ephy.yaml | 79 +++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun50i-h618-ac300-ephy.yaml

diff --git a/Documentation/devicetree/bindings/net/allwinner,sun50i-h618-ac300-ephy.yaml b/Documentation/devicetree/bindings/net/allwinner,sun50i-h618-ac300-ephy.yaml
new file mode 100644
index 000000000000..a04416e78138
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/allwinner,sun50i-h618-ac300-ephy.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/allwinner,sun50i-h618-ac300-ephy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner AC300 Ethernet PHY
+
+maintainers:
+  - Alastair D'Silva <alastair@d-silva.org>
+
+description:
+  The AC300 is an integrated Fast Ethernet Physical Layer (EPHY) co-packaged
+  with Allwinner H616 and H618 SoCs, communicated with over MDIO.
+
+allOf:
+  - $ref: ethernet-phy.yaml#
+
+select:
+  properties:
+    compatible:
+      contains:
+        const: allwinner,sun50i-h618-ac300-ephy
+  required:
+    - compatible
+
+properties:
+  compatible:
+    items:
+      - const: ethernet-phy-id0044.1400
+      - const: allwinner,sun50i-h618-ac300-ephy
+      - const: ethernet-phy-ieee802.3-c22
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    items:
+      - description: 25MHz reference clock from CCU
+      - description: 2MHz reference clock from PWM
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: ephy
+      - const: pwm
+
+  nvmem-cells:
+    items:
+      - description: Calibration data from SID
+
+  nvmem-cell-names:
+    items:
+      - const: calibration
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    mdio {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        ethernet-phy@0 {
+            compatible = "ethernet-phy-id0044.1400",
+                         "allwinner,sun50i-h618-ac300-ephy",
+                         "ethernet-phy-ieee802.3-c22";
+            reg = <0>;
+            clocks = <&ccu 81>, <&ac300_pwm_clk>;
+            clock-names = "ephy", "pwm";
+            nvmem-cells = <&ephy_calibration>;
+            nvmem-cell-names = "calibration";
+        };
+    };
-- 
2.53.0

Re: [PATCH net-next 1/4] dt-bindings: net: phy: Add Allwinner AC300 EPHY binding

[Andrew Lunn]

> +properties:
> +  compatible:
> +    items:
> +      - const: ethernet-phy-id0044.1400
> +      - const: allwinner,sun50i-h618-ac300-ephy

PHYs don't have compatibles which are vendor strings, only IDs or
c22/c45. PHYs get probed by ID, not these strings.

    Andrew

---
pw-bot: cr

Re: [PATCH net-next 1/4] dt-bindings: net: phy: Add Allwinner AC300 EPHY binding

[Rob Herring (Arm)]

On Wed, 16 Sep 2026 14:41:16 +1000, Alastair D'Silva wrote:
> Add device tree binding documentation for the Allwinner AC300
> Fast Ethernet Physical Layer (EPHY) co-packaged on Allwinner
> H616 and H618 SoCs.
> 
> Assisted-by: LLM
> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
> ---
> 
> Notes:
>     Tested on Mellow Fly-C5 (Allwinner H618) under Armbian with Linux 6.18 and
>     7.x kernels, verifying schema validation with dt_binding_check.
> 
>  .../net/allwinner,sun50i-h618-ac300-ephy.yaml | 79 +++++++++++++++++++
>  1 file changed, 79 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun50i-h618-ac300-ephy.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/net/allwinner,sun50i-h618-ac300-ephy.example.dtb: ethernet-phy@0 (ethernet-phy-id0044.1400): compatible: 'oneOf' conditional failed, one must be fixed:
	['ethernet-phy-id0044.1400', 'allwinner,sun50i-h618-ac300-ephy', 'ethernet-phy-ieee802.3-c22'] is too long
	'ethernet-phy-ieee802.3-c22' was expected
	'ethernet-phy-ieee802.3-c45' was expected
	from schema $id: http://devicetree.org/schemas/net/allwinner,sun50i-h618-ac300-ephy.yaml
Documentation/devicetree/bindings/net/allwinner,sun50i-h618-ac300-ephy.example.dtb: ethernet-phy@0 (ethernet-phy-id0044.1400): compatible: 'oneOf' conditional failed, one must be fixed:
	['ethernet-phy-id0044.1400', 'allwinner,sun50i-h618-ac300-ephy', 'ethernet-phy-ieee802.3-c22'] is too long
	'ethernet-phy-ieee802.3-c22' was expected
	'ethernet-phy-ieee802.3-c45' was expected
	from schema $id: http://devicetree.org/schemas/net/ethernet-phy.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.kernel.org/project/devicetree/patch/20260916044119.475666-2-alastair@d-silva.org

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

[PATCH net-next 2/4] net: phy: Add Allwinner AC300 EPHY driver

[Alastair D'Silva]

Add support for the Allwinner AC300 integrated Fast Ethernet Physical
Layer (EPHY) co-packaged on Allwinner H616 and H618 SoCs.

The driver communicates with the AC300 configuration space over MDIO
at address 16 + phy_addr, handles internal power domains, clock gating,
bandgap calibration retrieval from SID nvmem, and optimizes transceiver
signal path registers.

Assisted-by: LLM
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
---

Notes:
    Tested on Mellow Fly-C5 (Allwinner H618) under Armbian with sustained
    100Mbps traffic (DHCP, iperf3, NFS rootfs), verifying indirect MDIO
    register programming and bandgap calibration readout from SID nvmem.

 drivers/net/phy/Kconfig     |   9 +
 drivers/net/phy/Makefile    |   1 +
 drivers/net/phy/ac300-phy.c | 331 ++++++++++++++++++++++++++++++++++++
 3 files changed, 341 insertions(+)
 create mode 100644 drivers/net/phy/ac300-phy.c

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index b4ef927fd4a6..c473f0a814b7 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -120,6 +120,15 @@ config MESON_GXL_PHY
 	help
 	  Currently has a driver for the Amlogic Meson GXL Internal PHY
 
+config AC300_PHY
+	tristate "Allwinner AC300 EPHY support"
+	depends on OF && NVMEM
+	help
+	  Support for the Allwinner AC300 integrated Fast Ethernet Physical
+	  Layer (EPHY) co-packaged on Allwinner H616 and H618 SoCs. The AC300
+	  EPHY communicates over MDIO and provides 10/100 Mbps connectivity.
+	  If compiled as a module, it will be called ac300-phy.
+
 config ADIN_PHY
 	tristate "Analog Devices Industrial Ethernet PHYs"
 	help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 25c4a3c2429f..98453e68fd9f 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_SFP)		+= sfp.o
 sfp-obj-$(CONFIG_SFP)		+= sfp-bus.o
 obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
 
+obj-$(CONFIG_AC300_PHY)		+= ac300-phy.o
 obj-$(CONFIG_ADIN_PHY)		+= adin.o
 obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
 obj-$(CONFIG_ADIN1140_PHY)	+= adin1140-phy.o
diff --git a/drivers/net/phy/ac300-phy.c b/drivers/net/phy/ac300-phy.c
new file mode 100644
index 000000000000..c70f567c3179
--- /dev/null
+++ b/drivers/net/phy/ac300-phy.c
@@ -0,0 +1,331 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * Driver for X-Powers AC300 Ethernet PHY
+ *
+ * Datasheet: https://linux-sunxi.org/images/b/b2/AC300_User_Manual_V1.0_cleaned.pdf
+ *
+ * Copyright (c) 2026 Alastair D'Silva <alastair@d-silva.org>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+
+#define AC300_EPHY_ID			0x00441400
+#define AC300_EPHY_ID_MASK		0x0ffffff0
+
+/* AC300 Configuration Registers (on MDIO Address 16) */
+#define AC300_REG00_CHIP_VERSION_MASK	GENMASK(15, 12)
+#define AC300_REG00_PKG_STATUS_MASK	GENMASK(11, 8)
+#define AC300_REG00_EPHY_CLK_SEL_MASK	GENMASK(7, 6)
+#define AC300_REG00_EPHY_CLK_SEL_25M	0
+#define AC300_REG00_EPHY_CLK_SEL_27M	1
+#define AC300_REG00_EPHY_CLK_SEL_24M	2
+#define AC300_REG00_EFUSE_REG_CLK_GATING	BIT(5)
+#define AC300_REG00_EPHY_REG_CLK_GATING	BIT(4)
+#define AC300_REG00_MDIO_ERROR		BIT(3)
+#define AC300_REG00_CLKIN_GATING	BIT(2)
+#define AC300_REG00_EPHY_RESET_INVALID	BIT(1)
+#define AC300_REG00_CHIP_RESET		BIT(0)
+
+#define AC300_REG01_DEFAULT		0x1084
+#define AC300_REG01_BGTC_MASK		GENMASK(12, 8)
+#define AC300_REG01_BG_EN		BIT(7)
+#define AC300_REG01_BGV_MASK		GENMASK(5, 0)
+
+#define AC300_REG02_DEFAULT		0xC000
+#define AC300_REG02_DLDOEN		BIT(15)
+#define AC300_REG02_DLDOVOL_MASK	GENMASK(14, 12)
+
+#define AC300_REG05_DEFAULT		0xA800
+#define AC300_REG05_MDIO_DRV_MASK	GENMASK(15, 14)
+#define AC300_REG05_LED_DRV_MASK	GENMASK(13, 12)
+#define AC300_REG05_MII_DRV_MASK	GENMASK(11, 10)
+#define AC300_REG05_EPHY_IRQ_STATUS	BIT(9)
+#define AC300_REG05_EPHY_IRQ_ENABLE	BIT(8)
+#define AC300_REG05_CLKIN_PAD_EN	BIT(4)
+#define AC300_REG05_E_DPX_LED_IO_EN	BIT(3)
+#define AC300_REG05_E_SPD_LED_IO_EN	BIT(2)
+#define AC300_REG05_E_LNK_LED_IO_EN	BIT(1)
+#define AC300_REG05_EPHY_MII_IO_EN	BIT(0)
+
+#define AC300_REG06_DEFAULT		0x0001
+#define AC300_REG06_BGS_EFUSE_MASK	GENMASK(15, 12)
+#define AC300_REG06_XMII_SEL		BIT(11)
+#define AC300_REG06_EPHY_MODE_MASK	GENMASK(10, 9)
+#define AC300_REG06_BIST_CLK_EN		BIT(3)
+#define AC300_REG06_LED_POL		BIT(1)
+#define AC300_REG06_SHUTDOWN		BIT(0)
+
+struct ac300_phy_priv {
+	struct clk *ephy_clk;
+	struct clk *pwm_clk;
+	u16 caldata;
+};
+
+static int ac300_phy_disable(struct phy_device *phydev)
+{
+	struct mii_bus *bus = phydev->mdio.bus;
+	int cfg_addr = 16 + phydev->mdio.addr;
+	u16 val;
+	int ret;
+
+	val = 0x1f00 | FIELD_PREP(AC300_REG00_EPHY_CLK_SEL_MASK, AC300_REG00_EPHY_CLK_SEL_24M);
+	ret = mdiobus_write(bus, cfg_addr, 0x00, val);
+	if (ret)
+		return ret;
+
+	ret = mdiobus_write(bus, cfg_addr, 0x05, AC300_REG05_DEFAULT);
+	if (ret)
+		return ret;
+
+	return mdiobus_write(bus, cfg_addr, 0x06, AC300_REG06_SHUTDOWN);
+}
+
+static int ac300_phy_enable(struct phy_device *phydev)
+{
+	struct ac300_phy_priv *priv = phydev->priv;
+	struct mii_bus *bus = phydev->mdio.bus;
+	int cfg_addr = 16 + phydev->mdio.addr;
+	u16 val;
+	int ret;
+
+	/* Step 1: release reset */
+	val = 0x1f00 | FIELD_PREP(AC300_REG00_EPHY_CLK_SEL_MASK, AC300_REG00_EPHY_CLK_SEL_24M) |
+	      AC300_REG00_EPHY_RESET_INVALID | AC300_REG00_CHIP_RESET;
+	ret = mdiobus_write(bus, cfg_addr, 0x00, val);
+	if (ret)
+		return ret;
+	usleep_range(10000, 11000);
+
+	/* Step 2: clk gating */
+	val |= AC300_REG00_EPHY_REG_CLK_GATING | AC300_REG00_CLKIN_GATING |
+	       AC300_REG00_EFUSE_REG_CLK_GATING;
+	ret = mdiobus_write(bus, cfg_addr, 0x00, val);
+	if (ret)
+		return ret;
+	usleep_range(10000, 11000);
+
+	/* Step 2.5: Apply System BIAS Calibration */
+	val = AC300_REG01_DEFAULT;
+	if (priv->caldata)
+		val = (priv->caldata & (AC300_REG01_BGTC_MASK | AC300_REG01_BGV_MASK));
+	val |= AC300_REG01_BG_EN; /* Ensure Bandgap is enabled */
+	ret = mdiobus_write(bus, cfg_addr, 0x01, val);
+	if (ret)
+		return ret;
+	usleep_range(10000, 11000);
+
+	/* Step 3: SYS_IO setup */
+	val = AC300_REG05_DEFAULT | AC300_REG05_CLKIN_PAD_EN |
+	      AC300_REG05_EPHY_MII_IO_EN | AC300_REG05_E_DPX_LED_IO_EN;
+	ret = mdiobus_write(bus, cfg_addr, 0x05, val);
+	if (ret)
+		return ret;
+	usleep_range(10000, 11000);
+
+	/* Step 4: RMII Mode, SHUTDOWN=0, calibration & LED polarity */
+	val = 0;
+	if (phydev->interface == PHY_INTERFACE_MODE_RMII)
+		val |= AC300_REG06_XMII_SEL;
+	val |= AC300_REG06_LED_POL; /* LED_POL 1:Low active */
+	val &= ~(0x0F << 12);
+	val |= (0x0F & (0x03 + priv->caldata)) << 12;
+	ret = mdiobus_write(bus, cfg_addr, 0x06, val);
+	if (ret)
+		return ret;
+	msleep(100);
+
+	return 0;
+}
+
+static int ac300_phy_config_init(struct phy_device *phydev)
+{
+	struct ac300_phy_priv *priv = phydev->priv;
+	int ret;
+
+	/* Write page-based EPHY transceiver and signal path optimizations */
+	ret = phy_write(phydev, 0x1f, 0x0100); /* Switch to Page 1 */
+	if (ret)
+		return ret;
+	ret = phy_write(phydev, 0x12, 0x4824); /* Disable APS */
+	if (ret)
+		return ret;
+
+	ret = phy_write(phydev, 0x1f, 0x0200); /* Switch to Page 2 */
+	if (ret)
+		return ret;
+	ret = phy_write(phydev, 0x18, 0x0000); /* PHYAFE TRX optimization */
+	if (ret)
+		return ret;
+
+	ret = phy_write(phydev, 0x1f, 0x0600); /* Switch to Page 6 */
+	if (ret)
+		return ret;
+	if (priv->caldata & BIT(9)) {
+		ret = phy_write(phydev, 0x14, 0x7809); /* Fixed TX optimization */
+		if (ret)
+			return ret;
+		ret = phy_write(phydev, 0x13, 0xf000); /* Fixed RX optimization */
+		if (ret)
+			return ret;
+		ret = phy_write(phydev, 0x10, 0x5523);
+		if (ret)
+			return ret;
+		ret = phy_write(phydev, 0x15, 0x3533);
+		if (ret)
+			return ret;
+	} else {
+		ret = phy_write(phydev, 0x14, 0x708b); /* Default TX optimization */
+		if (ret)
+			return ret;
+		ret = phy_write(phydev, 0x13, 0xF000); /* Default RX optimization */
+		if (ret)
+			return ret;
+		ret = phy_write(phydev, 0x15, 0x1530);
+		if (ret)
+			return ret;
+	}
+
+	ret = phy_write(phydev, 0x1f, 0x0800); /* Switch to Page 8 */
+	if (ret)
+		return ret;
+	if (priv->caldata & BIT(9)) {
+		ret = phy_write(phydev, 0x1d, 0x0844); /* disable auto offset */
+		if (ret)
+			return ret;
+	}
+	ret = phy_write(phydev, 0x18, 0x00bc); /* PHYAFE TRX optimization */
+	if (ret)
+		return ret;
+
+	ret = phy_write(phydev, 0x1f, 0x0100); /* Switch to page 1 */
+	if (ret)
+		return ret;
+	ret = phy_clear_bits(phydev, 0x17, BIT(3)); /* Disable Intelligent EEE */
+	if (ret)
+		return ret;
+
+	/* Disable 802.3az EEE */
+	ret = phy_write(phydev, 0x1f, 0x0200); /* Switch to page 2 */
+	if (ret)
+		return ret;
+	ret = phy_write(phydev, 0x18, 0x0000);
+	if (ret)
+		return ret;
+	ret = phy_write(phydev, 0x1f, 0x0000); /* Switch to page 0 */
+	if (ret)
+		return ret;
+
+	return phy_clear_bits_mmd(phydev, 0x7, 0x3c, BIT(1));
+}
+
+static int ac300_phy_probe(struct phy_device *phydev)
+{
+	struct device *dev = &phydev->mdio.dev;
+	struct ac300_phy_priv *priv;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	phydev->priv = priv;
+
+	priv->ephy_clk = devm_clk_get_optional_enabled(dev, "ephy");
+	if (IS_ERR(priv->ephy_clk))
+		return dev_err_probe(dev, PTR_ERR(priv->ephy_clk),
+				     "Failed to request ephy clock\n");
+
+	priv->pwm_clk = devm_clk_get_optional_enabled(dev, "pwm");
+	if (IS_ERR(priv->pwm_clk))
+		return dev_err_probe(dev, PTR_ERR(priv->pwm_clk),
+				     "Failed to request pwm clock\n");
+
+	/* Read calibration data from NVMEM/SID */
+	ret = nvmem_cell_read_u16(dev, "calibration", &priv->caldata);
+	if (ret) {
+		if (ret == -EPROBE_DEFER)
+			return -EPROBE_DEFER;
+		dev_warn(dev, "Failed to read EPHY calibration (%pe)\n", ERR_PTR(ret));
+	} else {
+		dev_info(dev, "Read AC300 EPHY calibration: 0x%04x\n", priv->caldata);
+	}
+
+	return ac300_phy_enable(phydev);
+}
+
+static void ac300_phy_remove(struct phy_device *phydev)
+{
+	ac300_phy_disable(phydev);
+}
+
+static int ac300_phy_suspend(struct phy_device *phydev)
+{
+	int ret;
+
+	ret = ac300_phy_disable(phydev);
+	if (ret)
+		return ret;
+	return genphy_suspend(phydev);
+}
+
+static int ac300_phy_resume(struct phy_device *phydev)
+{
+	int ret;
+
+	ret = ac300_phy_enable(phydev);
+	if (ret)
+		return ret;
+	return genphy_resume(phydev);
+}
+
+static int ac300_phy_soft_reset(struct phy_device *phydev)
+{
+	int ret;
+
+	ret = ac300_phy_enable(phydev);
+	if (ret)
+		return ret;
+	return genphy_soft_reset(phydev);
+}
+
+static int ac300_phy_match_phy_device(struct phy_device *phydev,
+				      const struct phy_driver *phydrv)
+{
+	return of_device_is_compatible(phydev->mdio.dev.of_node,
+				       "allwinner,sun50i-h618-ac300-ephy");
+}
+
+static struct phy_driver ac300_phy_driver[] = {
+	{
+		.phy_id		= AC300_EPHY_ID,
+		.phy_id_mask	= AC300_EPHY_ID_MASK,
+		.name		= "Allwinner AC300 EPHY",
+		.features	= PHY_BASIC_FEATURES,
+		.match_phy_device = ac300_phy_match_phy_device,
+		.soft_reset	= ac300_phy_soft_reset,
+		.config_init	= ac300_phy_config_init,
+		.probe		= ac300_phy_probe,
+		.remove		= ac300_phy_remove,
+		.suspend	= ac300_phy_suspend,
+		.resume		= ac300_phy_resume,
+	}
+};
+module_phy_driver(ac300_phy_driver);
+
+MODULE_AUTHOR("Alastair D'Silva <alastair@d-silva.org>");
+MODULE_DESCRIPTION("X-Powers AC300 Ethernet PHY driver");
+MODULE_LICENSE("GPL");
+
+static const struct mdio_device_id __maybe_unused ac300_phy_tbl[] = {
+	{ AC300_EPHY_ID, AC300_EPHY_ID_MASK },
+	{ }
+};
+MODULE_DEVICE_TABLE(mdio, ac300_phy_tbl);
-- 
2.53.0

Re: [PATCH net-next 2/4] net: phy: Add Allwinner AC300 EPHY driver

[Andrew Lunn]

> +static int ac300_phy_config_init(struct phy_device *phydev)
> +{
> +	struct ac300_phy_priv *priv = phydev->priv;
> +	int ret;
> +
> +	/* Write page-based EPHY transceiver and signal path optimizations */
> +	ret = phy_write(phydev, 0x1f, 0x0100); /* Switch to Page 1 */
> +	if (ret)
> +		return ret;
> +	ret = phy_write(phydev, 0x12, 0x4824); /* Disable APS */
> +	if (ret)
> +		return ret;
> +
> +	ret = phy_write(phydev, 0x1f, 0x0200); /* Switch to Page 2 */
> +	if (ret)

Please implement .read_page and .write.page in struct phy_driver.

> +	/* Disable 802.3az EEE */
> +	ret = phy_write(phydev, 0x1f, 0x0200); /* Switch to page 2 */
> +	if (ret)
> +		return ret;

Is it broken? phy_disable_eee()?

> +	return phy_clear_bits_mmd(phydev, 0x7, 0x3c, BIT(1));

MDIO_MMD_AN, MDIO_AN_EEE_ADV.

With those magic numbers replaced with macros, i then have to ask what
is going on with EEE.

I also hope you see why magic numbers are bad and should where ever
possible be replaced to meaningful macros.

> +	/* Read calibration data from NVMEM/SID */
> +	ret = nvmem_cell_read_u16(dev, "calibration", &priv->caldata);
> +	if (ret) {
> +		if (ret == -EPROBE_DEFER)
> +			return -EPROBE_DEFER;
> +		dev_warn(dev, "Failed to read EPHY calibration (%pe)\n", ERR_PTR(ret));

Take a look at dev_err_probe().

> +static int ac300_phy_match_phy_device(struct phy_device *phydev,
> +				      const struct phy_driver *phydrv)
> +{
> +	return of_device_is_compatible(phydev->mdio.dev.of_node,
> +				       "allwinner,sun50i-h618-ac300-ephy");
> +}

Why?

	Andrew

[PATCH net-next 3/4] dt-bindings: net: allwinner,sun8i-a83t-emac: Add Allwinner H616 EMAC1 and syscon index

[Alastair D'Silva]

Document the Allwinner H616 EMAC1 and internal EMAC compatible strings
("allwinner,sun50i-h616-emac1" and "allwinner,sun50i-h616-internal-emac").
Update the syscon property schema to support an optional register index
offset argument, allowing boards to reference the secondary EMAC clock
register on H616/H618 SoCs.

Assisted-by: LLM
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
---

Notes:
    Tested against Allwinner H616/H618 device trees in Armbian, verifying
    schema validation with dt_binding_check.

 .../bindings/net/allwinner,sun8i-a83t-emac.yaml    | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
index 323a669fa982..cd1075dab581 100644
--- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
+++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
@@ -39,6 +39,8 @@ properties:
               - allwinner,sun50i-a100-emac
               - allwinner,sun50i-h6-emac
               - allwinner,sun50i-h616-emac0
+              - allwinner,sun50i-h616-emac1
+              - allwinner,sun50i-h616-internal-emac
               - allwinner,sun55i-a523-gmac0
           - const: allwinner,sun50i-a64-emac
       - items:
@@ -71,10 +73,16 @@ properties:
     maxItems: 1
 
   syscon:
-    $ref: /schemas/types.yaml#/definitions/phandle
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - minItems: 1
+        maxItems: 2
+        items:
+          - description: Phandle to the device containing the EMAC or GMAC clock register
+          - description: Register index offset (0 for EMAC0, 1 for EMAC1)
     description:
-      Phandle to the device containing the EMAC or GMAC clock
-      register
+      Phandle to the device containing the EMAC or GMAC clock register,
+      with an optional register index (0 for EMAC0, 1 for EMAC1).
 
 required:
   - compatible
-- 
2.53.0

Re: [PATCH net-next 3/4] dt-bindings: net: allwinner,sun8i-a83t-emac: Add Allwinner H616 EMAC1 and syscon index

[Rob Herring (Arm)]

On Wed, 16 Sep 2026 14:41:18 +1000, Alastair D'Silva wrote:
> Document the Allwinner H616 EMAC1 and internal EMAC compatible strings
> ("allwinner,sun50i-h616-emac1" and "allwinner,sun50i-h616-internal-emac").
> Update the syscon property schema to support an optional register index
> offset argument, allowing boards to reference the secondary EMAC clock
> register on H616/H618 SoCs.
> 
> Assisted-by: LLM
> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
> ---
> 
> Notes:
>     Tested against Allwinner H616/H618 device trees in Armbian, verifying
>     schema validation with dt_binding_check.
> 
>  .../bindings/net/allwinner,sun8i-a83t-emac.yaml    | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml: properties:syscon:items:0: {'minItems': 1, 'maxItems': 2, 'items': [{'description': 'Phandle to the device containing the EMAC or GMAC clock register'}, {'description': 'Register index offset (0 for EMAC0, 1 for EMAC1)'}]} should not be valid under {'required': ['maxItems']}
	hint: "maxItems" is not needed with an "items" list
	from schema $id: http://devicetree.org/meta-schemas/items.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.kernel.org/project/devicetree/patch/20260916044119.475666-4-alastair@d-silva.org

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

[PATCH net-next 4/4] net: stmmac: dwmac-sun8i: Add Allwinner H616 EMAC clock index and internal PHY support

[Alastair D'Silva]

Support EMAC1 and the internal Fast Ethernet PHY (AC300) on Allwinner
H616 and H618 SoCs:
- Allow reading a register index from the syscon property to offset the
  regmap field for EMAC1's dedicated clock control register.
- Add emac_variant_h616_internal with support for internal PHY, MII,
  RMII, and RGMII modes.
- Delay the MAC software reset until sun8i_dwmac_init() when using the
  internal PHY, ensuring the PHY has powered on and begun generating
  the receive clock before the MAC attempts to reset.
- Skip setting H3_EPHY_SELECT for H616 internal EMAC, which does not
  use the H3-style EPHY select bit.
- Handle -EPROBE_DEFER cleanly during clock and reset control acquisition
  in get_ephy_nodes().

Assisted-by: LLM
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
---

Notes:
    Tested on Mellow Fly-C5 (Allwinner H618) under Armbian, verifying stable
    EMAC1 probe, deferred soft reset with the internal AC300 EPHY, and 100M full
    duplex operation under load.

 .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 65 ++++++++++++++++---
 1 file changed, 55 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 48c52eb96233..1728893589a6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -130,6 +130,16 @@ static const struct emac_variant emac_variant_a64 = {
 	.tx_delay_max = 7,
 };
 
+static const struct emac_variant emac_variant_h616_internal = {
+	.syscon_field = &sun8i_syscon_reg_field,
+	.soc_has_internal_phy = true,
+	.support_mii = true,
+	.support_rmii = true,
+	.support_rgmii = true,
+	.rx_delay_max = 31,
+	.tx_delay_max = 7,
+};
+
 static const struct emac_variant emac_variant_h6 = {
 	.syscon_field = &sun8i_syscon_reg_field,
 	/* The "Internal PHY" of H6 is not on the die. It's on the
@@ -570,6 +580,7 @@ static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = {
 };
 
 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv);
+static int sun8i_dwmac_reset(struct stmmac_priv *priv);
 
 static int sun8i_dwmac_init(struct device *dev, void *priv)
 {
@@ -589,6 +600,10 @@ static int sun8i_dwmac_init(struct device *dev, void *priv)
 		ret = sun8i_dwmac_power_internal_phy(netdev_priv(ndev));
 		if (ret)
 			goto err_disable_regulator;
+
+		ret = sun8i_dwmac_reset(netdev_priv(ndev));
+		if (ret)
+			goto err_disable_regulator;
 	}
 
 	return 0;
@@ -784,16 +799,23 @@ static int get_ephy_nodes(struct stmmac_priv *priv)
 	/* Seek for internal PHY */
 	for_each_child_of_node_scoped(mdio_internal, iphynode) {
 		gmac->ephy_clk = of_clk_get(iphynode, 0);
-		if (IS_ERR(gmac->ephy_clk))
-			continue;
+		if (IS_ERR(gmac->ephy_clk)) {
+			ret = PTR_ERR(gmac->ephy_clk);
+			if (ret == -EPROBE_DEFER) {
+				of_node_put(mdio_internal);
+				return ret;
+			}
+			gmac->ephy_clk = NULL;
+		}
 		gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL);
 		if (IS_ERR(gmac->rst_ephy)) {
 			ret = PTR_ERR(gmac->rst_ephy);
 			if (ret == -EPROBE_DEFER) {
+				clk_put(gmac->ephy_clk);
 				of_node_put(mdio_internal);
 				return ret;
 			}
-			continue;
+			gmac->rst_ephy = NULL;
 		}
 		dev_info(priv->device, "Found internal PHY node\n");
 		of_node_put(mdio_internal);
@@ -871,7 +893,9 @@ static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
 		switch (desired_child) {
 		case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:
 			dev_info(priv->device, "Switch mux to internal PHY");
-			val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;
+			val = (reg & ~H3_EPHY_MUX_MASK);
+			if (gmac->variant != &emac_variant_h616_internal)
+				val |= H3_EPHY_SELECT;
 			gmac->use_internal_phy = true;
 			break;
 		case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID:
@@ -892,10 +916,13 @@ static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
 		} else {
 			sun8i_dwmac_unpower_internal_phy(gmac);
 		}
-		/* After changing syscon value, the MAC need reset or it will
+		/* After changing syscon value, the MAC needs reset or it will
 		 * use the last value (and so the last PHY set).
+		 * For internal PHY, the MAC reset will timeout because the PHY
+		 * is not yet enabled/clocked. Delay the reset to dwmac_init.
 		 */
-		ret = sun8i_dwmac_reset(priv);
+		if (!gmac->use_internal_phy)
+			ret = sun8i_dwmac_reset(priv);
 	}
 	return ret;
 }
@@ -1000,9 +1027,13 @@ static int sun8i_dwmac_set_syscon(struct device *dev,
 
 static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)
 {
-	if (gmac->variant->soc_has_internal_phy)
-		regmap_field_write(gmac->regmap_field,
-				   (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT));
+	if (gmac->variant->soc_has_internal_phy) {
+		u32 val = H3_EPHY_SHUTDOWN;
+
+		if (gmac->variant != &emac_variant_h616_internal)
+			val |= H3_EPHY_SELECT;
+		regmap_field_write(gmac->regmap_field, val);
+	}
 }
 
 static void sun8i_dwmac_exit(struct device *dev, void *priv)
@@ -1111,6 +1142,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
 	struct stmmac_priv *priv;
 	struct net_device *ndev;
 	struct regmap *regmap;
+	u32 syscon_idx = 0;
 	int ret;
 
 	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
@@ -1163,8 +1195,15 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1,
+					 &syscon_idx);
 	gmac->regmap_field = devm_regmap_field_alloc(dev, regmap,
-						     *gmac->variant->syscon_field);
+						     (const struct reg_field) {
+							.reg = gmac->variant->syscon_field->reg +
+							       syscon_idx * sizeof(u32),
+							.lsb = gmac->variant->syscon_field->lsb,
+							.msb = gmac->variant->syscon_field->msb,
+						     });
 	if (IS_ERR(gmac->regmap_field)) {
 		ret = PTR_ERR(gmac->regmap_field);
 		dev_err(dev, "Unable to map syscon register: %d\n", ret);
@@ -1278,6 +1317,12 @@ static const struct of_device_id sun8i_dwmac_match[] = {
 		.data = &emac_variant_a64 },
 	{ .compatible = "allwinner,sun50i-h6-emac",
 		.data = &emac_variant_h6 },
+	{ .compatible = "allwinner,sun50i-h616-emac",
+		.data = &emac_variant_h6 },
+	{ .compatible = "allwinner,sun50i-h616-emac1",
+		.data = &emac_variant_h6 },
+	{ .compatible = "allwinner,sun50i-h616-internal-emac",
+		.data = &emac_variant_h616_internal },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
-- 
2.53.0

Re: [PATCH net-next 4/4] net: stmmac: dwmac-sun8i: Add Allwinner H616 EMAC clock index and internal PHY support

[Maxime Chevallier]

Hi,

On 9/16/26 06:41, Alastair D'Silva wrote:
> Support EMAC1 and the internal Fast Ethernet PHY (AC300) on Allwinner
> H616 and H618 SoCs:
> - Allow reading a register index from the syscon property to offset the
>   regmap field for EMAC1's dedicated clock control register.
> - Add emac_variant_h616_internal with support for internal PHY, MII,
>   RMII, and RGMII modes.
> - Delay the MAC software reset until sun8i_dwmac_init() when using the
>   internal PHY, ensuring the PHY has powered on and begun generating
>   the receive clock before the MAC attempts to reset.
> - Skip setting H3_EPHY_SELECT for H616 internal EMAC, which does not
>   use the H3-style EPHY select bit.
> - Handle -EPROBE_DEFER cleanly during clock and reset control acquisition
>   in get_ephy_nodes().
> 
> Assisted-by: LLM
> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
> ---

Even if this is a duplicate some of the work done by James Hilliard, this
raises interesting points.

> Notes:
>     Tested on Mellow Fly-C5 (Allwinner H618) under Armbian, verifying stable
>     EMAC1 probe, deferred soft reset with the internal AC300 EPHY, and 100M full
>     duplex operation under load.
> 
>  .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 65 ++++++++++++++++---
>  1 file changed, 55 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> index 48c52eb96233..1728893589a6 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> @@ -130,6 +130,16 @@ static const struct emac_variant emac_variant_a64 = {
>  	.tx_delay_max = 7,
>  };
>  
> +static const struct emac_variant emac_variant_h616_internal = {
> +	.syscon_field = &sun8i_syscon_reg_field,
> +	.soc_has_internal_phy = true,
> +	.support_mii = true,
> +	.support_rmii = true,
> +	.support_rgmii = true,
> +	.rx_delay_max = 31,
> +	.tx_delay_max = 7,
> +};
James's series [1] says this SoC only supports RMII (yet includes RGMII timing
control), and here for seemingly the same device, there's MII and RGMII
support listed.

[1] : https://lore.kernel.org/r/20260915-submit-h616-emac1-v1-v1-0-195de0bb1f8a@gmail.com

Maybe you can coordinate with one another, can we connect that SoC to a non-internal PHY ?
If so, can we use MII, RMII and RGMII ? or is it just RMII ?

Maxime

Re: [PATCH net-next 4/4] net: stmmac: dwmac-sun8i: Add Allwinner H616 EMAC clock index and internal PHY support

[James Hilliard]

On Wed, Sep 16, 2026 at 12:25 AM Maxime Chevallier
<maxime.chevallier@bootlin.com> wrote:
>
> Hi,
>
> On 9/16/26 06:41, Alastair D'Silva wrote:
> > Support EMAC1 and the internal Fast Ethernet PHY (AC300) on Allwinner
> > H616 and H618 SoCs:
> > - Allow reading a register index from the syscon property to offset the
> >   regmap field for EMAC1's dedicated clock control register.
> > - Add emac_variant_h616_internal with support for internal PHY, MII,
> >   RMII, and RGMII modes.
> > - Delay the MAC software reset until sun8i_dwmac_init() when using the
> >   internal PHY, ensuring the PHY has powered on and begun generating
> >   the receive clock before the MAC attempts to reset.
> > - Skip setting H3_EPHY_SELECT for H616 internal EMAC, which does not
> >   use the H3-style EPHY select bit.
> > - Handle -EPROBE_DEFER cleanly during clock and reset control acquisition
> >   in get_ephy_nodes().
> >
> > Assisted-by: LLM
> > Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
> > ---
>
> Even if this is a duplicate some of the work done by James Hilliard, this
> raises interesting points.
>
> > Notes:
> >     Tested on Mellow Fly-C5 (Allwinner H618) under Armbian, verifying stable
> >     EMAC1 probe, deferred soft reset with the internal AC300 EPHY, and 100M full
> >     duplex operation under load.
> >
> >  .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 65 ++++++++++++++++---
> >  1 file changed, 55 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> > index 48c52eb96233..1728893589a6 100644
> > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> > @@ -130,6 +130,16 @@ static const struct emac_variant emac_variant_a64 = {
> >       .tx_delay_max = 7,
> >  };
> >
> > +static const struct emac_variant emac_variant_h616_internal = {
> > +     .syscon_field = &sun8i_syscon_reg_field,
> > +     .soc_has_internal_phy = true,
> > +     .support_mii = true,
> > +     .support_rmii = true,
> > +     .support_rgmii = true,
> > +     .rx_delay_max = 31,
> > +     .tx_delay_max = 7,
> > +};
> James's series [1] says this SoC only supports RMII (yet includes RGMII timing
> control), and here for seemingly the same device, there's MII and RGMII
> support listed.
>
> [1] : https://lore.kernel.org/r/20260915-submit-h616-emac1-v1-v1-0-195de0bb1f8a@gmail.com
>
> Maybe you can coordinate with one another, can we connect that SoC to a non-internal PHY ?

The SoC, yes, on emac0 for H616, but not for emac1.

> If so, can we use MII, RMII and RGMII ? or is it just RMII ?

Looks like it's just RMII.

>
> Maxime

Re: [PATCH net-next 4/4] net: stmmac: dwmac-sun8i: Add Allwinner H616 EMAC clock index and internal PHY support

[Alastair D'Silva]

On Wed, 2026-09-16 at 08:24 +0200, Maxime Chevallier wrote:
> Hi,
> 
> > 
<snip>

> >  .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 65
> > ++++++++++++++++---
> >  1 file changed, 55 insertions(+), 10 deletions(-)
> > 
> > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> > b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> > index 48c52eb96233..1728893589a6 100644
> > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> > @@ -130,6 +130,16 @@ static const struct emac_variant
> > emac_variant_a64 = {
> >   .tx_delay_max = 7,
> >  };
> >  
> > +static const struct emac_variant emac_variant_h616_internal = {
> > + .syscon_field = &sun8i_syscon_reg_field,
> > + .soc_has_internal_phy = true,
> > + .support_mii = true,
> > + .support_rmii = true,
> > + .support_rgmii = true,
> > + .rx_delay_max = 31,
> > + .tx_delay_max = 7,
> > +};
> James's series [1] says this SoC only supports RMII (yet includes
> RGMII timing
> control), and here for seemingly the same device, there's MII and
> RGMII
> support listed.
> 
> [1] : https://lore.kernel.org/r/20260915-submit-h616-emac1-v1-v1-0-
> 195de0bb1f8a@gmail.com
> 
> Maybe you can coordinate with one another, can we connect that SoC to
> a non-internal PHY ?
> If so, can we use MII, RMII and RGMII ? or is it just RMII ?
> 
> Maxime

I just double checked, MII & RGMII are bogus.

Only EMAC0 can be connected to an external PHY.

-- 
Alastair D'Silva

Re: [PATCH net-next 4/4] net: stmmac: dwmac-sun8i: Add Allwinner H616 EMAC clock index and internal PHY support

[Andre Przywara]

Hi,

On 9/16/26 08:24, Maxime Chevallier wrote:
> Hi,
> 
> On 9/16/26 06:41, Alastair D'Silva wrote:
>> Support EMAC1 and the internal Fast Ethernet PHY (AC300) on Allwinner
>> H616 and H618 SoCs:
>> - Allow reading a register index from the syscon property to offset the
>>    regmap field for EMAC1's dedicated clock control register.
>> - Add emac_variant_h616_internal with support for internal PHY, MII,
>>    RMII, and RGMII modes.
>> - Delay the MAC software reset until sun8i_dwmac_init() when using the
>>    internal PHY, ensuring the PHY has powered on and begun generating
>>    the receive clock before the MAC attempts to reset.
>> - Skip setting H3_EPHY_SELECT for H616 internal EMAC, which does not
>>    use the H3-style EPHY select bit.
>> - Handle -EPROBE_DEFER cleanly during clock and reset control acquisition
>>    in get_ephy_nodes().
>>
>> Assisted-by: LLM
>> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
>> ---
> 
> Even if this is a duplicate some of the work done by James Hilliard, this
> raises interesting points.

I think the point is that this patch is just wrong, in many parts ;-)
I think much of the code stems from the original Allwinner BSP code, 
which is just, say, misinformed in many respects. The use of compatible 
strings, and shoehorning the PHY clock into the MAC code are just 
examples. More below.

>> Notes:
>>      Tested on Mellow Fly-C5 (Allwinner H618) under Armbian, verifying stable
>>      EMAC1 probe, deferred soft reset with the internal AC300 EPHY, and 100M full
>>      duplex operation under load.
>>
>>   .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 65 ++++++++++++++++---
>>   1 file changed, 55 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
>> index 48c52eb96233..1728893589a6 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
>> @@ -130,6 +130,16 @@ static const struct emac_variant emac_variant_a64 = {
>>   	.tx_delay_max = 7,
>>   };
>>   
>> +static const struct emac_variant emac_variant_h616_internal = {
>> +	.syscon_field = &sun8i_syscon_reg_field,
>> +	.soc_has_internal_phy = true,

For instance this cannot be true. internal_phy refers to the H3 
generation, which works quite differently. We had this issue already 
with the H6, and there is a comment there mentioning this.

And this becomes obvious in other parts of the code, where this patch 
reverts the has_internal_phy tests, because they don't apply here.

>> +	.support_mii = true,
>> +	.support_rmii = true,
>> +	.support_rgmii = true,


>> +	.rx_delay_max = 31,
>> +	.tx_delay_max = 7,
>> +};
> James's series [1] says this SoC only supports RMII (yet includes RGMII timing
> control), and here for seemingly the same device, there's MII and RGMII
> support listed.
> 
> [1] : https://lore.kernel.org/r/20260915-submit-h616-emac1-v1-v1-0-195de0bb1f8a@gmail.com
> 
> Maybe you can coordinate with one another, can we connect that SoC to a non-internal PHY ?
> If so, can we use MII, RMII and RGMII ? or is it just RMII ?

This MAC is *only* connected to the AC200/AC300 PHY, which is a separate 
die, but co-packaged into the SoC. So that's set in stone. And while the 
MAC IP might support more MII modes (because it's maybe the same IP as 
the primary MAC? We don't know), it is irrelevant here, since only RMII 
is usable.

Cheers,
Andre

> 
> Maxime

Re: [PATCH net-next 0/4] net: Add Allwinner H616/H618 EMAC1 and AC300 EPHY support

[Chen-Yu Tsai]

On Wed, Sep 16, 2026 at 12:41 PM Alastair D'Silva <alastair@d-silva.org> wrote:
>
> This series adds support for the secondary Ethernet MAC controller (EMAC1)
> and the co-packaged AC300 Fast Ethernet Physical Layer (EPHY) found on
> Allwinner H616 and H618 SoCs.
>
> The Allwinner H616/H618 SoCs feature two EMAC instances: EMAC0 (typically
> used with an external RGMII Gigabit PHY) and EMAC1 (Fast Ethernet,
> connected internally to the co-packaged AC300 EPHY). EMAC1 uses a
> dedicated clock control register in the syscon register space, which is
> accessed via an offset index in the DT syscon property.
>
> The AC300 is an integrated 10/100M (100BASE-TX / 10BASE-T) Fast Ethernet
> PHY communicating over MDIO at address 16 + phy_addr. It requires
> retrieving factory bandgap calibration data from the SID nvmem controller,
> managing internal power rails and clocks, and optimizing transceiver signal
> parameters.

There is already a series from James covering the same thing. Please check
the mailing list and possibly our wiki (linux-sunxi.org) to avoid duplicate
work and subjecting the maintainers to the same discussions again.


ChenYu

> To ensure reliable link establishment and MAC software reset with the
> internal PHY, dwmac-sun8i is updated to defer MAC software reset until
> sun8i_dwmac_init() after the internal PHY has powered on and begun
> clock generation.
>
> The series is structured as follows:
> - Patch 1: DT binding for Allwinner AC300 EPHY.
> - Patch 2: PHY driver for Allwinner AC300 EPHY.
> - Patch 3: DT binding update for Allwinner H616 EMAC1 and syscon index.
> - Patch 4: dwmac-sun8i driver support for H616 EMAC1 clock index and
>            internal PHY deferred reset.
>
> Testing:
> - Tested on physical Mellow Fly-C5 hardware (Allwinner H618) running
>   Armbian with sustained 100Mbps full-duplex network traffic (DHCP,
>   iperf3, NFS rootfs).
> - Device tree bindings validated with dt_binding_check.
> - Separate SoC and board DTS additions will be submitted via the
>   linux-sunxi tree.
>
> Alastair D'Silva (4):
>   dt-bindings: net: phy: Add Allwinner AC300 EPHY binding
>   net: phy: Add Allwinner AC300 EPHY driver
>   dt-bindings: net: allwinner,sun8i-a83t-emac: Add Allwinner H616 EMAC1
>     and syscon index
>   net: stmmac: dwmac-sun8i: Add Allwinner H616 EMAC clock index and
>     internal PHY support
>
>  .../net/allwinner,sun50i-h618-ac300-ephy.yaml |  79 +++++
>  .../net/allwinner,sun8i-a83t-emac.yaml        |  14 +-
>  .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c |  65 +++-
>  drivers/net/phy/Kconfig                       |   9 +
>  drivers/net/phy/Makefile                      |   1 +
>  drivers/net/phy/ac300-phy.c                   | 331 ++++++++++++++++++
>  6 files changed, 486 insertions(+), 13 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun50i-h618-ac300-ephy.yaml
>  create mode 100644 drivers/net/phy/ac300-phy.c
>
> --
> 2.53.0
>

Re: [PATCH net-next 0/4] net: Add Allwinner H616/H618 EMAC1 and AC300 EPHY support

[James Hilliard]

On Tue, Sep 15, 2026 at 10:56 PM Chen-Yu Tsai <wens@kernel.org> wrote:
>
> On Wed, Sep 16, 2026 at 12:41 PM Alastair D'Silva <alastair@d-silva.org> wrote:
> >
> > This series adds support for the secondary Ethernet MAC controller (EMAC1)
> > and the co-packaged AC300 Fast Ethernet Physical Layer (EPHY) found on
> > Allwinner H616 and H618 SoCs.
> >
> > The Allwinner H616/H618 SoCs feature two EMAC instances: EMAC0 (typically
> > used with an external RGMII Gigabit PHY) and EMAC1 (Fast Ethernet,
> > connected internally to the co-packaged AC300 EPHY). EMAC1 uses a
> > dedicated clock control register in the syscon register space, which is
> > accessed via an offset index in the DT syscon property.
> >
> > The AC300 is an integrated 10/100M (100BASE-TX / 10BASE-T) Fast Ethernet
> > PHY communicating over MDIO at address 16 + phy_addr. It requires
> > retrieving factory bandgap calibration data from the SID nvmem controller,
> > managing internal power rails and clocks, and optimizing transceiver signal
> > parameters.
>
> There is already a series from James covering the same thing. Please check
> the mailing list and possibly our wiki (linux-sunxi.org) to avoid duplicate
> work and subjecting the maintainers to the same discussions again.

See:
https://git.kernel.org/netdev/net-next/c/783f6f1fdcd5
https://git.kernel.org/netdev/net-next/c/6cc2fbceb49b
https://lore.kernel.org/all/20260915-submit-h616-emac1-v1-v2-2-322b32e40eb9@gmail.com/

>
>
> ChenYu
>
> > To ensure reliable link establishment and MAC software reset with the
> > internal PHY, dwmac-sun8i is updated to defer MAC software reset until
> > sun8i_dwmac_init() after the internal PHY has powered on and begun
> > clock generation.
> >
> > The series is structured as follows:
> > - Patch 1: DT binding for Allwinner AC300 EPHY.
> > - Patch 2: PHY driver for Allwinner AC300 EPHY.
> > - Patch 3: DT binding update for Allwinner H616 EMAC1 and syscon index.
> > - Patch 4: dwmac-sun8i driver support for H616 EMAC1 clock index and
> >            internal PHY deferred reset.
> >
> > Testing:
> > - Tested on physical Mellow Fly-C5 hardware (Allwinner H618) running
> >   Armbian with sustained 100Mbps full-duplex network traffic (DHCP,
> >   iperf3, NFS rootfs).
> > - Device tree bindings validated with dt_binding_check.
> > - Separate SoC and board DTS additions will be submitted via the
> >   linux-sunxi tree.
> >
> > Alastair D'Silva (4):
> >   dt-bindings: net: phy: Add Allwinner AC300 EPHY binding
> >   net: phy: Add Allwinner AC300 EPHY driver
> >   dt-bindings: net: allwinner,sun8i-a83t-emac: Add Allwinner H616 EMAC1
> >     and syscon index
> >   net: stmmac: dwmac-sun8i: Add Allwinner H616 EMAC clock index and
> >     internal PHY support
> >
> >  .../net/allwinner,sun50i-h618-ac300-ephy.yaml |  79 +++++
> >  .../net/allwinner,sun8i-a83t-emac.yaml        |  14 +-
> >  .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c |  65 +++-
> >  drivers/net/phy/Kconfig                       |   9 +
> >  drivers/net/phy/Makefile                      |   1 +
> >  drivers/net/phy/ac300-phy.c                   | 331 ++++++++++++++++++
> >  6 files changed, 486 insertions(+), 13 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun50i-h618-ac300-ephy.yaml
> >  create mode 100644 drivers/net/phy/ac300-phy.c
> >
> > --
> > 2.53.0
> >

Re: [PATCH net-next 0/4] net: Add Allwinner H616/H618 EMAC1 and AC300 EPHY support

[Alastair D'Silva]

On Tue, 2026-09-15 at 23:12 -0600, James Hilliard wrote:
> On Tue, Sep 15, 2026 at 10:56 PM Chen-Yu Tsai <wens@kernel.org>
> wrote:
> > 
<snip>
> > There is already a series from James covering the same thing.
> > Please check
> > the mailing list and possibly our wiki (linux-sunxi.org) to avoid
> > duplicate
> > work and subjecting the maintainers to the same discussions again.
> 
> See:
> https://git.kernel.org/netdev/net-next/c/783f6f1fdcd5
> https://git.kernel.org/netdev/net-next/c/6cc2fbceb49b
> https://lore.kernel.org/all/20260915-submit-h616-emac1-v1-v2-2-
> 322b32e40eb9@gmail.com/
> > > 

Thanks, I'll withdraw this series.


There is one subtle timing issue worth highlighting from our Armbian
testing on the Mellow Fly-C5 (H618):

In James's dwmac patch, setting soc_has_internal_phy = false causes
sun8i_dwmac_probe() to fall through to sun8i_dwmac_reset(priv). The
Synopsys EMAC DMA soft reset (EMAC_BASIC_CTL1 bit 0) requires a running
RMII clock from the PHY to clear.

While this reset succeeds when the PHY driver is built-in and probes
synchronously, if CONFIG_XPOWERS_ACX00_PHY is built as a module (=m)
or if the PHY probe defers (-EPROBE_DEFER on regulator/clock/nvmem),
the PHY is unpowered and not clocking when sun8i_dwmac_probe() runs.

This causes sun8i_dwmac_reset() to time out after 100ms ("EMAC reset
timeout"), failing MAC driver probe. In our testing, deferring the MAC
reset until sun8i_dwmac_init() (which runs upon ndo_open after phylink
has attached and the PHY is active) avoided this probe failure.

Cheers,

-- 
Alastair D'Silva

Re: [PATCH net-next 0/4] net: Add Allwinner H616/H618 EMAC1 and AC300 EPHY support

[Maxime Chevallier]

Hi,
On 9/16/26 08:49, Alastair D'Silva wrote:

> There is one subtle timing issue worth highlighting from our Armbian
> testing on the Mellow Fly-C5 (H618):
> 
> In James's dwmac patch, setting soc_has_internal_phy = false causes
> sun8i_dwmac_probe() to fall through to sun8i_dwmac_reset(priv). The
> Synopsys EMAC DMA soft reset (EMAC_BASIC_CTL1 bit 0) requires a running
> RMII clock from the PHY to clear.
> 
> While this reset succeeds when the PHY driver is built-in and probes
> synchronously, if CONFIG_XPOWERS_ACX00_PHY is built as a module (=m)
> or if the PHY probe defers (-EPROBE_DEFER on regulator/clock/nvmem),
> the PHY is unpowered and not clocking when sun8i_dwmac_probe() runs.
> 
> This causes sun8i_dwmac_reset() to time out after 100ms ("EMAC reset
> timeout"), failing MAC driver probe. In our testing, deferring the MAC
> reset until sun8i_dwmac_init() (which runs upon ndo_open after phylink
> has attached and the PHY is active) avoided this probe failure.

I'm OK with going with James' version, however this seems like a valid
point that needs to be figured out.

James, can you add Alastair in CC of your next iterations, and Alastair
it would be great if you could give James's patches a test when he
submits them :)

There's more stuff in the dwmac part for Alastair's version, some
-EPROBEFER handling for clocks, the reset thing as well as the MUX
part, for which use-cases is all of that required ?

If that's something that needs to land with proper EMAC1 support, maybe
this could be split out from Alastair's work (in individual patches
please), and integrated in James's series ?

Maxime

Re: [PATCH net-next 0/4] net: Add Allwinner H616/H618 EMAC1 and AC300 EPHY support

[Alastair D'Silva]

On Wed, 2026-09-16 at 09:06 +0200, Maxime Chevallier wrote:
> Hi,
> On 9/16/26 08:49, Alastair D'Silva wrote:
> 
> > There is one subtle timing issue worth highlighting from our
> > Armbian
> > testing on the Mellow Fly-C5 (H618):
> > 
> > In James's dwmac patch, setting soc_has_internal_phy = false causes
> > sun8i_dwmac_probe() to fall through to sun8i_dwmac_reset(priv). The
> > Synopsys EMAC DMA soft reset (EMAC_BASIC_CTL1 bit 0) requires a
> > running
> > RMII clock from the PHY to clear.
> > 
> > While this reset succeeds when the PHY driver is built-in and
> > probes
> > synchronously, if CONFIG_XPOWERS_ACX00_PHY is built as a module
> > (=m)
> > or if the PHY probe defers (-EPROBE_DEFER on
> > regulator/clock/nvmem),
> > the PHY is unpowered and not clocking when sun8i_dwmac_probe()
> > runs.
> > 
> > This causes sun8i_dwmac_reset() to time out after 100ms ("EMAC
> > reset
> > timeout"), failing MAC driver probe. In our testing, deferring the
> > MAC
> > reset until sun8i_dwmac_init() (which runs upon ndo_open after
> > phylink
> > has attached and the PHY is active) avoided this probe failure.
> 
> I'm OK with going with James' version, however this seems like a
> valid
> point that needs to be figured out.
> 
> James, can you add Alastair in CC of your next iterations, and
> Alastair
> it would be great if you could give James's patches a test when he
> submits them :)
> 
> There's more stuff in the dwmac part for Alastair's version, some
> -EPROBEFER handling for clocks, the reset thing as well as the MUX
> part, for which use-cases is all of that required ?
> 
> If that's something that needs to land with proper EMAC1 support,
> maybe
> this could be split out from Alastair's work (in individual patches
> please), and integrated in James's series ?
> 
> Maxime

Thanks Maxime. Here is the breakdown of why those pieces were in my
earlier patch and how they relate to James's series:

1. MDIO MUX & H3_EPHY_SELECT:
   These are NOT needed for James's series.
   My initial test tree was using the legacy
   "allwinner,sun8i-h3-mdio-mux" node inherited from older
   vendor/Armbian DTs. That mux driver attempts to toggle
   H3_EPHY_SELECT (bit 0 of SYSCON), which on H616 register 0x34 is
   actually SYSCON_EPIT (interface type), so I had to mask it out.
   With James's series, there is no fake mdio-mux node (direct MDIO bus
   with the ethernet-phy-package), which is much cleaner and completely
   bypasses all H3 mux code.

2. -EPROBE_DEFER handling in get_ephy_nodes():
   Also NOT needed for H616 EMAC1.
   get_ephy_nodes() is only called when soc_has_internal_phy = true.
   In James's series, all PHY clocks, regulators, and NVMEM cells are
   managed inside the PHY package driver
   (drivers/net/phy/xpowers/ac300.c), where -EPROBE_DEFER is already
   handled cleanly via dev_err_probe().
   (The get_ephy_nodes() fix is only relevant as an independent 
   cleanup for legacy H3/V3s platforms).

3. MAC Soft Reset timing (The one piece that IS needed):
   This is the one issue that affects James's series.
   Because emac_variant_h616_emac1 sets soc_has_internal_phy = false,
   sun8i_dwmac_probe() falls through to line 1221:
       ret = sun8i_dwmac_reset(priv);

   The Allwinner EMAC DMA soft reset (EMAC_BASIC_CTL1 bit 0) requires
   the RMII clock from the PHY to toggle in order to complete.
   If CONFIG_XPOWERS_ACX00_PHY is built as a module (=m), or if any of
   the AC300 package resources defer probe, the PHY is unpowered and
   not clocking during sun8i_dwmac_probe(). sun8i_dwmac_reset() will
   time out after 100ms ("EMAC reset timeout"), aborting the MAC probe
   completely.
   For EMAC1, skipping sun8i_dwmac_reset() during probe and letting it
   run in sun8i_dwmac_init() (which runs upon ndo_open after phylink
   has connected and the PHY is clocked) avoids this probe failure.

James, I'm happy to test your next revision on physical Mellow Fly-C5
(H618) hardware as both a builtin driver, and a module.

-- 
Alastair D'Silva
0493 18 5566