Re: [PATCH v11 1/9] dt-bindings: media: qcom,glymur-iris: Add glymur video codec

[Vishnu Reddy <busanna.reddy@oss.qualcomm.com>]

On 9/22/2026 6:29 PM, Dmitry Baryshkov wrote:
> On Thu, Sep 17, 2026 at 10:30:20AM +0530, Vishnu Reddy wrote:
>> Add device tree binding for the Qualcomm Glymur Iris video codec. Glymur
>> is a new generation of video IP that introduces a dual-core architecture.
>> The second core brings its own power domain, clocks, and reset lines,
>> requiring additional power domains and clocks in the power sequence. The
>> current maxItems constraints for clocks, power-domains and non-pixel
>> iommus in the common venus schema were sized for platforms available at
>> the time of authoring. The glymur platform introduces a dual core
>> architecture that requires more clocks and power domains, exceeding these
>> limits. Raise maxItems for clocks, clock-names, power-domains,
>> power-domain-names and non-pixel iommus to accommodate glymur platform.
>> The glymur platform specific schema have fixed constraints for these
>> properties, so the common schema only acts as an upper bound. Since the
>> common schema now only acts as an upper bound, add explicit maxItems
>> overrides for the non-pixel iommus in the qcom,sm8550-iris and
>> qcom,sm8750-iris schemas to keep the fixed constraints as before.
>>
>> Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
>> ---
>>  .../bindings/media/qcom,glymur-iris.yaml           | 218 +++++++++++++++++++++
>>  .../bindings/media/qcom,sm8550-iris.yaml           |   6 +
>>  .../bindings/media/qcom,sm8750-iris.yaml           |   6 +
>>  .../bindings/media/qcom,venus-common.yaml          |  11 +-
>>  4 files changed, 236 insertions(+), 5 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml
>> new file mode 100644
>> index 000000000000..de4792f3b658
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml
>> @@ -0,0 +1,218 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/media/qcom,glymur-iris.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Glymur SoC Iris video encoder and decoder
>> +
>> +maintainers:
>> +  - Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
>> +
>> +description:
>> +  The Iris video processing unit on Qualcomm Glymur SoC is a video encode and
>> +  decode accelerator.
>> +
>> +properties:
>> +  compatible:
>> +    const: qcom,glymur-iris
>> +
>> +  clocks:
>> +    maxItems: 9
>> +
>> +  clock-names:
>> +    items:
>> +      - const: core_iface
>> +      - const: core
>> +      - const: vcodec0_core
>> +      - const: vcodec0_iface
>> +      - const: core_freerun
>> +      - const: vcodec0_core_freerun
>> +      - const: vcodec1_iface
>> +      - const: vcodec1_core
> Nit: is there any logic in the order of the clocks? Why vcodec0_core
> comes before vcodec0_iface, but vcodec1_core comes after vcodec1_iface?

I followed the clock ordering from the SM8750 binding for the existing entries.
For the additional glymur clocks, I appended them at the end and kept the new
pair in the same interface-before-core style as the inherited clock list. That
is why vcodec1_iface appears before vcodec1_core. There was no specific
functional dependency intended by this ordering. Let me know if you have any
preference on reordering.

>> +      - const: vcodec1_core_freerun
>> +
>> +  dma-coherent: true
>> +
>> +  interconnects:
>> +    maxItems: 2
>