From: JeeHeng Sia <jeeheng.sia@starfivetech.com>
To: Alexandre Ghiti <alex@ghiti.fr>,
"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
"palmer@dabbelt.com" <palmer@dabbelt.com>,
"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>
Cc: "linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Leyfoon Tan <leyfoon.tan@starfivetech.com>,
Mason Huo <mason.huo@starfivetech.com>
Subject: RE: [PATCH v4 2/4] RISC-V: Factor out common code of __cpu_resume_enter()
Date: Mon, 27 Feb 2023 02:21:56 +0000 [thread overview]
Message-ID: <3415321bb1a1451ca7cca68c9eae9511@EXMBX066.cuchost.com> (raw)
In-Reply-To: <651d5f06-a22b-4cd9-1ec7-d198adf0a6f1@ghiti.fr>
> -----Original Message-----
> From: Alexandre Ghiti <alex@ghiti.fr>
> Sent: Friday, 24 February, 2023 6:19 PM
> To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu
> Cc: linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com>; Mason Huo
> <mason.huo@starfivetech.com>
> Subject: Re: [PATCH v4 2/4] RISC-V: Factor out common code of __cpu_resume_enter()
>
> Hi Sia,
>
> On 2/21/23 03:35, Sia Jee Heng wrote:
> > The cpu_resume() function is very similar for the suspend to disk and
> > suspend to ram cases. Factor out the common code into restore_csr macro
> > and restore_reg macro.
> >
> > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> > ---
> > arch/riscv/include/asm/assembler.h | 62 ++++++++++++++++++++++++++++++
> > arch/riscv/kernel/suspend_entry.S | 34 ++--------------
> > 2 files changed, 65 insertions(+), 31 deletions(-)
> > create mode 100644 arch/riscv/include/asm/assembler.h
> >
> > diff --git a/arch/riscv/include/asm/assembler.h b/arch/riscv/include/asm/assembler.h
> > new file mode 100644
> > index 000000000000..727a97735493
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/assembler.h
> > @@ -0,0 +1,62 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> > + *
> > + * Author: Jee Heng Sia <jeeheng.sia@starfivetech.com>
> > + */
> > +
> > +#ifndef __ASSEMBLY__
> > +#error "Only include this from assembly code"
> > +#endif
> > +
> > +#ifndef __ASM_ASSEMBLER_H
> > +#define __ASM_ASSEMBLER_H
> > +
> > +#include <asm/asm.h>
> > +#include <asm/asm-offsets.h>
> > +#include <asm/csr.h>
> > +
> > +/*
> > + * restore_csr - restore hart's CSR value
> > + */
> > + .macro restore_csr
> > + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
> > + csrw CSR_EPC, t0
> > + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
> > + csrw CSR_STATUS, t0
> > + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
> > + csrw CSR_TVAL, t0
> > + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
> > + csrw CSR_CAUSE, t0
> > + .endm
> > +
> > +/*
> > + * restore_reg - Restore registers (except A0 and T0-T6)
> > + */
> > + .macro restore_reg
> > + REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
> > + REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
> > + REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
> > + REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
> > + REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
> > + REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
> > + REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
> > + REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
> > + REG_L a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
> > + REG_L a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
> > + REG_L a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
> > + REG_L a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
> > + REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
> > + REG_L s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
> > + REG_L s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
> > + REG_L s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
> > + REG_L s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
> > + REG_L s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
> > + REG_L s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
> > + REG_L s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
> > + REG_L s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
> > + REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
> > + REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
> > + .endm
> > +
> > +#endif /* __ASM_ASSEMBLER_H */
>
>
> You introduce assembler.h which in the future may contain other assembly
> functions not related to suspend: I'd rename those macros so that we
> know they are suspend related, something like
> suspend_restore_regs/suspend_restore_csrs.
Sure, these can be done.
>
> And instead of (SUSPEND_CONTEXT_REGS + PT_XXX) you could introduce
> SUSPEND_CONTEXT_REGS_PT_XXX in asm-offsets.c?
There are already PT_XXX defined in the asm-offset.c, we should not create another set of SUSPEND_CONTEXT_REGS_PT_XXX because we can just re-use the definition instead of duplicate another set of offset which are doing the same thing. So, I would rather stick with the current definition.
DEFINE(PT_SIZE, sizeof(struct pt_regs));
OFFSET(PT_EPC, pt_regs, epc);
OFFSET(PT_RA, pt_regs, ra);
OFFSET(PT_FP, pt_regs, s0);
OFFSET(PT_S0, pt_regs, s0);
OFFSET(PT_S1, pt_regs, s1);
OFFSET(PT_S2, pt_regs, s2);
>
>
> > diff --git a/arch/riscv/kernel/suspend_entry.S b/arch/riscv/kernel/suspend_entry.S
> > index aafcca58c19d..74a8fab8e0f6 100644
> > --- a/arch/riscv/kernel/suspend_entry.S
> > +++ b/arch/riscv/kernel/suspend_entry.S
> > @@ -7,6 +7,7 @@
> > #include <linux/linkage.h>
> > #include <asm/asm.h>
> > #include <asm/asm-offsets.h>
> > +#include <asm/assembler.h>
> > #include <asm/csr.h>
> > #include <asm/xip_fixup.h>
> >
> > @@ -83,39 +84,10 @@ ENTRY(__cpu_resume_enter)
> > add a0, a1, zero
> >
> > /* Restore CSRs */
> > - REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
> > - csrw CSR_EPC, t0
> > - REG_L t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
> > - csrw CSR_STATUS, t0
> > - REG_L t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
> > - csrw CSR_TVAL, t0
> > - REG_L t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
> > - csrw CSR_CAUSE, t0
> > + restore_csr
> >
> > /* Restore registers (except A0 and T0-T6) */
> > - REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
> > - REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
> > - REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
> > - REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
> > - REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
> > - REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
> > - REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
> > - REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
> > - REG_L a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
> > - REG_L a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
> > - REG_L a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
> > - REG_L a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
> > - REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
> > - REG_L s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
> > - REG_L s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
> > - REG_L s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
> > - REG_L s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
> > - REG_L s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
> > - REG_L s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
> > - REG_L s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
> > - REG_L s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
> > - REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
> > - REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
> > + restore_reg
> >
> > /* Return zero value */
> > add a0, zero, zero
next prev parent reply other threads:[~2023-02-27 2:32 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-21 2:35 [PATCH v4 0/4] RISC-V Hibernation Support Sia Jee Heng
2023-02-21 2:35 ` [PATCH v4 1/4] RISC-V: Change suspend_save_csrs and suspend_restore_csrs to public function Sia Jee Heng
2023-02-23 6:39 ` Andrew Jones
2023-02-24 1:33 ` JeeHeng Sia
2023-02-21 2:35 ` [PATCH v4 2/4] RISC-V: Factor out common code of __cpu_resume_enter() Sia Jee Heng
2023-02-23 6:51 ` Andrew Jones
2023-02-24 1:33 ` JeeHeng Sia
2023-02-24 10:19 ` Alexandre Ghiti
2023-02-27 2:21 ` JeeHeng Sia [this message]
2023-02-21 2:35 ` [PATCH v4 3/4] RISC-V: mm: Enable huge page support to kernel_page_present() function Sia Jee Heng
2023-02-23 6:57 ` Andrew Jones
2023-02-24 1:33 ` JeeHeng Sia
2023-02-24 10:21 ` Alexandre Ghiti
2023-02-21 2:35 ` [PATCH v4 4/4] RISC-V: Add arch functions to support hibernation/suspend-to-disk Sia Jee Heng
2023-02-23 18:07 ` Andrew Jones
2023-02-24 2:05 ` JeeHeng Sia
2023-02-24 9:00 ` Andrew Jones
2023-02-24 9:33 ` JeeHeng Sia
2023-02-24 9:55 ` Andrew Jones
2023-02-24 10:30 ` JeeHeng Sia
2023-02-24 12:07 ` Andrew Jones
2023-02-27 2:14 ` JeeHeng Sia
2023-02-27 7:59 ` Andrew Jones
2023-02-27 10:52 ` JeeHeng Sia
2023-02-27 11:44 ` Andrew Jones
2023-02-28 1:32 ` JeeHeng Sia
2023-02-28 5:04 ` Andrew Jones
2023-02-28 5:33 ` JeeHeng Sia
2023-02-28 7:18 ` Andrew Jones
2023-02-28 7:29 ` JeeHeng Sia
2023-02-28 7:37 ` Andrew Jones
2023-03-03 1:53 ` JeeHeng Sia
2023-03-03 8:09 ` Andrew Jones
2023-02-28 6:33 ` JeeHeng Sia
2023-02-28 7:29 ` Andrew Jones
2023-02-28 7:34 ` JeeHeng Sia
2023-02-24 2:12 ` JeeHeng Sia
2023-02-24 12:29 ` Alexandre Ghiti
2023-02-27 3:11 ` JeeHeng Sia
2023-02-27 20:31 ` Alexandre Ghiti
2023-02-28 1:20 ` JeeHeng Sia
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