* [PATCH v4 1/2] dt-bindings: arm: altera: add Agilex SoCDK multi-QSPI board
2026-10-12 7:48 [PATCH v4 0/2] arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board genevieve.chan
@ 2026-10-12 7:48 ` genevieve.chan
2026-10-12 7:48 ` [PATCH v4 2/2] arm64: dts: socfpga: agilex: add " genevieve.chan
2026-10-26 14:04 ` [PATCH v4 0/2] " Dinh Nguyen
2 siblings, 0 replies; 4+ messages in thread
From: genevieve.chan @ 2026-10-12 7:48 UTC (permalink / raw)
To: dinguyen, robh, krzk+dt, conor+dt; +Cc: devicetree, linux-kernel
From: Genevieve Chan <genevieve.chan@altera.com>
The Agilex SoCDK can be fitted with a multi-QSPI daughter card in
place of the default single-flash QSPI card. The multi-QSPI card
carries four Micron MT25QU02G flashes connected to the HPS QSPI
controller on chip selects 0-3.
The different flash population requires a separate board DTS, hence, add
a board compatible for it, following the existing SoCDK variants.
The board uses the Agilex SoC (marketed as Agilex 7 F-Series), so it
falls back to "intel,socfpga-agilex".
Signed-off-by: Genevieve Chan <genevieve.chan@altera.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes in v4:
- None.
Changes in v3:
- Add Conor's Acked-by.
Changes in v2:
- Rename compatible from intel,socfpga-agilex7f-socdk-multiqspi to
intel,socfpga-agilex-socdk-multiqspi.
- Describe the hardware difference in the commit message.
Documentation/devicetree/bindings/arm/altera.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
index 5fce1161210e..01f6323b9a6b 100644
--- a/Documentation/devicetree/bindings/arm/altera.yaml
+++ b/Documentation/devicetree/bindings/arm/altera.yaml
@@ -97,6 +97,7 @@ properties:
- intel,socfpga-agilex-n6000
- intel,socfpga-agilex-socdk
- intel,socfpga-agilex-socdk-emmc
+ - intel,socfpga-agilex-socdk-multiqspi
- const: intel,socfpga-agilex
- description: Agilex3 boards
--
2.43.7
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v4 2/2] arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board
2026-10-12 7:48 [PATCH v4 0/2] arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board genevieve.chan
2026-10-12 7:48 ` [PATCH v4 1/2] dt-bindings: arm: altera: add Agilex " genevieve.chan
@ 2026-10-12 7:48 ` genevieve.chan
2026-10-26 14:04 ` [PATCH v4 0/2] " Dinh Nguyen
2 siblings, 0 replies; 4+ messages in thread
From: genevieve.chan @ 2026-10-12 7:48 UTC (permalink / raw)
To: dinguyen, robh, krzk+dt, conor+dt; +Cc: devicetree, linux-kernel
From: Genevieve Chan <genevieve.chan@altera.com>
Add a device tree for the Agilex SoCDK fitted with the multi-QSPI
daughter board. The daughter board replaces the single QSPI flash of
the default SoCDK with four Micron MT25QU02G flashes on chip selects
0-3, which allows the system to use up to 1 GiB of QSPI storage.
The four flashes share SCLK and DQ[3:0], with only the chip selects
routed separately. The added load of four devices and the longer
routing on the daughter board lower the clock the bus can run
reliably, so the flashes are described at 25 MHz, the rate Altera's
multi-QSPI reference design for this board is validated at, rather
than the 100 MHz used on the SoCDK.
Each flash has one partition covering the whole device. The partition
on flash@0 keeps the "Boot and fpga data" label, which U-Boot's RSU
code looks up to locate the boot partition on chip select 0. The
partitions on flash@1-3 are numbered so that every label is unique.
The board is otherwise identical to the SoCDK and builds on
socfpga_agilex.dtsi.
Signed-off-by: Genevieve Chan <genevieve.chan@altera.com>
---
Changes in v4:
- Give the partitions on flash@1-3 unique labels so that they do not
share an MTD name with flash@0 (Dinh, Sashiko).
- Explain in the commit message why the flashes run at 25 MHz rather
than the 100 MHz used on the SoCDK (Dinh).
Changes in v3:
- Reword subject to avoid repeating "Agilex".
- Move the DTS to arch/arm64/boot/dts/altera/, following the move of
the SoCFPGA device trees in for-next.
Changes in v2:
- Rename file, compatible and model to drop the "agilex7f" prefix.
- Reword commit message to describe the hardware.
arch/arm64/boot/dts/altera/Makefile | 1 +
.../altera/socfpga_agilex_socdk_multiqspi.dts | 213 ++++++++++++++++++
2 files changed, 214 insertions(+)
create mode 100644 arch/arm64/boot/dts/altera/socfpga_agilex_socdk_multiqspi.dts
diff --git a/arch/arm64/boot/dts/altera/Makefile b/arch/arm64/boot/dts/altera/Makefile
index 8f41349103b8..d38fe88a1cc8 100644
--- a/arch/arm64/boot/dts/altera/Makefile
+++ b/arch/arm64/boot/dts/altera/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_emmc.dtb \
+ socfpga_agilex_socdk_multiqspi.dtb \
socfpga_agilex_socdk_nand.dtb \
socfpga_agilex3_socdk.dtb \
socfpga_agilex5_socdk.dtb \
diff --git a/arch/arm64/boot/dts/altera/socfpga_agilex_socdk_multiqspi.dts b/arch/arm64/boot/dts/altera/socfpga_agilex_socdk_multiqspi.dts
new file mode 100644
index 000000000000..9b49d12cba36
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/socfpga_agilex_socdk_multiqspi.dts
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026, Intel Corporation
+ */
+#include "socfpga_agilex.dtsi"
+
+/ {
+ model = "SoCFPGA Agilex SoCDK multi-QSPI daughter board";
+ compatible = "intel,socfpga-agilex-socdk-multiqspi", "intel,socfpga-agilex";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &gmac2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led0 {
+ label = "hps_led0";
+ gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ led1 {
+ label = "hps_led1";
+ gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ led2 {
+ label = "hps_led2";
+ gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0x80000000 0 0>;
+ };
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gmac0 {
+ status = "okay";
+ /* PHY delays are configured via skew properties */
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+
+ max-frame-size = <9000>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@4 {
+ reg = <4>;
+
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <900>; /* 0ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ };
+ };
+};
+
+&mmc {
+ status = "okay";
+ cap-sd-highspeed;
+ broken-cd;
+ bus-width = <4>;
+ clk-phase-sd-hs = <0>, <135>;
+};
+
+&osc1 {
+ clock-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ disable-over-current;
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+
+ flash@0 {
+ compatible = "micron,mt25qu02g", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+
+ m25p,fast-read;
+ cdns,read-delay = <2>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot0: partition@0 {
+ label = "Boot and fpga data";
+ reg = <0x0 0x10000000>;
+ };
+ };
+ };
+
+ flash@1 {
+ compatible = "micron,mt25qu02g", "jedec,spi-nor";
+ reg = <1>;
+ spi-max-frequency = <25000000>;
+
+ m25p,fast-read;
+ cdns,read-delay = <2>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot1: partition@0 {
+ label = "Boot and fpga data 1";
+ reg = <0x0 0x10000000>;
+ };
+ };
+ };
+
+ flash@2 {
+ compatible = "micron,mt25qu02g", "jedec,spi-nor";
+ reg = <2>;
+ spi-max-frequency = <25000000>;
+
+ m25p,fast-read;
+ cdns,read-delay = <2>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot2: partition@0 {
+ label = "Boot and fpga data 2";
+ reg = <0x0 0x10000000>;
+ };
+ };
+ };
+
+ flash@3 {
+ compatible = "micron,mt25qu02g", "jedec,spi-nor";
+ reg = <3>;
+ spi-max-frequency = <25000000>;
+
+ m25p,fast-read;
+ cdns,read-delay = <2>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot3: partition@0 {
+ label = "Boot and fpga data 3";
+ reg = <0x0 0x10000000>;
+ };
+ };
+ };
+};
--
2.43.7
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v4 0/2] arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board
2026-10-12 7:48 [PATCH v4 0/2] arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board genevieve.chan
2026-10-12 7:48 ` [PATCH v4 1/2] dt-bindings: arm: altera: add Agilex " genevieve.chan
2026-10-12 7:48 ` [PATCH v4 2/2] arm64: dts: socfpga: agilex: add " genevieve.chan
@ 2026-10-26 14:04 ` Dinh Nguyen
2 siblings, 0 replies; 4+ messages in thread
From: Dinh Nguyen @ 2026-10-26 14:04 UTC (permalink / raw)
To: genevieve.chan, robh, krzk+dt, conor+dt; +Cc: devicetree, linux-kernel
On 10/12/26 02:48, genevieve.chan@altera.com wrote:
> From: Genevieve Chan <genevieve.chan@altera.com>
>
> The Agilex SoCDK is populated with a single QSPI flash by default. A
> multi-QSPI daughter board can be fitted in its place. That board connects
> four Micron MT25QU02G devices (256 MiB each, 1 GiB total) to the HPS
> QSPI controller on chip selects 0-3. Each device carries one partition
> covering the whole flash, and is described in quad mode at 25 MHz, as
> the four devices share the clock and data lines.
>
> This is a board-level population difference, in the same way the
> existing SoCDK eMMC and NAND variants differ from the default SoCDK.
> The HPS is the Agilex SoC, later marketed as Agilex 7 F-Series. The
> programming model is unchanged, so the board falls back to
> "intel,socfpga-agilex" and does not add an F-Series SoC compatible.
> Agilex 7 M-Series is a different device and already has its own
> fallback.
>
> Patch 1 documents that compatible next to the other Agilex SoCDK
> boards. Patch 2 adds socfpga_agilex_socdk_multiqspi.dts. UART,
> Ethernet, USB, SDMMC, LEDs and the watchdog match the SoCDK; the QSPI
> node is the difference.
>
> Changes in v4:
> - Give the partitions on flash@1-3 unique labels so that they do not
> share an MTD name with flash@0 (Dinh, Sashiko). flash@0 keeps
> "Boot and fpga data", which U-Boot's RSU code looks up by name.
> - Explain in the patch 2 commit message why the flashes run at 25 MHz
> rather than the 100 MHz used on the SoCDK (Dinh).
>
> Changes in v3:
> - Rebase onto the socfpga for-next branch, which moved the SoCFPGA
> device trees to arch/arm64/boot/dts/altera/. The new DTS is added
> there.
> - Reword the subject of patch 2 to avoid repeating "Agilex" (Dinh).
> - Add Conor's Acked-by to patch 1.
>
> Changes in v2:
> - Rename the compatible, DTS filename and model, dropping "agilex7f".
> - State in the binding patch why the fallback is "intel,socfpga-agilex".
> - Describe the daughter card instead of restating the diff.
>
> Genevieve Chan (2):
> dt-bindings: arm: altera: add Agilex SoCDK multi-QSPI board
> arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board
>
> .../devicetree/bindings/arm/altera.yaml | 1 +
> arch/arm64/boot/dts/altera/Makefile | 1 +
> .../altera/socfpga_agilex_socdk_multiqspi.dts | 213 ++++++++++++++++++
> 3 files changed, 215 insertions(+)
> create mode 100644 arch/arm64/boot/dts/altera/socfpga_agilex_socdk_multiqspi.dts
>
Applied!
Thanks,
Dinh
^ permalink raw reply [flat|nested] 4+ messages in thread