* [PATCH V4 1/3] dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P
2024-11-12 7:58 [PATCH V4 0/3] Add EPSS L3 provider support on SA8775P SoC Raviteja Laggyshetty
@ 2024-11-12 7:58 ` Raviteja Laggyshetty
2024-11-12 13:50 ` Dmitry Baryshkov
2024-11-12 7:58 ` [PATCH V4 2/3] arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider Raviteja Laggyshetty
2024-11-12 7:58 ` [PATCH V4 3/3] interconnect: qcom: Add EPSS L3 support on SA8775P Raviteja Laggyshetty
2 siblings, 1 reply; 8+ messages in thread
From: Raviteja Laggyshetty @ 2024-11-12 7:58 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: Sibi Sankar, linux-arm-msm, linux-pm, devicetree, linux-kernel,
Odelu Kukatla, Mike Tipton
Add Epoch Subsystem (EPSS) L3 interconnect provider binding on
SA8775P SoCs.
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
---
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
index 21dae0b92819..94f7f283787a 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -33,6 +33,7 @@ properties:
- qcom,sm6375-cpucp-l3
- qcom,sm8250-epss-l3
- qcom,sm8350-epss-l3
+ - qcom,sa8775p-epss-l3
- const: qcom,epss-l3
reg:
--
2.39.2
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH V4 2/3] arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider
2024-11-12 7:58 [PATCH V4 0/3] Add EPSS L3 provider support on SA8775P SoC Raviteja Laggyshetty
2024-11-12 7:58 ` [PATCH V4 1/3] dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P Raviteja Laggyshetty
@ 2024-11-12 7:58 ` Raviteja Laggyshetty
2024-11-12 7:58 ` [PATCH V4 3/3] interconnect: qcom: Add EPSS L3 support on SA8775P Raviteja Laggyshetty
2 siblings, 0 replies; 8+ messages in thread
From: Raviteja Laggyshetty @ 2024-11-12 7:58 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: Sibi Sankar, linux-arm-msm, linux-pm, devicetree, linux-kernel,
Odelu Kukatla, Mike Tipton
Add Epoch Subsystem (EPSS) L3 interconnect provider node on SA8775P
SoCs.
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 9f315a51a7c1..e790d74de962 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/firmware/qcom,scm.h>
@@ -4282,6 +4283,15 @@ rpmhpd_opp_turbo_l1: opp-9 {
};
};
+ epss_l3_cl0: interconnect@18590000 {
+ compatible = "qcom,sa8775p-epss-l3",
+ "qcom,epss-l3";
+ reg = <0x0 0x18590000 0x0 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,sa8775p-cpufreq-epss",
"qcom,cpufreq-epss";
@@ -4295,6 +4305,15 @@ cpufreq_hw: cpufreq@18591000 {
#freq-domain-cells = <1>;
};
+ epss_l3_cl1: interconnect@18592000 {
+ compatible = "qcom,sa8775p-epss-l3",
+ "qcom,epss-l3";
+ reg = <0x0 0x18592000 0x0 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
remoteproc_gpdsp0: remoteproc@20c00000 {
compatible = "qcom,sa8775p-gpdsp0-pas";
reg = <0x0 0x20c00000 0x0 0x10000>;
--
2.39.2
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH V4 3/3] interconnect: qcom: Add EPSS L3 support on SA8775P
2024-11-12 7:58 [PATCH V4 0/3] Add EPSS L3 provider support on SA8775P SoC Raviteja Laggyshetty
2024-11-12 7:58 ` [PATCH V4 1/3] dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P Raviteja Laggyshetty
2024-11-12 7:58 ` [PATCH V4 2/3] arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider Raviteja Laggyshetty
@ 2024-11-12 7:58 ` Raviteja Laggyshetty
2 siblings, 0 replies; 8+ messages in thread
From: Raviteja Laggyshetty @ 2024-11-12 7:58 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: Sibi Sankar, linux-arm-msm, linux-pm, devicetree, linux-kernel,
Odelu Kukatla, Mike Tipton
Add Epoch Subsystem (EPSS) L3 interconnect provider on
SA8775P SoCs with multiple device support.
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
---
drivers/interconnect/qcom/osm-l3.c | 86 ++++++++++++++++++++++--------
1 file changed, 64 insertions(+), 22 deletions(-)
diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
index 6a656ed44d49..8393ef6d4740 100644
--- a/drivers/interconnect/qcom/osm-l3.c
+++ b/drivers/interconnect/qcom/osm-l3.c
@@ -1,16 +1,19 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/args.h>
#include <linux/bitfield.h>
#include <linux/clk.h>
+#include <linux/idr.h>
#include <linux/interconnect-provider.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
@@ -34,9 +37,14 @@
#define OSM_L3_MAX_LINKS 1
+#define OSM_L3_NODE_ID_START 10000
+#define OSM_NODE_NAME_SUFFIX_SIZE 10
+
#define to_osm_l3_provider(_provider) \
container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
+static DEFINE_IDA(osm_l3_id);
+
struct qcom_osm_l3_icc_provider {
void __iomem *base;
unsigned int max_state;
@@ -55,46 +63,40 @@ struct qcom_osm_l3_icc_provider {
*/
struct qcom_osm_l3_node {
const char *name;
- u16 links[OSM_L3_MAX_LINKS];
+ const char *links[OSM_L3_MAX_LINKS];
u16 id;
u16 num_links;
u16 buswidth;
};
struct qcom_osm_l3_desc {
- const struct qcom_osm_l3_node * const *nodes;
+ struct qcom_osm_l3_node * const *nodes;
size_t num_nodes;
unsigned int lut_row_size;
unsigned int reg_freq_lut;
unsigned int reg_perf_state;
};
-enum {
- OSM_L3_MASTER_NODE = 10000,
- OSM_L3_SLAVE_NODE,
-};
-
-#define DEFINE_QNODE(_name, _id, _buswidth, ...) \
- static const struct qcom_osm_l3_node _name = { \
+#define DEFINE_QNODE(_name, _buswidth, ...) \
+ static struct qcom_osm_l3_node _name = { \
.name = #_name, \
- .id = _id, \
.buswidth = _buswidth, \
.num_links = COUNT_ARGS(__VA_ARGS__), \
- .links = { __VA_ARGS__ }, \
+ __VA_OPT__(.links = { #__VA_ARGS__ }) \
}
-DEFINE_QNODE(osm_l3_master, OSM_L3_MASTER_NODE, 16, OSM_L3_SLAVE_NODE);
-DEFINE_QNODE(osm_l3_slave, OSM_L3_SLAVE_NODE, 16);
+DEFINE_QNODE(osm_l3_master, 16, osm_l3_slave);
+DEFINE_QNODE(osm_l3_slave, 16);
-static const struct qcom_osm_l3_node * const osm_l3_nodes[] = {
+static struct qcom_osm_l3_node * const osm_l3_nodes[] = {
[MASTER_OSM_L3_APPS] = &osm_l3_master,
[SLAVE_OSM_L3] = &osm_l3_slave,
};
-DEFINE_QNODE(epss_l3_master, OSM_L3_MASTER_NODE, 32, OSM_L3_SLAVE_NODE);
-DEFINE_QNODE(epss_l3_slave, OSM_L3_SLAVE_NODE, 32);
+DEFINE_QNODE(epss_l3_master, 32, epss_l3_slave);
+DEFINE_QNODE(epss_l3_slave, 32);
-static const struct qcom_osm_l3_node * const epss_l3_nodes[] = {
+static struct qcom_osm_l3_node * const epss_l3_nodes[] = {
[MASTER_EPSS_L3_APPS] = &epss_l3_master,
[SLAVE_EPSS_L3_SHARED] = &epss_l3_slave,
};
@@ -123,6 +125,19 @@ static const struct qcom_osm_l3_desc epss_l3_l3_vote = {
.reg_perf_state = EPSS_REG_L3_VOTE,
};
+static u16 get_node_id_by_name(const char *node_name,
+ const struct qcom_osm_l3_desc *desc)
+{
+ struct qcom_osm_l3_node *const *nodes = desc->nodes;
+ int i;
+
+ for (i = 0; i < desc->num_nodes; i++) {
+ if (!strcmp(nodes[i]->name, node_name))
+ return nodes[i]->id;
+ }
+ return 0;
+}
+
static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
{
struct qcom_osm_l3_icc_provider *qp;
@@ -164,10 +179,11 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
const struct qcom_osm_l3_desc *desc;
struct icc_onecell_data *data;
struct icc_provider *provider;
- const struct qcom_osm_l3_node * const *qnodes;
+ struct qcom_osm_l3_node * const *qnodes;
struct icc_node *node;
size_t num_nodes;
struct clk *clk;
+ u64 addr;
int ret;
clk = clk_get(&pdev->dev, "xo");
@@ -188,6 +204,10 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
if (!qp)
return -ENOMEM;
+ ret = of_property_read_reg(pdev->dev.of_node, 0, &addr, NULL);
+ if (ret)
+ return ret;
+
qp->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(qp->base))
return PTR_ERR(qp->base);
@@ -242,8 +262,13 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
icc_provider_init(provider);
+ /* Allocate unique id for qnodes */
+ for (i = 0; i < num_nodes; i++)
+ qnodes[i]->id = ida_alloc_min(&osm_l3_id, OSM_L3_NODE_ID_START, GFP_KERNEL);
+
for (i = 0; i < num_nodes; i++) {
- size_t j;
+ char *node_name;
+ size_t j, len;
node = icc_node_create(qnodes[i]->id);
if (IS_ERR(node)) {
@@ -251,13 +276,29 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
goto err;
}
- node->name = qnodes[i]->name;
+ /* len = strlen(node->name) + @ + 8 (base-address) + NULL */
+ len = strlen(qnodes[i]->name) + OSM_NODE_NAME_SUFFIX_SIZE;
+ node_name = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
+ if (!node_name) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ snprintf(node_name, len, "%s@%08llx", qnodes[i]->name, addr);
+ node->name = node_name;
+
/* Cast away const and add it back in qcom_osm_l3_set() */
node->data = (void *)qnodes[i];
icc_node_add(node, provider);
- for (j = 0; j < qnodes[i]->num_links; j++)
- icc_link_create(node, qnodes[i]->links[j]);
+ for (j = 0; j < qnodes[i]->num_links; j++) {
+ u16 link_node_id = get_node_id_by_name(qnodes[i]->links[j], desc);
+
+ if (link_node_id)
+ icc_link_create(node, link_node_id);
+ else
+ goto err;
+ }
data->nodes[i] = node;
}
@@ -284,6 +325,7 @@ static const struct of_device_id osm_l3_of_match[] = {
{ .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 },
{ .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 },
{ .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state },
+ { .compatible = "qcom,sa8775p-epss-l3", .data = &epss_l3_perf_state },
{ }
};
MODULE_DEVICE_TABLE(of, osm_l3_of_match);
--
2.39.2
^ permalink raw reply [flat|nested] 8+ messages in thread