[PATCH v3 0/2] arm64: dts: agilex5: add support for debug daughter card

[PATCH v3 0/2] arm64: dts: agilex5: add support for debug daughter card

[Adrian Ng Ho Yin]

The Agilex5 SoCDK supports an optional debug daughter card that requires
a dedicated device tree variant due to differences in peripheral
connectivity compared to the standard SoCDK configuration.

When the debug daughter card is fitted:
  - gpio0 is unrouted and remains disabled; HPS LED is on gpio1 (portb)
  - gmac2 is replaced by gmac0 for Ethernet connectivity
  - spi0 is connected to a Microchip 25AA128 16 KByte SPI EEPROM

The board compatible (intel,socfpga-agilex5-socdk-debug) is already
present in altera.yaml and is not part of this series.

---
changelog:
v2->v3:
- Remap HPS LED to &portb 12 (gpio1): gpio0 is unrouted, so keeping
  &porta would leave leds-gpio in perpetual probe deferral
- Retain spi0 dmas/dma-names from the SoC DTSI; do not delete them to
  work around a software/defconfig issue (DT should describe hardware)
- Add microchip,25aa128 to the at25 binding and use
  "microchip,25aa128", "atmel,at25" for the EEPROM node
- Drop the altera.yaml compatible patch (already accepted/applied)
- Use &usb31 to match the current Agilex5 SoCDK USB topology

v1->v2:
- Use socfpga_agilex5.dtsi as the base include instead of
  socfpga_agilex5_socdk.dts to follow the convention that .dts files
  are final compilation units and should not be included by other files
- Replace spidev node (with fake rohm,dh2228fv compatible) with a
  proper atmel,at25 EEPROM binding describing the actual hardware
- Remove dmas/dma-names from spi0: CONFIG_DW_AXI_DMAC is not enabled
  in the platform defconfig and retaining them stalls the SPI driver
  in probe deferral
- Remove incorrect HPS LED GPIO override; the LED mapping is unchanged
  from the base board
---

Adrian Ng Ho Yin (2):
  dt-bindings: eeprom: at25: add Microchip 25AA128
  arm64: dts: agilex5: add support for debug daughter card

 .../devicetree/bindings/eeprom/at25.yaml      |   1 +
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 .../dts/intel/socfpga_agilex5_socdk_debug.dts | 121 ++++++++++++++++++
 3 files changed, 123 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_debug.dts

-- 
2.49.GIT

[PATCH v3 1/2] dt-bindings: eeprom: at25: add Microchip 25AA128

[Adrian Ng Ho Yin]

Add the vendor-specific compatible for the Microchip 25AA128 SPI EEPROM.
New device trees should pair it with "atmel,at25" rather than using the
bare "atmel,at25" fallback alone.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
---
 Documentation/devicetree/bindings/eeprom/at25.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/eeprom/at25.yaml b/Documentation/devicetree/bindings/eeprom/at25.yaml
index bb78e12b8823..dda69e4d62bf 100644
--- a/Documentation/devicetree/bindings/eeprom/at25.yaml
+++ b/Documentation/devicetree/bindings/eeprom/at25.yaml
@@ -32,6 +32,7 @@ properties:
               - fujitsu,mb85rs256
               - fujitsu,mb85rs64
               - microchip,25aa010a
+              - microchip,25aa128
               - microchip,at25160bn
               - microchip,25lc040
               - st,m95m02
-- 
2.49.GIT

[PATCH v3 2/2] arm64: dts: agilex5: add support for debug daughter card

[Adrian Ng Ho Yin]

The debug daughter card replaces gmac2 with gmac0 for Ethernet, leaves
gpio0 unrouted (HPS LED on gpio1/portb), and adds a Microchip 25AA128
16 KByte SPI EEPROM on spi0. Retain the SoC dmas/dma-names on spi0 so
the DT continues to describe the hardware DMA wiring. Set
spi-max-frequency to 500 kHz for board signal-integrity limits.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
---
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 .../dts/intel/socfpga_agilex5_socdk_debug.dts | 121 ++++++++++++++++++
 2 files changed, 122 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_debug.dts

diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index b52cd2330cef..96dcbeed032c 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
 				socfpga_agilex3_socdk.dtb \
 				socfpga_agilex5_socdk.dtb \
 				socfpga_agilex5_socdk_013b.dtb \
+				socfpga_agilex5_socdk_debug.dtb \
 				socfpga_agilex5_socdk_emmc.dtb \
 				socfpga_agilex5_socdk_modular.dtb \
 				socfpga_agilex5_socdk_nand.dtb \
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_debug.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_debug.dts
new file mode 100644
index 000000000000..b7b53576a136
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_debug.dts
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026, Altera Corporation
+ */
+#include "socfpga_agilex5.dtsi"
+
+/ {
+	model = "SoCFPGA Agilex5 SoCDK - debug daughter card";
+	compatible = "intel,socfpga-agilex5-socdk-debug", "intel,socfpga-agilex5";
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		ethernet2 = &gmac2;
+		i3c0 = &i3c0;
+		i3c1 = &i3c1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			label = "hps_led0";
+			/* gpio0 is unrouted on the debug daughter card; LED is on gpio1 */
+			gpios = <&portb 12 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the reg */
+		reg = <0x0 0x80000000 0x0 0x0>;
+	};
+};
+
+&gmac0 {
+	status = "okay";
+	phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */
+	phy-handle = <&emac0_phy0>;
+	max-frame-size = <9000>;
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		emac0_phy0: ethernet-phy@0 {
+			reg = <0>;
+		};
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&osc1 {
+	clock-frequency = <25000000>;
+};
+
+&qspi {
+	status = "okay";
+	flash@0 {
+		compatible = "micron,mt25qu02g", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <100000000>;
+		m25p,fast-read;
+		cdns,read-delay = <2>;
+		cdns,tshsl-ns = <50>;
+		cdns,tsd2d-ns = <50>;
+		cdns,tchsh-ns = <4>;
+		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			qspi_boot: partition@0 {
+				label = "Boot and fpga data";
+				reg = <0x0 0x04200000>;
+			};
+
+			root: partition@4200000 {
+				label = "root";
+				reg = <0x04200000 0x0be00000>;
+			};
+		};
+	};
+};
+
+&spi0 {
+	status = "okay";
+
+	eeprom@0 {
+		compatible = "microchip,25aa128", "atmel,at25";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+		size = <16384>;
+		pagesize = <64>;
+		address-width = <16>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb31 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};
-- 
2.49.GIT