[PATCH v2 0/2] clk: vc5: Add IDT VersaClock 5P49V5925

[PATCH v2 0/2] clk: vc5: Add IDT VersaClock 5P49V5925

[Vladimir Barinov]

Hello,

This adds the folowing:
- Update IDT VersaClock 5 driver to support 5P49V5925
- Add bindings for IDT VersaClock 5P49V5925

This has the following dependency:
- [V3,7/8] clk: vc5: Add bindings for IDT VersaClock 5P49V6901
- [V3,8/8] clk: vc5: Add support for IDT VersaClock 5P49V6901

Vladimir Barinov (2):
[1/2] clk: vc5: Add support for IDT VersaClock 5P49V5925
[2/2] dt: Add bindings for IDT VersaClock 5P49V5925

---
This patchset is against the 'kernel/git/torvalds/linux.git' repo.

 Documentation/devicetree/bindings/clock/idt,versaclock5.txt |   11 +++++++----
 drivers/clk/clk-versaclock5.c                               |   11 +++++++++++
 2 files changed, 18 insertions(+), 4 deletions(-)

[PATCH v2 1/2] clk: vc5: Add support for IDT VersaClock 5P49V5925

[Vladimir Barinov]

From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>

Update IDT VersaClock 5 driver to support 5P49V5925. This chip has only
external clock input, four fractional dividers (FODs) and five clock
outputs (four universal clock outputs and one reference clock output at
OUT0_SELB_I2C).

Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
---
Changes in version 2:
- rebased against patch:
  [V3,8/8] clk: vc5: Add support for IDT VersaClock 5P49V6901

 drivers/clk/clk-versaclock5.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
index c894db2..1808a55 100644
--- a/drivers/clk/clk-versaclock5.c
+++ b/drivers/clk/clk-versaclock5.c
@@ -129,6 +129,7 @@
 /* Supported IDT VC5 models. */
 enum vc5_model {
 	IDT_VC5_5P49V5923,
+	IDT_VC5_5P49V5925,
 	IDT_VC5_5P49V5933,
 	IDT_VC5_5P49V5935,
 	IDT_VC6_5P49V6901,
@@ -686,6 +687,7 @@ static int vc5_map_index_to_output(const enum vc5_model model,
 	case IDT_VC5_5P49V5933:
 		return (n == 0) ? 0 : 3;
 	case IDT_VC5_5P49V5923:
+	case IDT_VC5_5P49V5925:
 	case IDT_VC5_5P49V5935:
 	case IDT_VC6_5P49V6901:
 	default:
@@ -911,6 +913,13 @@ static int vc5_remove(struct i2c_client *client)
 	.flags = 0,
 };
 
+static const struct vc5_chip_info idt_5p49v5925_info = {
+	.model = IDT_VC5_5P49V5925,
+	.clk_fod_cnt = 4,
+	.clk_out_cnt = 5,
+	.flags = 0,
+};
+
 static const struct vc5_chip_info idt_5p49v5933_info = {
 	.model = IDT_VC5_5P49V5933,
 	.clk_fod_cnt = 2,
@@ -934,6 +943,7 @@ static int vc5_remove(struct i2c_client *client)
 
 static const struct i2c_device_id vc5_id[] = {
 	{ "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
+	{ "5p49v5925", .driver_data = IDT_VC5_5P49V5925 },
 	{ "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
 	{ "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
 	{ "5p49v6901", .driver_data = IDT_VC6_5P49V6901 },
@@ -943,6 +953,7 @@ static int vc5_remove(struct i2c_client *client)
 
 static const struct of_device_id clk_vc5_of_match[] = {
 	{ .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
+	{ .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },
 	{ .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
 	{ .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
 	{ .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
-- 
1.9.1

[PATCH v2 2/2] dt: Add bindings for IDT VersaClock 5P49V5925

[Vladimir Barinov]

From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>

IDT VersaClock 5 5P49V5925 has 5 clock outputs, 4 fractional dividers.
Input clock source can be taken only from external reference clock.

Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
---
Changes in version 2:
- fixed typo in patch header: VC5 has 5 clock outputs
- rebased against patch:
  [V3,7/8] clk: vc5: Add bindings for IDT VersaClock 5P49V6901

 Documentation/devicetree/bindings/clock/idt,versaclock5.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
index 66ef0a0..05a245c 100644
--- a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
+++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
@@ -8,6 +8,7 @@ generators providing from 3 to 12 output clocks.
 Required properties:
 - compatible:	shall be one of
 		"idt,5p49v5923"
+		"idt,5p49v5925"
 		"idt,5p49v5933"
 		"idt,5p49v5935"
 		"idt,5p49v6901"
@@ -15,6 +16,7 @@ Required properties:
 - #clock-cells:	from common clock binding; shall be set to 1.
 - clocks:	from common clock binding; list of parent clock handles,
 		- 5p49v5923 and
+		  5p49v5925 and
 		  5p49v6901: (required) either or both of XTAL or CLKIN
 					reference clock.
 		- 5p49v5933 and
@@ -23,6 +25,7 @@ Required properties:
 					clock.
 - clock-names:	from common clock binding; clock input names, can be
 		- 5p49v5923 and
+		  5p49v5925 and
 		  5p49v6901: (required) either or both of "xin", "clkin".
 		- 5p49v5933 and
 		- 5p49v5935: (optional) property not present or "clkin".
@@ -42,6 +45,7 @@ clock specifier, the following mapping applies:
 	1 -- OUT1
 	2 -- OUT4
 
+5P49V5925 and
 5P49V5935:
 	0 -- OUT0_SEL_I2CB
 	1 -- OUT1
-- 
1.9.1

Re: [PATCH v2 2/2] dt: Add bindings for IDT VersaClock 5P49V5925

[Marek Vasut]

On 07/09/2017 07:40 PM, Vladimir Barinov wrote:
> From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
> 
> IDT VersaClock 5 5P49V5925 has 5 clock outputs, 4 fractional dividers.
> Input clock source can be taken only from external reference clock.
> 
> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>

Reviewed-by: Marek Vasut <marek.vasut@gmail.com>

> ---
> Changes in version 2:
> - fixed typo in patch header: VC5 has 5 clock outputs
> - rebased against patch:
>   [V3,7/8] clk: vc5: Add bindings for IDT VersaClock 5P49V6901
> 
>  Documentation/devicetree/bindings/clock/idt,versaclock5.txt | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
> index 66ef0a0..05a245c 100644
> --- a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
> +++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
> @@ -8,6 +8,7 @@ generators providing from 3 to 12 output clocks.
>  Required properties:
>  - compatible:	shall be one of
>  		"idt,5p49v5923"
> +		"idt,5p49v5925"
>  		"idt,5p49v5933"
>  		"idt,5p49v5935"
>  		"idt,5p49v6901"
> @@ -15,6 +16,7 @@ Required properties:
>  - #clock-cells:	from common clock binding; shall be set to 1.
>  - clocks:	from common clock binding; list of parent clock handles,
>  		- 5p49v5923 and
> +		  5p49v5925 and
>  		  5p49v6901: (required) either or both of XTAL or CLKIN
>  					reference clock.
>  		- 5p49v5933 and
> @@ -23,6 +25,7 @@ Required properties:
>  					clock.
>  - clock-names:	from common clock binding; clock input names, can be
>  		- 5p49v5923 and
> +		  5p49v5925 and
>  		  5p49v6901: (required) either or both of "xin", "clkin".
>  		- 5p49v5933 and
>  		- 5p49v5935: (optional) property not present or "clkin".
> @@ -42,6 +45,7 @@ clock specifier, the following mapping applies:
>  	1 -- OUT1
>  	2 -- OUT4
>  
> +5P49V5925 and
>  5P49V5935:
>  	0 -- OUT0_SEL_I2CB
>  	1 -- OUT1
> 


-- 
Best regards,
Marek Vasut

Re: [PATCH v2 2/2] dt: Add bindings for IDT VersaClock 5P49V5925

[Rob Herring]

On Sun, Jul 09, 2017 at 08:40:05PM +0300, Vladimir Barinov wrote:
> From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
> 
> IDT VersaClock 5 5P49V5925 has 5 clock outputs, 4 fractional dividers.
> Input clock source can be taken only from external reference clock.
> 
> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
> ---
> Changes in version 2:
> - fixed typo in patch header: VC5 has 5 clock outputs
> - rebased against patch:
>   [V3,7/8] clk: vc5: Add bindings for IDT VersaClock 5P49V6901
> 
>  Documentation/devicetree/bindings/clock/idt,versaclock5.txt | 4 ++++
>  1 file changed, 4 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>