[PATCH 0/2] arm64: dts: socfpga: agilex: add Agilex7F SoCDK multi-QSPI board

[PATCH 0/2] arm64: dts: socfpga: agilex: add Agilex7F SoCDK multi-QSPI board

[genevieve.chan]

From: Genevieve Chan <genevieve.chan@altera.com>

Add device tree support for the Agilex7F SoCDK board variant with
multi-QSPI flash. Patch 1 adds the board compatible to the Altera DT
bindings. Patch 2 adds the board DTS, based on socfpga_agilex.dtsi,
describing four Micron MT25QU02G flashes on chip selects 0-3.

Genevieve Chan (2):
  dt-bindings: arm: altera: add Agilex7F SoCDK multi-QSPI compatible
  arm64: dts: socfpga: agilex: add Agilex7F SoCDK multi-QSPI board

 .../devicetree/bindings/arm/altera.yaml       |   1 +
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 .../socfpga_agilex7f_socdk_multiqspi.dts      | 214 ++++++++++++++++++
 3 files changed, 216 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_multiqspi.dts

--
2.43.7

[PATCH 1/2] dt-bindings: arm: altera: add Agilex7F SoCDK multi-QSPI compatible

[genevieve.chan]

From: Genevieve Chan <genevieve.chan@altera.com>

Add "intel,socfpga-agilex7f-socdk-multiqspi" for the Agilex7F SoCDK
board variant with multi-QSPI flash support.

Signed-off-by: Genevieve Chan <genevieve.chan@altera.com>
---
 Documentation/devicetree/bindings/arm/altera.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
index 3030cf46fe74..2e7fa5e12530 100644
--- a/Documentation/devicetree/bindings/arm/altera.yaml
+++ b/Documentation/devicetree/bindings/arm/altera.yaml
@@ -97,6 +97,7 @@ properties:
               - intel,socfpga-agilex-n6000
               - intel,socfpga-agilex-socdk
               - intel,socfpga-agilex-socdk-emmc
+              - intel,socfpga-agilex7f-socdk-multiqspi
           - const: intel,socfpga-agilex
 
       - description: Agilex3 boards
-- 
2.43.7

Re: [PATCH 1/2] dt-bindings: arm: altera: add Agilex7F SoCDK multi-QSPI compatible

[Krzysztof Kozlowski]

On Mon, Sep 14, 2026 at 10:50:51AM +0800, genevieve.chan@altera.com wrote:
> From: Genevieve Chan <genevieve.chan@altera.com>
> 
> Add "intel,socfpga-agilex7f-socdk-multiqspi" for the Agilex7F SoCDK
> board variant with multi-QSPI flash support.

Why is agilex7f the same as agilex?

Your commit msg is pretty redundant, just copies diff instead of
explaining odd things like why do you have exception from rules in
writing bindings.

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: arm: altera: add Agilex7F SoCDK multi-QSPI compatible

[Chan, Genevieve]

On 15/9/2026 6:49 pm, Krzysztof Kozlowski wrote:
 > On Mon, Sep 14, 2026 at 10:50:51AM +0800, Genevieve Chan wrote:
 >> From: Genevieve Chan <genevieve.chan@altera.com>
 >>
 >> Add "intel,socfpga-agilex7f-socdk-multiqspi" for the Agilex7F SoCDK
 >> board variant with multi-QSPI flash support.
 >
 > Why is agilex7f the same as agilex?

Hi Krzysztof,

It is the same SoC. The original Agilex family was renamed to
"Agilex 7" when the Agilex 5 and Agilex 3 families were introduced,
so "Agilex 7 F-Series" is the current product name of the
Agilex F-Series device. The silicon and the HPS are unchanged, which
is why the board uses socfpga_agilex.dtsi and falls back to
"intel,socfpga-agilex", like the existing Agilex SoCDK boards.

Using "agilex7f" in the board compatible creates a confusion, as it
suggests a different SoC. In v2 I will rename it to
"intel,socfpga-agilex-socdk-multiqspi" to follow the existing
"intel,socfpga-agilex-socdk" and "intel,socfpga-agilex-socdk-emmc"
entries.

 > Your commit msg is pretty redundant, just copies diff instead of
 > explaining odd things like why do you have exception from rules in
 > writing bindings.

Understood. With the fixes mentioned earlier, there will no longer be an 
exception to the naming rules. In v2 the commit message will explain how 
this board differs from the standard Agilex SoCDK (the multi-QSPI flash
population) and why it needs its own compatible, instead of
repeating the diff.

Thanks,
Genevieve

[PATCH 2/2] arm64: dts: socfpga: agilex: add Agilex7F SoCDK multi-QSPI board

[genevieve.chan]

From: Genevieve Chan <genevieve.chan@altera.com>

Add a board device tree for the Agilex7F SoCDK with multi-QSPI support.
Describe four Micron MT25QU02G flashes on chip selects 0-3, based on
socfpga_agilex.dtsi like other Agilex board variants.

Signed-off-by: Genevieve Chan <genevieve.chan@altera.com>
---
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 .../socfpga_agilex7f_socdk_multiqspi.dts      | 214 ++++++++++++++++++
 2 files changed, 215 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_multiqspi.dts

diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index 270c70fdf084..9298ab8b9314 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -10,5 +10,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
 				socfpga_agilex5_socdk_nand.dtb \
 				socfpga_agilex72_socdk.dtb \
 				socfpga_agilex7m_socdk.dtb \
+				socfpga_agilex7f_socdk_multiqspi.dtb \
 				socfpga_n5x_socdk.dtb
 dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_multiqspi.dts b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_multiqspi.dts
new file mode 100644
index 000000000000..7d444a84fd67
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_multiqspi.dts
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026, Intel Corporation
+ */
+#include "socfpga_agilex.dtsi"
+
+/ {
+	model = "SoCFPGA Agilex7F SoCDK multi-QSPI";
+	compatible = "intel,socfpga-agilex7f-socdk-multiqspi",
+		     "intel,socfpga-agilex";
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		ethernet2 = &gmac2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led0 {
+			label = "hps_led0";
+			gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
+		};
+
+		led1 {
+			label = "hps_led1";
+			gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
+		};
+
+		led2 {
+			label = "hps_led2";
+			gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the reg */
+		reg = <0 0x80000000 0 0>;
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gmac0 {
+	status = "okay";
+	/* PHY delays are configured via skew properties */
+	phy-mode = "rgmii";
+	phy-handle = <&phy0>;
+
+	max-frame-size = <9000>;
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		phy0: ethernet-phy@4 {
+			reg = <4>;
+
+			txd0-skew-ps = <0>; /* -420ps */
+			txd1-skew-ps = <0>; /* -420ps */
+			txd2-skew-ps = <0>; /* -420ps */
+			txd3-skew-ps = <0>; /* -420ps */
+			rxd0-skew-ps = <420>; /* 0ps */
+			rxd1-skew-ps = <420>; /* 0ps */
+			rxd2-skew-ps = <420>; /* 0ps */
+			rxd3-skew-ps = <420>; /* 0ps */
+			txen-skew-ps = <0>; /* -420ps */
+			txc-skew-ps = <900>; /* 0ps */
+			rxdv-skew-ps = <420>; /* 0ps */
+			rxc-skew-ps = <1680>; /* 780ps */
+		};
+	};
+};
+
+&mmc {
+	status = "okay";
+	cap-sd-highspeed;
+	broken-cd;
+	bus-width = <4>;
+	clk-phase-sd-hs = <0>, <135>;
+};
+
+&osc1 {
+	clock-frequency = <25000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	disable-over-current;
+};
+
+&watchdog0 {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+
+	flash@0 {
+		compatible = "micron,mt25qu02g", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+
+		m25p,fast-read;
+		cdns,read-delay = <2>;
+		cdns,tshsl-ns = <50>;
+		cdns,tsd2d-ns = <50>;
+		cdns,tchsh-ns = <4>;
+		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			qspi_boot0: partition@0 {
+				label = "Boot and fpga data";
+				reg = <0x0 0x10000000>;
+			};
+		};
+	};
+
+	flash@1 {
+		compatible = "micron,mt25qu02g", "jedec,spi-nor";
+		reg = <1>;
+		spi-max-frequency = <25000000>;
+
+		m25p,fast-read;
+		cdns,read-delay = <2>;
+		cdns,tshsl-ns = <50>;
+		cdns,tsd2d-ns = <50>;
+		cdns,tchsh-ns = <4>;
+		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			qspi_boot1: partition@0 {
+				label = "Boot and fpga data";
+				reg = <0x0 0x10000000>;
+			};
+		};
+	};
+
+	flash@2 {
+		compatible = "micron,mt25qu02g", "jedec,spi-nor";
+		reg = <2>;
+		spi-max-frequency = <25000000>;
+
+		m25p,fast-read;
+		cdns,read-delay = <2>;
+		cdns,tshsl-ns = <50>;
+		cdns,tsd2d-ns = <50>;
+		cdns,tchsh-ns = <4>;
+		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			qspi_boot2: partition@0 {
+				label = "Boot and fpga data";
+				reg = <0x0 0x10000000>;
+			};
+		};
+	};
+
+	flash@3 {
+		compatible = "micron,mt25qu02g", "jedec,spi-nor";
+		reg = <3>;
+		spi-max-frequency = <25000000>;
+
+		m25p,fast-read;
+		cdns,read-delay = <2>;
+		cdns,tshsl-ns = <50>;
+		cdns,tsd2d-ns = <50>;
+		cdns,tchsh-ns = <4>;
+		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			qspi_boot3: partition@0 {
+				label = "Boot and fpga data";
+				reg = <0x0 0x10000000>;
+			};
+		};
+	};
+};
-- 
2.43.7