* [PATCH RESEND v3 2/2] arm64: dts: socfpga: agilex5: add clock-names property to nand node
@ 2025-02-28 4:53 niravkumar.l.rabara
2025-03-04 12:48 ` Dinh Nguyen
0 siblings, 1 reply; 2+ messages in thread
From: niravkumar.l.rabara @ 2025-02-28 4:53 UTC (permalink / raw)
To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
niravkumar.l.rabara, nirav.rabara, devicetree, linux-kernel
Cc: Krzysztof Kozlowski
From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Add required clock-names property to the nand node.
Fixes: 2d599bc43813 (arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
---
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 51c6e19e40b8..27f75e1bc8eb 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -271,6 +271,7 @@ nand: nand-controller@10b80000 {
#size-cells = <0>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkmgr AGILEX5_NAND_NF_CLK>;
+ clock-names = "nf_clk";
cdns,board-delay-ps = <4830>;
status = "disabled";
};
--
2.25.1
^ permalink raw reply [flat|nested] 2+ messages in thread* Re: [PATCH RESEND v3 2/2] arm64: dts: socfpga: agilex5: add clock-names property to nand node
2025-02-28 4:53 [PATCH RESEND v3 2/2] arm64: dts: socfpga: agilex5: add clock-names property to nand node niravkumar.l.rabara
@ 2025-03-04 12:48 ` Dinh Nguyen
0 siblings, 0 replies; 2+ messages in thread
From: Dinh Nguyen @ 2025-03-04 12:48 UTC (permalink / raw)
To: niravkumar.l.rabara, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, nirav.rabara, devicetree, linux-kernel
Cc: Krzysztof Kozlowski
On 2/27/25 22:53, niravkumar.l.rabara@intel.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
>
> Add required clock-names property to the nand node.
>
> Fixes: 2d599bc43813 (arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA)
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> ---
> arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 51c6e19e40b8..27f75e1bc8eb 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -271,6 +271,7 @@ nand: nand-controller@10b80000 {
> #size-cells = <0>;
> interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clkmgr AGILEX5_NAND_NF_CLK>;
> + clock-names = "nf_clk";
> cdns,board-delay-ps = <4830>;
> status = "disabled";
> };
Applied!
Thanks,
Dinh
^ permalink raw reply [flat|nested] 2+ messages in thread
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2025-02-28 4:53 [PATCH RESEND v3 2/2] arm64: dts: socfpga: agilex5: add clock-names property to nand node niravkumar.l.rabara
2025-03-04 12:48 ` Dinh Nguyen
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