* [PATCH] x86/resctrl: Rename AMD resctrl MSR defines to use MSR_AMD_ prefix
@ 2026-07-22 16:57 Babu Moger
2026-08-12 22:29 ` Reinette Chatre
0 siblings, 1 reply; 2+ messages in thread
From: Babu Moger @ 2026-07-22 16:57 UTC (permalink / raw)
To: tglx, mingo, bp, tony.luck, reinette.chatre
Cc: dave.hansen, x86, hpa, Dave.Martin, james.morse, babu.moger,
dapeng1.mi, peterz, seanjc, chang.seok.bae, acme, namhyung,
kan.liang, prathyushi.nangia, linux-kernel
Several resctrl MSRs in the AMD address range (0xc0000xxx) were defined
with an MSR_IA32_ prefix even though they are AMD-specific and unrelated
to Intel's IA32 resctrl MSRs. The MSR_IA32_ prefix is misleading when
reading or grepping the codebase alongside the Intel MSR_IA32_* resctrl
definitions in msr-index.h.
Rename the AMD resctrl MSR definitions, update all call sites, and keep
the tools copy of msr-index.h in sync:
MSR_IA32_MBA_BW_BASE -> MSR_AMD_MBA_BW_BASE
MSR_IA32_SMBA_BW_BASE -> MSR_AMD_SMBA_BW_BASE
MSR_IA32_L3_QOS_ABMC_CFG -> MSR_AMD_L3_QOS_ABMC_CFG
MSR_IA32_L3_QOS_EXT_CFG -> MSR_AMD_L3_QOS_EXT_CFG
MSR_IA32_EVT_CFG_BASE -> MSR_AMD_EVT_CFG_BASE
No functional changes.
Suggested-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
arch/x86/include/asm/msr-index.h | 10 +++++-----
arch/x86/kernel/cpu/resctrl/core.c | 4 ++--
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 6 +++---
arch/x86/kernel/cpu/resctrl/internal.h | 4 ++--
arch/x86/kernel/cpu/resctrl/monitor.c | 6 +++---
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 4 ++--
fs/resctrl/rdtgroup.c | 4 ++--
tools/arch/x86/include/asm/msr-index.h | 10 +++++-----
8 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 18c4be75e927..b68ad3088779 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -1290,11 +1290,11 @@
#define MSR_IA32_MBA_THRTL_BASE 0xd50
/* - AMD: */
-#define MSR_IA32_MBA_BW_BASE 0xc0000200
-#define MSR_IA32_SMBA_BW_BASE 0xc0000280
-#define MSR_IA32_L3_QOS_ABMC_CFG 0xc00003fd
-#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff
-#define MSR_IA32_EVT_CFG_BASE 0xc0000400
+#define MSR_AMD_MBA_BW_BASE 0xc0000200
+#define MSR_AMD_SMBA_BW_BASE 0xc0000280
+#define MSR_AMD_L3_QOS_ABMC_CFG 0xc00003fd
+#define MSR_AMD_L3_QOS_EXT_CFG 0xc00003ff
+#define MSR_AMD_EVT_CFG_BASE 0xc0000400
/* AMD-V MSRs */
#define MSR_VM_CR 0xc0010114
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index cf780c1969e9..cd32851876e2 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -1051,10 +1051,10 @@ static __init void rdt_init_res_defs_amd(void)
r->cache.arch_has_per_cpu_cfg = true;
r->cache.min_cbm_bits = 0;
} else if (r->rid == RDT_RESOURCE_MBA) {
- hw_res->msr_base = MSR_IA32_MBA_BW_BASE;
+ hw_res->msr_base = MSR_AMD_MBA_BW_BASE;
hw_res->msr_update = mba_wrmsr_amd;
} else if (r->rid == RDT_RESOURCE_SMBA) {
- hw_res->msr_base = MSR_IA32_SMBA_BW_BASE;
+ hw_res->msr_base = MSR_AMD_SMBA_BW_BASE;
hw_res->msr_update = mba_wrmsr_amd;
}
}
diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
index e74f1ed54b86..ed14256d7f3b 100644
--- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
+++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
@@ -102,9 +102,9 @@ static void resctrl_sdciae_set_one_amd(void *arg)
bool *enable = arg;
if (*enable)
- msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
+ msr_set_bit(MSR_AMD_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
else
- msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
+ msr_clear_bit(MSR_AMD_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
}
static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable)
@@ -114,7 +114,7 @@ static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable)
/* Walking r->ctrl_domains, ensure it can't race with cpuhp */
lockdep_assert_cpus_held();
- /* Update MSR_IA32_L3_QOS_EXT_CFG MSR on all the CPUs in all domains */
+ /* Update MSR_AMD_L3_QOS_EXT_CFG MSR on all the CPUs in all domains */
list_for_each_entry_rcu(d, &r->ctrl_domains, hdr.list, lockdep_is_cpus_held())
on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, 1);
}
diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
index e3cfa0c10e92..6e7f6e0d1bf8 100644
--- a/arch/x86/kernel/cpu/resctrl/internal.h
+++ b/arch/x86/kernel/cpu/resctrl/internal.h
@@ -49,7 +49,7 @@ struct arch_mbm_state {
#define ABMC_EXTENDED_EVT_ID BIT(31)
#define ABMC_EVT_ID BIT(0)
-/* Setting bit 1 in MSR_IA32_L3_QOS_EXT_CFG enables the SDCIAE feature. */
+/* Setting bit 1 in MSR_AMD_L3_QOS_EXT_CFG enables the SDCIAE feature. */
#define SDCIAE_ENABLE_BIT 1
/**
@@ -187,7 +187,7 @@ union cpuid_0x10_x_edx {
};
/*
- * ABMC counters are configured by writing to MSR_IA32_L3_QOS_ABMC_CFG.
+ * ABMC counters are configured by writing to MSR_AMD_L3_QOS_ABMC_CFG.
*
* @bw_type : Event configuration that represents the memory
* transactions being tracked by the @cntr_id.
diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c
index 3838e0a13d36..a2c9acc7aec8 100644
--- a/arch/x86/kernel/cpu/resctrl/monitor.c
+++ b/arch/x86/kernel/cpu/resctrl/monitor.c
@@ -498,9 +498,9 @@ static void resctrl_abmc_set_one_amd(void *arg)
bool *enable = arg;
if (*enable)
- msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT);
+ msr_set_bit(MSR_AMD_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT);
else
- msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT);
+ msr_clear_bit(MSR_AMD_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT);
}
/*
@@ -542,7 +542,7 @@ static void resctrl_abmc_config_one_amd(void *info)
{
union l3_qos_abmc_cfg *abmc_cfg = info;
- wrmsrq(MSR_IA32_L3_QOS_ABMC_CFG, abmc_cfg->full);
+ wrmsrq(MSR_AMD_L3_QOS_ABMC_CFG, abmc_cfg->full);
}
/*
diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
index 5ffa39fa86fa..6590ebf6b29d 100644
--- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
+++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
@@ -96,7 +96,7 @@ void resctrl_arch_mon_event_config_read(void *_config_info)
pr_warn_once("Invalid event id %d\n", config_info->evtid);
return;
}
- rdmsrq(MSR_IA32_EVT_CFG_BASE + index, msrval);
+ rdmsrq(MSR_AMD_EVT_CFG_BASE + index, msrval);
/* Report only the valid event configuration bits */
config_info->mon_config = msrval & MAX_EVT_CONFIG_BITS;
@@ -112,7 +112,7 @@ void resctrl_arch_mon_event_config_write(void *_config_info)
pr_warn_once("Invalid event id %d\n", config_info->evtid);
return;
}
- wrmsrq(MSR_IA32_EVT_CFG_BASE + index, config_info->mon_config);
+ wrmsrq(MSR_AMD_EVT_CFG_BASE + index, config_info->mon_config);
}
static void l3_qos_cfg_update(void *arg)
diff --git a/fs/resctrl/rdtgroup.c b/fs/resctrl/rdtgroup.c
index 30df902ea776..30c4c57e0e4c 100644
--- a/fs/resctrl/rdtgroup.c
+++ b/fs/resctrl/rdtgroup.c
@@ -1785,8 +1785,8 @@ static void mbm_config_write_domain(struct rdt_resource *r,
mon_info.mon_config = val;
/*
- * Update MSR_IA32_EVT_CFG_BASE MSR on one of the CPUs in the
- * domain. The MSRs offset from MSR MSR_IA32_EVT_CFG_BASE
+ * Update MSR_AMD_EVT_CFG_BASE MSR on one of the CPUs in the
+ * domain. The MSRs offset from MSR_AMD_EVT_CFG_BASE
* are scoped at the domain level. Writing any of these MSRs
* on one CPU is observed by all the CPUs in the domain.
*/
diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index eff29645719b..5f11fa3b7b1b 100644
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -1279,11 +1279,11 @@
#define MSR_IA32_MBA_THRTL_BASE 0xd50
/* - AMD: */
-#define MSR_IA32_MBA_BW_BASE 0xc0000200
-#define MSR_IA32_SMBA_BW_BASE 0xc0000280
-#define MSR_IA32_L3_QOS_ABMC_CFG 0xc00003fd
-#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff
-#define MSR_IA32_EVT_CFG_BASE 0xc0000400
+#define MSR_AMD_MBA_BW_BASE 0xc0000200
+#define MSR_AMD_SMBA_BW_BASE 0xc0000280
+#define MSR_AMD_L3_QOS_ABMC_CFG 0xc00003fd
+#define MSR_AMD_L3_QOS_EXT_CFG 0xc00003ff
+#define MSR_AMD_EVT_CFG_BASE 0xc0000400
/* AMD-V MSRs */
#define MSR_VM_CR 0xc0010114
--
2.43.0
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] x86/resctrl: Rename AMD resctrl MSR defines to use MSR_AMD_ prefix
2026-07-22 16:57 [PATCH] x86/resctrl: Rename AMD resctrl MSR defines to use MSR_AMD_ prefix Babu Moger
@ 2026-08-12 22:29 ` Reinette Chatre
0 siblings, 0 replies; 2+ messages in thread
From: Reinette Chatre @ 2026-08-12 22:29 UTC (permalink / raw)
To: Babu Moger, tglx, mingo, bp, tony.luck
Cc: dave.hansen, x86, hpa, Dave.Martin, james.morse, dapeng1.mi,
peterz, seanjc, chang.seok.bae, acme, namhyung, kan.liang,
prathyushi.nangia, linux-kernel
Hi Babu,
On 7/22/26 9:57 AM, Babu Moger wrote:
> Several resctrl MSRs in the AMD address range (0xc0000xxx) were defined
"Several resctrl MSRs" -> "resctrl MSRs"?
(looks like all of them were defined this way)
"were defined" -> "are defined"?
> with an MSR_IA32_ prefix even though they are AMD-specific and unrelated
> to Intel's IA32 resctrl MSRs. The MSR_IA32_ prefix is misleading when
> reading or grepping the codebase alongside the Intel MSR_IA32_* resctrl
> definitions in msr-index.h.
>
> Rename the AMD resctrl MSR definitions, update all call sites, and keep
> the tools copy of msr-index.h in sync:
>
> MSR_IA32_MBA_BW_BASE -> MSR_AMD_MBA_BW_BASE
> MSR_IA32_SMBA_BW_BASE -> MSR_AMD_SMBA_BW_BASE
> MSR_IA32_L3_QOS_ABMC_CFG -> MSR_AMD_L3_QOS_ABMC_CFG
> MSR_IA32_L3_QOS_EXT_CFG -> MSR_AMD_L3_QOS_EXT_CFG
> MSR_IA32_EVT_CFG_BASE -> MSR_AMD_EVT_CFG_BASE
>
> No functional changes.
>
> Suggested-by: Borislav Petkov (AMD) <bp@alien8.de>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> ---
...
> @@ -114,7 +114,7 @@ static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable)
> /* Walking r->ctrl_domains, ensure it can't race with cpuhp */
> lockdep_assert_cpus_held();
>
> - /* Update MSR_IA32_L3_QOS_EXT_CFG MSR on all the CPUs in all domains */
> + /* Update MSR_AMD_L3_QOS_EXT_CFG MSR on all the CPUs in all domains */
I think this is a good opportunity to remove the redundant text when referring to these MSRs.
For example, "Update MSR_AMD_L3_QOS_EXT_CFG MSR ..." can just be "Update MSR_AMD_L3_QOS_EXT_CFG ..."
This is indeed done by this patch, but not consistently.
> list_for_each_entry_rcu(d, &r->ctrl_domains, hdr.list, lockdep_is_cpus_held())
> on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, 1);
> }
...
> diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c
> index 3838e0a13d36..a2c9acc7aec8 100644
> --- a/arch/x86/kernel/cpu/resctrl/monitor.c
> +++ b/arch/x86/kernel/cpu/resctrl/monitor.c
> @@ -498,9 +498,9 @@ static void resctrl_abmc_set_one_amd(void *arg)
> bool *enable = arg;
>
> if (*enable)
> - msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT);
> + msr_set_bit(MSR_AMD_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT);
> else
> - msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT);
> + msr_clear_bit(MSR_AMD_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT);
> }
>
> /*
The comment appearing at this point contains "L3_QOS_EXT_CFG MSR" - the changelog mentions
support for "grepping the codebase" making this a candidate for changing also?
> @@ -542,7 +542,7 @@ static void resctrl_abmc_config_one_amd(void *info)
> {
> union l3_qos_abmc_cfg *abmc_cfg = info;
>
> - wrmsrq(MSR_IA32_L3_QOS_ABMC_CFG, abmc_cfg->full);
> + wrmsrq(MSR_AMD_L3_QOS_ABMC_CFG, abmc_cfg->full);
> }
>
> /*
...
> diff --git a/fs/resctrl/rdtgroup.c b/fs/resctrl/rdtgroup.c
> index 30df902ea776..30c4c57e0e4c 100644
> --- a/fs/resctrl/rdtgroup.c
> +++ b/fs/resctrl/rdtgroup.c
> @@ -1785,8 +1785,8 @@ static void mbm_config_write_domain(struct rdt_resource *r,
> mon_info.mon_config = val;
>
> /*
> - * Update MSR_IA32_EVT_CFG_BASE MSR on one of the CPUs in the
> - * domain. The MSRs offset from MSR MSR_IA32_EVT_CFG_BASE
> + * Update MSR_AMD_EVT_CFG_BASE MSR on one of the CPUs in the
"MSR_AMD_EVT_CFG_BASE MSR" -> "MSR_AMD_EVT_CFG_BASE"?
> + * domain. The MSRs offset from MSR_AMD_EVT_CFG_BASE
Here the redundant text is indeed removed.
> * are scoped at the domain level. Writing any of these MSRs
> * on one CPU is observed by all the CPUs in the domain.
> */
I just have these nits. The patch looks good to me.
Reinette
^ permalink raw reply [flat|nested] 2+ messages in thread
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2026-07-22 16:57 [PATCH] x86/resctrl: Rename AMD resctrl MSR defines to use MSR_AMD_ prefix Babu Moger
2026-08-12 22:29 ` Reinette Chatre
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