Re: [PATCH v13 2/5] PCI: Assume control of portdrv-related features only when portdrv enabled

["Bowman, Terry" <terry.bowman@amd.com>]

On 9/21/2026 2:01 PM, Bjorn Helgaas wrote:
> [+cc Terry, in case you have thoughts about native_cxl_error;
> beginning of thread:
> https://lore.kernel.org/all/20260919162655.3499010-1-sathyanarayanan.kuppuswamy@linux.intel.com]
> 
> On Sun, Sep 20, 2026 at 08:17:21AM +0200, Lukas Wunner wrote:
>> On Sat, Sep 19, 2026 at 09:26:52AM -0700, Kuppuswamy Sathyanarayanan wrote:
>>> +++ b/drivers/pci/probe.c
>>> @@ -668,12 +668,14 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge)
>>>  	 * may implement its own AER handling and use _OSC to prevent the
>>>  	 * OS from interfering.
>>>  	 */
>>> +#ifdef CONFIG_PCIEPORTBUS
>>>  	bridge->native_aer = 1;
>>>  	bridge->native_pcie_hotplug = 1;
>>> -	bridge->native_shpc_hotplug = 1;
>>>  	bridge->native_pme = 1;
>>> -	bridge->native_ltr = 1;
>>>  	bridge->native_dpc = 1;
>>> +#endif
>>> +	bridge->native_ltr = 1;
>>> +	bridge->native_shpc_hotplug = 1;
>>>  	bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET;
>>
>> How about (e.g.)
>>
>>  	bridge->native_pcie_hotplug = IS_ENABLED(CONFIG_PCIEPORTBUS);
>>
>> instead of using #ifdef?  That's the preferred style according to
>> section 21 of Documentation/process/coding-style.rst
>>
>>>  	bridge->native_cxl_error = 1;
>>
>> Hm, this one depends on CONFIG_PCIEAER I believe.
>> (But Terry Bowman is the expert.)

native_cxl_error gates CXL device event record reporting, which is distinct from 
CXL protocol RAS errors. Its only consumer is cxl_event_config(). This should remain:
        bridge->native_cxl_error = 1;
This must be assigned outside of the #ifdef as the corresponding _OSC control is 
based on CONFIG_MEMORY_FAILURE and not CONFIG_PCIEAER.

CXL protocol errors are gated on AER (OSC_PCI_EXPRESS_AER_CONTROL).

-Terry