From: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
To: Andi Kleen <andi@firstfloor.org>
Cc: Ingo Molnar <mingo@elte.hu>,
Peter Zijlstra <peterz@infradead.org>,
Stephane Eranian <eranian@google.com>,
linux-kernel@vger.kernel.org, acme@redhat.com,
ming.m.lin@intel.com, robert.richter@amd.com, ravitillo@lbl.gov
Subject: Re: [PATCH 07/12] perf_events: add LBR software filter support for Intel X86
Date: Tue, 11 Oct 2011 21:59:32 +0900 [thread overview]
Message-ID: <4E943DB4.1070400@hitachi.com> (raw)
In-Reply-To: <20111010144538.GZ14482@one.firstfloor.org>
(2011/10/10 23:45), Andi Kleen wrote:
>> Ah, nice. Maybe we need another test binary, since current one is
>> just ensuring the output of objdump and decoder is same.
>> anyway it's not so difficult if it feeds random binaries to
>> ensure the decoder doesn't access bad address.
>
> Pure /dev/urandom is not good because it cannot be ever reproduced.
> Better use a PRNG with random seed from urandom, but print the seed.
Sure,
> In addition to random I would do fuzzing: take an existing stream
> and just corrupt some bits and groups of bits. This will exercise different
> paths. In fact fuzzing is probably better than random for most tests.
>
> Not sure it's needed to run on every build though, just checks
> now and then should be sufficient.
I made a test for that, and I didn't hit any random
bytes which can not be decoded after I've tested 100,000,000.
(with previous hardening patch)
since the number of the combination is 2^128 (MAX_INSN_SIZE is 16),
too huge to check all of them. Of course, the real number of
possible combination should be smaller than that.
- Because this decoder don't evaluate but just decode,
we can skip immediates and operands.
- If we hit the non-oprand opcode, mod/rm, sib, or displacement
in the middle of byte stream, we can stop trying decode tail bytes.
So I think there is smarter way to cover all possible combination
for the decoder than feeding random bytes.
Anyway, the decoder code can evolve in the future, I think it
should be put into the linux kernel.
Thank you,
--
Masami HIRAMATSU
Software Platform Research Dept. Linux Technology Center
Hitachi, Ltd., Yokohama Research Laboratory
E-mail: masami.hiramatsu.pt@hitachi.com
next prev parent reply other threads:[~2011-10-11 12:59 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-06 14:49 [PATCH 00/12] perf_events: add support for sampling taken branches Stephane Eranian
2011-10-06 14:49 ` [PATCH 01/12] perf_events: add generic taken branch sampling support Stephane Eranian
2011-10-06 16:57 ` Peter Zijlstra
2011-10-07 10:28 ` Stephane Eranian
2011-10-07 10:32 ` Peter Zijlstra
2011-10-07 10:44 ` Stephane Eranian
2011-10-06 17:01 ` Peter Zijlstra
2011-10-06 14:49 ` [PATCH 02/12] perf_events: add Intel LBR MSR definitions Stephane Eranian
2011-10-06 14:49 ` [PATCH 03/12] perf_events: add Intel X86 LBR sharing logic Stephane Eranian
2011-10-06 14:49 ` [PATCH 04/12] perf_events: sync branch stack sampling with X86 precise_sampling Stephane Eranian
2011-10-06 17:25 ` Peter Zijlstra
2011-10-07 10:34 ` Stephane Eranian
2011-10-07 10:37 ` Peter Zijlstra
2011-10-06 14:49 ` [PATCH 05/12] perf_events: add LBR mappings for PERF_SAMPLE_BRANCH filters Stephane Eranian
2011-10-06 14:49 ` [PATCH 06/12] perf_events: implement PERF_SAMPLE_BRANCH for Intel X86 Stephane Eranian
2011-10-06 17:54 ` Peter Zijlstra
2011-10-06 18:05 ` Peter Zijlstra
2011-10-06 14:49 ` [PATCH 07/12] perf_events: add LBR software filter support " Stephane Eranian
2011-10-06 15:32 ` Andi Kleen
2011-10-06 16:43 ` Peter Zijlstra
2011-10-06 17:14 ` Andi Kleen
2011-10-10 6:08 ` Ingo Molnar
2011-10-10 9:39 ` Peter Zijlstra
2011-10-07 7:06 ` Masami Hiramatsu
2011-10-07 10:38 ` Stephane Eranian
2011-10-07 10:40 ` Stephane Eranian
2011-10-07 10:42 ` Peter Zijlstra
2011-10-07 10:49 ` Stephane Eranian
2011-10-07 11:18 ` Peter Zijlstra
2011-10-07 11:21 ` Peter Zijlstra
2011-10-07 11:54 ` Masami Hiramatsu
2011-10-07 13:31 ` [PATCH] x86: Fix insn decoder for longer instruction Masami Hiramatsu
2011-10-10 7:04 ` Ingo Molnar
2011-10-10 6:09 ` [PATCH 07/12] perf_events: add LBR software filter support for Intel X86 Ingo Molnar
2011-10-10 14:05 ` Masami Hiramatsu
2011-10-10 14:45 ` Andi Kleen
2011-10-11 12:59 ` Masami Hiramatsu [this message]
2011-10-12 7:06 ` Ingo Molnar
2011-10-13 10:54 ` Masami Hiramatsu
2011-10-13 11:01 ` [RFC PATCH] x86: Add a sanity test of x86 decoder Masami Hiramatsu
2011-10-18 6:54 ` Ingo Molnar
2011-10-19 4:29 ` Masami Hiramatsu
2011-10-19 6:44 ` Ingo Molnar
2011-10-20 14:01 ` [RFC PATCH v2 1/2] " Masami Hiramatsu
2011-11-18 23:16 ` [tip:perf/core] x86, perf: Add a build-time sanity test to the " tip-bot for Masami Hiramatsu
2011-10-20 14:01 ` [RFC PATCH v2 2/2] [RESEND] x86: Fix insn decoder for longer instruction Masami Hiramatsu
2011-10-07 15:42 ` [PATCH 07/12] perf_events: add LBR software filter support for Intel X86 Andi Kleen
2011-10-07 11:25 ` Masami Hiramatsu
2011-10-07 11:40 ` Peter Zijlstra
2011-10-07 15:44 ` Andi Kleen
2011-10-07 15:09 ` Andi Kleen
2011-10-07 16:05 ` Peter Zijlstra
2011-10-06 14:49 ` [PATCH 08/12] perf_events: disable PERF_SAMPLE_BRANCH_* when not supported Stephane Eranian
2011-10-06 18:53 ` Peter Zijlstra
2011-10-06 14:49 ` [PATCH 09/12] perf_events: add hook to flush branch_stack on context switch Stephane Eranian
2011-10-06 14:49 ` [PATCH 10/12] perf: add code to support PERF_SAMPLE_BRANCH_STACK Stephane Eranian
2011-10-06 18:50 ` Peter Zijlstra
2011-10-07 10:25 ` Stephane Eranian
2011-10-07 10:27 ` Peter Zijlstra
2011-10-06 14:49 ` [PATCH 11/12] perf: add support for sampling taken branch to perf record Stephane Eranian
2011-10-06 14:49 ` [PATCH 12/12] perf: add support for taken branch sampling to perf report Stephane Eranian
2011-10-06 15:25 ` [PATCH 00/12] perf_events: add support for sampling taken branches Andi Kleen
2011-10-07 10:23 ` Stephane Eranian
2011-10-06 18:32 ` Peter Zijlstra
2011-10-06 21:41 ` Stephane Eranian
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