Re: [PATCH v1 3/3] iommu/amd: Dynamically verify Southbridge IOAPIC via PCI config space

[Vasant Hegde <vasant.hegde@amd.com>]

On 4/6/2026 9:10 PM, Wei Wang wrote:
> check_ioapic_information() verifies whether the BIOS has provided a valid
> device ID for the Southbridge (SB) IOAPIC in the IVRS table. Currently,
> if the SB IOAPIC entry in the IVRS table does not match a historically
> hardcoded device ID (00:14.0), interrupt remapping is forcibly disabled.
> 
> This hardcoded expectation does not scale to newer architectures. For
> example, recent Hygon Gen 4 servers use 00:0b.0 for the SB IOAPIC,
> causing the validation to fail and interrupt remapping to be permanently
> disabled on these systems.
> 
> Because the SB IOAPIC is embedded within the FCH (Fusion Controller Hub)
> and shares its device ID, we can inspect the PCI class code of the given
> device ID to confirm it is an actual FCH device, which is typically
> exposed as an SMBus controller function. The PCI class code at a given BDF
> is a stable, specification-defined property. Using it to identify an FCH
> function avoids maintaining per-vendor/per-generation hardcoded device IDs
> that must be updated for new platforms, while producing the same safe
> fallback (IR disabled) if the check ever fails.
> 
> Signed-off-by: Wei Wang <wei.w.wang@hotmail.com>


Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>


-Vasant