* [PATCH V10 0/7]Add EPSS L3 provider support on SA8775P SoC
@ 2025-03-24 18:31 Raviteja Laggyshetty
2025-03-24 18:31 ` [PATCH V10 1/7] dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P Raviteja Laggyshetty
` (6 more replies)
0 siblings, 7 replies; 14+ messages in thread
From: Raviteja Laggyshetty @ 2025-03-24 18:31 UTC (permalink / raw)
To: Georgi Djakov, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio, Raviteja Laggyshetty,
Odelu Kukatla, Mike Tipton, Jagadeesh Kona
Cc: Jeff Johnson, Sibi Sankar, linux-arm-msm, linux-pm, devicetree,
linux-kernel
Add Epoch Subsystem (EPSS) L3 provider support on SA8775P SoCs.
Current interconnect framework is based on static IDs for creating node
and registering with framework. This becomes a limitation for topologies
where there are multiple instances of same interconnect provider.
Modified interconnect framework APIs to create and link icc node with
dynamic IDs, this will help to overcome the dependency on static IDs.
Change since v9:
- Renamed macro ALLOC_DYN_ID to ICC_ALLOC_DYN_ID.
- Added APIs icc_node_create_dyn() and icc_link_nodes() for node
creation with dynamic ID allocation and linking.
- To optimize the memory, declared the link nodes as double pointer
"struct qcom_icc_node **link_nodes" instead of array of pointers
"struct qcom_icc_node *link_nodes[MAX_LINKS]".
- Added struct icc_node as member in struct qcom_icc_node to help in
tracking the node creation and avoid duplicates.
Change since v8:
- Moved the macro ALLOC_DYN_ID to interconnect.h header.
- Declared back the array of pointers and global structs as const in
L3 driver.
- Separated node creation and node linking in EPSS L3 driver probe,
cleaned up unused variables id, links and num_links.
- Dropped the opp labels for CPU OPP entries and used
(clockrate * buswidth) convention as per review comments.
Change since v7:
- Updated interconnect framework APIs icc_node_create() and
icc_link_create() to dynamically allocate IDs for interconnect nodes
during creation.
- Moved naming conventions to the framework and replaced snprintf() with
devm_kasprintf() as suggested.
- Updated the icc-rpmh driver and SA8775P SoC provider driver to support
dynamic ID allocation.
- Revised commit text to explain the use of the existing generic
compatible "qcom,epss-l3".
- Addressed other comments regarding the alphabetical ordering of
compatible properties.
Change since v6:
- Added icc_node_create_alloc_id() API to dynamically allocate ID while
creating the node. Replaced the IDA (ID allocator) with
icc_node_create_alloc_id() API to allocate node IDs dynamically.
- Removed qcom,epss-l3-perf generic compatible as per the comment.
- Added L3 ICC handles for CPU0 and CPU4 in DT, as per Bjorn comment.
Link to comment:
https://lore.kernel.org/lkml/ww3t3tu7p36qzlhcetaxif2xzrpgslydmuqo3fqvisbuar4bjh@qc2u43dck3qi/
Change since v5:
- Reused qcom,sm8250-epss-l3 compatible for sa8775p SoC.
- Rearranged the patches, moved dt changes to end of series.
- Updated the commit text.
Changes since v4:
- Added generic compatible "qcom,epss-l3-perf" and split the driver
changes accordingly.
Changes since v3:
- Removed epss-l3-perf generic compatible changes. These will be posted
as separate patch until then SoC specific compatible will be used for
probing.
Changes since v2:
- Updated the commit text to reflect the reason for code change.
- Added SoC-specific and generic compatible to driver match table.
Changes since v1:
- Removed the usage of static IDs and implemented dynamic ID assignment
for icc nodes using IDA.
- Removed separate compatibles for cl0 and cl1. Both cl0 and cl1
devices use the same compatible.
- Added new generic compatible for epss-l3-perf.
Jagadeesh Kona (1):
arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
Raviteja Laggyshetty (6):
dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P
interconnect: core: Add dynamic id allocation support
interconnect: qcom: Add multidev EPSS L3 support
interconnect: qcom: icc-rpmh: Add dynamic icc node id support
interconnect: qcom: sa8775p: Add dynamic icc node id support
arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider
.../bindings/interconnect/qcom,osm-l3.yaml | 1 +
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 229 +++++
drivers/interconnect/core.c | 83 +-
drivers/interconnect/qcom/icc-rpmh.c | 17 +-
drivers/interconnect/qcom/icc-rpmh.h | 5 +
drivers/interconnect/qcom/osm-l3.c | 36 +-
drivers/interconnect/qcom/sa8775p.c | 952 +++++++-----------
include/linux/interconnect-provider.h | 12 +
include/linux/interconnect.h | 3 +
9 files changed, 705 insertions(+), 633 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH V10 1/7] dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P
2025-03-24 18:31 [PATCH V10 0/7]Add EPSS L3 provider support on SA8775P SoC Raviteja Laggyshetty
@ 2025-03-24 18:31 ` Raviteja Laggyshetty
2025-03-24 18:31 ` [PATCH V10 2/7] interconnect: core: Add dynamic id allocation support Raviteja Laggyshetty
` (5 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Raviteja Laggyshetty @ 2025-03-24 18:31 UTC (permalink / raw)
To: Georgi Djakov, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio, Raviteja Laggyshetty,
Odelu Kukatla, Mike Tipton, Jagadeesh Kona
Cc: Jeff Johnson, Sibi Sankar, linux-arm-msm, linux-pm, devicetree,
linux-kernel, Krzysztof Kozlowski
Add Epoch Subsystem (EPSS) L3 interconnect provider binding on
SA8775P SoCs.
The L3 instance on the SA8775P SoC is similar to those on SoCs
like SM8250 and SC7280. These SoCs use the PERF register instead
of L3_REG for programming the performance level, which is managed
in the data associated with the target-specific compatibles.
Since the hardware remains the same across all EPSS-supporting SoCs,
the generic compatible is retained for all SoCs.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
---
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
index 4ac0863205b3..cd4bb912e0dc 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -28,6 +28,7 @@ properties:
- const: qcom,osm-l3
- items:
- enum:
+ - qcom,sa8775p-epss-l3
- qcom,sc7280-epss-l3
- qcom,sc8280xp-epss-l3
- qcom,sm6375-cpucp-l3
--
2.43.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH V10 2/7] interconnect: core: Add dynamic id allocation support
2025-03-24 18:31 [PATCH V10 0/7]Add EPSS L3 provider support on SA8775P SoC Raviteja Laggyshetty
2025-03-24 18:31 ` [PATCH V10 1/7] dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P Raviteja Laggyshetty
@ 2025-03-24 18:31 ` Raviteja Laggyshetty
2025-04-14 9:57 ` Georgi Djakov
2025-03-24 18:31 ` [PATCH V10 3/7] interconnect: qcom: Add multidev EPSS L3 support Raviteja Laggyshetty
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Raviteja Laggyshetty @ 2025-03-24 18:31 UTC (permalink / raw)
To: Georgi Djakov, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio, Raviteja Laggyshetty,
Odelu Kukatla, Mike Tipton, Jagadeesh Kona
Cc: Jeff Johnson, Sibi Sankar, linux-arm-msm, linux-pm, devicetree,
linux-kernel
The current interconnect framework relies on static IDs for node
creation and registration, which limits topologies with multiple
instances of the same interconnect provider. To address this,
introduce icc_node_create_dyn() and icc_link_nodes() APIs to
dynamically allocate IDs for interconnect nodes during creation
and link. This change removes the dependency on static IDs,
allowing multiple instances of the same hardware, such as EPSS L3.
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
---
drivers/interconnect/core.c | 83 ++++++++++++++++++++++++++-
include/linux/interconnect-provider.h | 12 ++++
include/linux/interconnect.h | 3 +
3 files changed, 97 insertions(+), 1 deletion(-)
diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c
index 9d5404a07e8a..d4c40c2b3ec1 100644
--- a/drivers/interconnect/core.c
+++ b/drivers/interconnect/core.c
@@ -20,6 +20,8 @@
#include "internal.h"
+#define ICC_DYN_ID_START 10000
+
#define CREATE_TRACE_POINTS
#include "trace.h"
@@ -826,7 +828,12 @@ static struct icc_node *icc_node_create_nolock(int id)
if (!node)
return ERR_PTR(-ENOMEM);
- id = idr_alloc(&icc_idr, node, id, id + 1, GFP_KERNEL);
+ /* dynamic id allocation */
+ if (id == ICC_ALLOC_DYN_ID)
+ id = idr_alloc(&icc_idr, node, ICC_DYN_ID_START, 0, GFP_KERNEL);
+ else
+ id = idr_alloc(&icc_idr, node, id, id + 1, GFP_KERNEL);
+
if (id < 0) {
WARN(1, "%s: couldn't get idr\n", __func__);
kfree(node);
@@ -838,6 +845,26 @@ static struct icc_node *icc_node_create_nolock(int id)
return node;
}
+/**
+ * icc_node_create_dyn() - create a node with dynamic id
+ * @id: node id
+ *
+ * Return: icc_node pointer on success, or ERR_PTR() on error
+ */
+struct icc_node *icc_node_create_dyn(void)
+{
+ struct icc_node *node;
+
+ mutex_lock(&icc_lock);
+
+ node = icc_node_create_nolock(ICC_ALLOC_DYN_ID);
+
+ mutex_unlock(&icc_lock);
+
+ return node;
+}
+EXPORT_SYMBOL_GPL(icc_node_create_dyn);
+
/**
* icc_node_create() - create a node
* @id: node id
@@ -884,6 +911,56 @@ void icc_node_destroy(int id)
}
EXPORT_SYMBOL_GPL(icc_node_destroy);
+/**
+ * icc_link_nodes() - create link between two nodes
+ * @src_node: source node
+ * @dst_node: destination node
+ *
+ * Create a link between two nodes. The nodes might belong to different
+ * interconnect providers and the @dst_node might not exist (if the
+ * provider driver has not probed yet). So just create the @dst_node
+ * and when the actual provider driver is probed, the rest of the node
+ * data is filled.
+ *
+ * Return: 0 on success, or an error code otherwise
+ */
+int icc_link_nodes(struct icc_node *src_node, struct icc_node **dst_node)
+{
+ struct icc_node **new;
+ int ret = 0;
+
+ if (!src_node->provider)
+ return -EINVAL;
+
+ mutex_lock(&icc_lock);
+
+ if (!*dst_node) {
+ *dst_node = icc_node_create_nolock(ICC_ALLOC_DYN_ID);
+
+ if (IS_ERR(*dst_node)) {
+ ret = PTR_ERR(*dst_node);
+ goto out;
+ }
+ }
+
+ new = krealloc(src_node->links,
+ (src_node->num_links + 1) * sizeof(*src_node->links),
+ GFP_KERNEL);
+ if (!new) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ src_node->links = new;
+ src_node->links[src_node->num_links++] = *dst_node;
+
+out:
+ mutex_unlock(&icc_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(icc_link_nodes);
+
/**
* icc_link_create() - create a link between two nodes
* @node: source node id
@@ -962,6 +1039,10 @@ void icc_node_add(struct icc_node *node, struct icc_provider *provider)
node->avg_bw = node->init_avg;
node->peak_bw = node->init_peak;
+ if (node->id >= ICC_DYN_ID_START)
+ node->name = devm_kasprintf(provider->dev, GFP_KERNEL, "%s@%s",
+ node->name, dev_name(provider->dev));
+
if (node->avg_bw || node->peak_bw) {
if (provider->pre_aggregate)
provider->pre_aggregate(node);
diff --git a/include/linux/interconnect-provider.h b/include/linux/interconnect-provider.h
index f5aef8784692..55cfebc658e6 100644
--- a/include/linux/interconnect-provider.h
+++ b/include/linux/interconnect-provider.h
@@ -116,8 +116,10 @@ struct icc_node {
int icc_std_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
+struct icc_node *icc_node_create_dyn(void);
struct icc_node *icc_node_create(int id);
void icc_node_destroy(int id);
+int icc_link_nodes(struct icc_node *src_node, struct icc_node **dst_node);
int icc_link_create(struct icc_node *node, const int dst_id);
void icc_node_add(struct icc_node *node, struct icc_provider *provider);
void icc_node_del(struct icc_node *node);
@@ -136,6 +138,11 @@ static inline int icc_std_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
return -ENOTSUPP;
}
+static inline struct icc_node *icc_node_create_dyn(void)
+{
+ return ERR_PTR(-EOPNOTSUPP);
+}
+
static inline struct icc_node *icc_node_create(int id)
{
return ERR_PTR(-ENOTSUPP);
@@ -145,6 +152,11 @@ static inline void icc_node_destroy(int id)
{
}
+static inline int icc_link_nodes(struct icc_node *src_node, struct icc_node **dst_node)
+{
+ return -EOPNOTSUPP;
+}
+
static inline int icc_link_create(struct icc_node *node, const int dst_id)
{
return -ENOTSUPP;
diff --git a/include/linux/interconnect.h b/include/linux/interconnect.h
index 97ac253df62c..e4b8808823ad 100644
--- a/include/linux/interconnect.h
+++ b/include/linux/interconnect.h
@@ -20,6 +20,9 @@
#define Mbps_to_icc(x) ((x) * 1000 / 8)
#define Gbps_to_icc(x) ((x) * 1000 * 1000 / 8)
+/* macro to indicate dynamic id allocation */
+#define ICC_ALLOC_DYN_ID -1
+
struct icc_path;
struct device;
--
2.43.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH V10 3/7] interconnect: qcom: Add multidev EPSS L3 support
2025-03-24 18:31 [PATCH V10 0/7]Add EPSS L3 provider support on SA8775P SoC Raviteja Laggyshetty
2025-03-24 18:31 ` [PATCH V10 1/7] dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P Raviteja Laggyshetty
2025-03-24 18:31 ` [PATCH V10 2/7] interconnect: core: Add dynamic id allocation support Raviteja Laggyshetty
@ 2025-03-24 18:31 ` Raviteja Laggyshetty
2025-04-14 9:58 ` Georgi Djakov
2025-03-24 18:32 ` [PATCH V10 4/7] interconnect: qcom: icc-rpmh: Add dynamic icc node id support Raviteja Laggyshetty
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Raviteja Laggyshetty @ 2025-03-24 18:31 UTC (permalink / raw)
To: Georgi Djakov, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio, Raviteja Laggyshetty,
Odelu Kukatla, Mike Tipton, Jagadeesh Kona
Cc: Jeff Johnson, Sibi Sankar, linux-arm-msm, linux-pm, devicetree,
linux-kernel
EPSS on SA8775P has two instances, necessitating the creation of two
device nodes with different compatibles due to the unique ICC node ID
and name limitations in the interconnect framework. Add multidevice
support for the OSM-L3 provider to dynamically obtain unique node IDs
and register with the framework.
EPSS topology includes a single master-slave pair within the same
provider, the node linking logic is simplified by directly connecting
the master node to the slave node.
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
---
drivers/interconnect/qcom/osm-l3.c | 36 ++++++++++--------------------
1 file changed, 12 insertions(+), 24 deletions(-)
diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
index 6a656ed44d49..43e67d2116b9 100644
--- a/drivers/interconnect/qcom/osm-l3.c
+++ b/drivers/interconnect/qcom/osm-l3.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/args.h>
@@ -48,16 +49,10 @@ struct qcom_osm_l3_icc_provider {
/**
* struct qcom_osm_l3_node - Qualcomm specific interconnect nodes
* @name: the node name used in debugfs
- * @links: an array of nodes where we can go next while traversing
- * @id: a unique node identifier
- * @num_links: the total number of @links
* @buswidth: width of the interconnect between a node and the bus
*/
struct qcom_osm_l3_node {
const char *name;
- u16 links[OSM_L3_MAX_LINKS];
- u16 id;
- u16 num_links;
u16 buswidth;
};
@@ -69,30 +64,22 @@ struct qcom_osm_l3_desc {
unsigned int reg_perf_state;
};
-enum {
- OSM_L3_MASTER_NODE = 10000,
- OSM_L3_SLAVE_NODE,
-};
-
-#define DEFINE_QNODE(_name, _id, _buswidth, ...) \
+#define DEFINE_QNODE(_name, _buswidth) \
static const struct qcom_osm_l3_node _name = { \
.name = #_name, \
- .id = _id, \
.buswidth = _buswidth, \
- .num_links = COUNT_ARGS(__VA_ARGS__), \
- .links = { __VA_ARGS__ }, \
}
-DEFINE_QNODE(osm_l3_master, OSM_L3_MASTER_NODE, 16, OSM_L3_SLAVE_NODE);
-DEFINE_QNODE(osm_l3_slave, OSM_L3_SLAVE_NODE, 16);
+DEFINE_QNODE(osm_l3_slave, 16);
+DEFINE_QNODE(osm_l3_master, 16);
static const struct qcom_osm_l3_node * const osm_l3_nodes[] = {
[MASTER_OSM_L3_APPS] = &osm_l3_master,
[SLAVE_OSM_L3] = &osm_l3_slave,
};
-DEFINE_QNODE(epss_l3_master, OSM_L3_MASTER_NODE, 32, OSM_L3_SLAVE_NODE);
-DEFINE_QNODE(epss_l3_slave, OSM_L3_SLAVE_NODE, 32);
+DEFINE_QNODE(epss_l3_slave, 32);
+DEFINE_QNODE(epss_l3_master, 32);
static const struct qcom_osm_l3_node * const epss_l3_nodes[] = {
[MASTER_EPSS_L3_APPS] = &epss_l3_master,
@@ -242,10 +229,10 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
icc_provider_init(provider);
+ /* Create nodes */
for (i = 0; i < num_nodes; i++) {
- size_t j;
+ node = icc_node_create_dyn();
- node = icc_node_create(qnodes[i]->id);
if (IS_ERR(node)) {
ret = PTR_ERR(node);
goto err;
@@ -256,12 +243,12 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
node->data = (void *)qnodes[i];
icc_node_add(node, provider);
- for (j = 0; j < qnodes[i]->num_links; j++)
- icc_link_create(node, qnodes[i]->links[j]);
-
data->nodes[i] = node;
}
+ /* Create link */
+ icc_link_nodes(data->nodes[MASTER_OSM_L3_APPS], &data->nodes[SLAVE_OSM_L3]);
+
ret = icc_provider_register(provider);
if (ret)
goto err;
@@ -278,6 +265,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
static const struct of_device_id osm_l3_of_match[] = {
{ .compatible = "qcom,epss-l3", .data = &epss_l3_l3_vote },
{ .compatible = "qcom,osm-l3", .data = &osm_l3 },
+ { .compatible = "qcom,sa8775p-epss-l3", .data = &epss_l3_perf_state },
{ .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 },
{ .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state },
{ .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 },
--
2.43.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH V10 4/7] interconnect: qcom: icc-rpmh: Add dynamic icc node id support
2025-03-24 18:31 [PATCH V10 0/7]Add EPSS L3 provider support on SA8775P SoC Raviteja Laggyshetty
` (2 preceding siblings ...)
2025-03-24 18:31 ` [PATCH V10 3/7] interconnect: qcom: Add multidev EPSS L3 support Raviteja Laggyshetty
@ 2025-03-24 18:32 ` Raviteja Laggyshetty
2025-03-26 17:41 ` Dmitry Baryshkov
2025-03-24 18:32 ` [PATCH V10 5/7] interconnect: qcom: sa8775p: " Raviteja Laggyshetty
` (2 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Raviteja Laggyshetty @ 2025-03-24 18:32 UTC (permalink / raw)
To: Georgi Djakov, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio, Raviteja Laggyshetty,
Odelu Kukatla, Mike Tipton, Jagadeesh Kona
Cc: Jeff Johnson, Sibi Sankar, linux-arm-msm, linux-pm, devicetree,
linux-kernel
Interconnect framework relies on static IDs for creating,
linking and maintaning the topology. This dependency on static
IDs prevents creating two instances of same provider. To overcome
the dependency on static IDs, dynamic ID support is being added.
To facilitate dynamic node ID support, the driver now uses
node pointers for links instead of static node IDs and icc_node
pointer is added as member in qcom_icc_node structure to track
the node creation.
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
---
drivers/interconnect/qcom/icc-rpmh.c | 17 ++++++++++++++---
drivers/interconnect/qcom/icc-rpmh.h | 5 +++++
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c
index f2d63745be54..41bfc6e7ee1d 100644
--- a/drivers/interconnect/qcom/icc-rpmh.c
+++ b/drivers/interconnect/qcom/icc-rpmh.c
@@ -280,7 +280,14 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
if (!qn)
continue;
- node = icc_node_create(qn->id);
+ if (desc->alloc_dyn_id) {
+ if (!qn->node)
+ qn->node = icc_node_create_dyn();
+ node = qn->node;
+ } else {
+ node = icc_node_create(qn->id);
+ }
+
if (IS_ERR(node)) {
ret = PTR_ERR(node);
goto err_remove_nodes;
@@ -290,8 +297,12 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
node->data = qn;
icc_node_add(node, provider);
- for (j = 0; j < qn->num_links; j++)
- icc_link_create(node, qn->links[j]);
+ for (j = 0; j < qn->num_links; j++) {
+ if (desc->alloc_dyn_id)
+ icc_link_nodes(node, &qn->link_nodes[j]->node);
+ else
+ icc_link_create(node, qn->links[j]);
+ }
data->nodes[i] = node;
}
diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h
index 82344c734091..bd8d730249b1 100644
--- a/drivers/interconnect/qcom/icc-rpmh.h
+++ b/drivers/interconnect/qcom/icc-rpmh.h
@@ -83,6 +83,8 @@ struct qcom_icc_qosbox {
* @name: the node name used in debugfs
* @links: an array of nodes where we can go next while traversing
* @id: a unique node identifier
+ * @link_nodes: links associated with this node
+ * @node: icc_node associated with this node
* @num_links: the total number of @links
* @channels: num of channels at this node
* @buswidth: width of the interconnect between a node and the bus
@@ -96,6 +98,8 @@ struct qcom_icc_node {
const char *name;
u16 links[MAX_LINKS];
u16 id;
+ struct qcom_icc_node **link_nodes;
+ struct icc_node *node;
u16 num_links;
u16 channels;
u16 buswidth;
@@ -154,6 +158,7 @@ struct qcom_icc_desc {
struct qcom_icc_bcm * const *bcms;
size_t num_bcms;
bool qos_requires_clocks;
+ bool alloc_dyn_id;
};
int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
--
2.43.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH V10 5/7] interconnect: qcom: sa8775p: Add dynamic icc node id support
2025-03-24 18:31 [PATCH V10 0/7]Add EPSS L3 provider support on SA8775P SoC Raviteja Laggyshetty
` (3 preceding siblings ...)
2025-03-24 18:32 ` [PATCH V10 4/7] interconnect: qcom: icc-rpmh: Add dynamic icc node id support Raviteja Laggyshetty
@ 2025-03-24 18:32 ` Raviteja Laggyshetty
2025-03-26 17:41 ` Dmitry Baryshkov
2025-03-24 18:32 ` [PATCH V10 6/7] arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider Raviteja Laggyshetty
2025-03-24 18:32 ` [PATCH V10 7/7] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3 Raviteja Laggyshetty
6 siblings, 1 reply; 14+ messages in thread
From: Raviteja Laggyshetty @ 2025-03-24 18:32 UTC (permalink / raw)
To: Georgi Djakov, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio, Raviteja Laggyshetty,
Odelu Kukatla, Mike Tipton, Jagadeesh Kona
Cc: Jeff Johnson, Sibi Sankar, linux-arm-msm, linux-pm, devicetree,
linux-kernel
To facilitate dynamic id allocation, discard the static IDs
from node data and set alloc_dyn_id in descriptor structure
to indicate dynamic ID allocation. Update the topology to use
node pointers for links instead of static IDs and forward declare
the node pointer to avoid undefined references.
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
---
drivers/interconnect/qcom/sa8775p.c | 952 ++++++++++------------------
1 file changed, 347 insertions(+), 605 deletions(-)
diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c
index e2826af3ea2e..04b4abbf4487 100644
--- a/drivers/interconnect/qcom/sa8775p.c
+++ b/drivers/interconnect/qcom/sa8775p.c
@@ -15,1859 +15,1587 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#define SA8775P_MASTER_GPU_TCU 0
-#define SA8775P_MASTER_PCIE_TCU 1
-#define SA8775P_MASTER_SYS_TCU 2
-#define SA8775P_MASTER_APPSS_PROC 3
-#define SA8775P_MASTER_LLCC 4
-#define SA8775P_MASTER_CNOC_LPASS_AG_NOC 5
-#define SA8775P_MASTER_GIC_AHB 6
-#define SA8775P_MASTER_CDSP_NOC_CFG 7
-#define SA8775P_MASTER_CDSPB_NOC_CFG 8
-#define SA8775P_MASTER_QDSS_BAM 9
-#define SA8775P_MASTER_QUP_0 10
-#define SA8775P_MASTER_QUP_1 11
-#define SA8775P_MASTER_QUP_2 12
-#define SA8775P_MASTER_A1NOC_SNOC 13
-#define SA8775P_MASTER_A2NOC_SNOC 14
-#define SA8775P_MASTER_CAMNOC_HF 15
-#define SA8775P_MASTER_CAMNOC_ICP 16
-#define SA8775P_MASTER_CAMNOC_SF 17
-#define SA8775P_MASTER_COMPUTE_NOC 18
-#define SA8775P_MASTER_COMPUTE_NOC_1 19
-#define SA8775P_MASTER_CNOC_A2NOC 20
-#define SA8775P_MASTER_CNOC_DC_NOC 21
-#define SA8775P_MASTER_GEM_NOC_CFG 22
-#define SA8775P_MASTER_GEM_NOC_CNOC 23
-#define SA8775P_MASTER_GEM_NOC_PCIE_SNOC 24
-#define SA8775P_MASTER_GPDSP_SAIL 25
-#define SA8775P_MASTER_GFX3D 26
-#define SA8775P_MASTER_LPASS_ANOC 27
-#define SA8775P_MASTER_MDP0 28
-#define SA8775P_MASTER_MDP1 29
-#define SA8775P_MASTER_MDP_CORE1_0 30
-#define SA8775P_MASTER_MDP_CORE1_1 31
-#define SA8775P_MASTER_MNOC_HF_MEM_NOC 32
-#define SA8775P_MASTER_CNOC_MNOC_HF_CFG 33
-#define SA8775P_MASTER_MNOC_SF_MEM_NOC 34
-#define SA8775P_MASTER_CNOC_MNOC_SF_CFG 35
-#define SA8775P_MASTER_ANOC_PCIE_GEM_NOC 36
-#define SA8775P_MASTER_SNOC_CFG 37
-#define SA8775P_MASTER_SNOC_GC_MEM_NOC 38
-#define SA8775P_MASTER_SNOC_SF_MEM_NOC 39
-#define SA8775P_MASTER_VIDEO_P0 40
-#define SA8775P_MASTER_VIDEO_P1 41
-#define SA8775P_MASTER_VIDEO_PROC 42
-#define SA8775P_MASTER_VIDEO_V_PROC 43
-#define SA8775P_MASTER_QUP_CORE_0 44
-#define SA8775P_MASTER_QUP_CORE_1 45
-#define SA8775P_MASTER_QUP_CORE_2 46
-#define SA8775P_MASTER_QUP_CORE_3 47
-#define SA8775P_MASTER_CRYPTO_CORE0 48
-#define SA8775P_MASTER_CRYPTO_CORE1 49
-#define SA8775P_MASTER_DSP0 50
-#define SA8775P_MASTER_DSP1 51
-#define SA8775P_MASTER_IPA 52
-#define SA8775P_MASTER_LPASS_PROC 53
-#define SA8775P_MASTER_CDSP_PROC 54
-#define SA8775P_MASTER_CDSP_PROC_B 55
-#define SA8775P_MASTER_PIMEM 56
-#define SA8775P_MASTER_QUP_3 57
-#define SA8775P_MASTER_EMAC 58
-#define SA8775P_MASTER_EMAC_1 59
-#define SA8775P_MASTER_GIC 60
-#define SA8775P_MASTER_PCIE_0 61
-#define SA8775P_MASTER_PCIE_1 62
-#define SA8775P_MASTER_QDSS_ETR_0 63
-#define SA8775P_MASTER_QDSS_ETR_1 64
-#define SA8775P_MASTER_SDC 65
-#define SA8775P_MASTER_UFS_CARD 66
-#define SA8775P_MASTER_UFS_MEM 67
-#define SA8775P_MASTER_USB2 68
-#define SA8775P_MASTER_USB3_0 69
-#define SA8775P_MASTER_USB3_1 70
-#define SA8775P_SLAVE_EBI1 512
-#define SA8775P_SLAVE_AHB2PHY_0 513
-#define SA8775P_SLAVE_AHB2PHY_1 514
-#define SA8775P_SLAVE_AHB2PHY_2 515
-#define SA8775P_SLAVE_AHB2PHY_3 516
-#define SA8775P_SLAVE_ANOC_THROTTLE_CFG 517
-#define SA8775P_SLAVE_AOSS 518
-#define SA8775P_SLAVE_APPSS 519
-#define SA8775P_SLAVE_BOOT_ROM 520
-#define SA8775P_SLAVE_CAMERA_CFG 521
-#define SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG 522
-#define SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG 523
-#define SA8775P_SLAVE_CLK_CTL 524
-#define SA8775P_SLAVE_CDSP_CFG 525
-#define SA8775P_SLAVE_CDSP1_CFG 526
-#define SA8775P_SLAVE_RBCPR_CX_CFG 527
-#define SA8775P_SLAVE_RBCPR_MMCX_CFG 528
-#define SA8775P_SLAVE_RBCPR_MX_CFG 529
-#define SA8775P_SLAVE_CPR_NSPCX 530
-#define SA8775P_SLAVE_CRYPTO_0_CFG 531
-#define SA8775P_SLAVE_CX_RDPM 532
-#define SA8775P_SLAVE_DISPLAY_CFG 533
-#define SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG 534
-#define SA8775P_SLAVE_DISPLAY1_CFG 535
-#define SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG 536
-#define SA8775P_SLAVE_EMAC_CFG 537
-#define SA8775P_SLAVE_EMAC1_CFG 538
-#define SA8775P_SLAVE_GP_DSP0_CFG 539
-#define SA8775P_SLAVE_GP_DSP1_CFG 540
-#define SA8775P_SLAVE_GPDSP0_THROTTLE_CFG 541
-#define SA8775P_SLAVE_GPDSP1_THROTTLE_CFG 542
-#define SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG 543
-#define SA8775P_SLAVE_GFX3D_CFG 544
-#define SA8775P_SLAVE_HWKM 545
-#define SA8775P_SLAVE_IMEM_CFG 546
-#define SA8775P_SLAVE_IPA_CFG 547
-#define SA8775P_SLAVE_IPC_ROUTER_CFG 548
-#define SA8775P_SLAVE_LLCC_CFG 549
-#define SA8775P_SLAVE_LPASS 550
-#define SA8775P_SLAVE_LPASS_CORE_CFG 551
-#define SA8775P_SLAVE_LPASS_LPI_CFG 552
-#define SA8775P_SLAVE_LPASS_MPU_CFG 553
-#define SA8775P_SLAVE_LPASS_THROTTLE_CFG 554
-#define SA8775P_SLAVE_LPASS_TOP_CFG 555
-#define SA8775P_SLAVE_MX_RDPM 556
-#define SA8775P_SLAVE_MXC_RDPM 557
-#define SA8775P_SLAVE_PCIE_0_CFG 558
-#define SA8775P_SLAVE_PCIE_1_CFG 559
-#define SA8775P_SLAVE_PCIE_RSC_CFG 560
-#define SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG 561
-#define SA8775P_SLAVE_PCIE_THROTTLE_CFG 562
-#define SA8775P_SLAVE_PDM 563
-#define SA8775P_SLAVE_PIMEM_CFG 564
-#define SA8775P_SLAVE_PKA_WRAPPER_CFG 565
-#define SA8775P_SLAVE_QDSS_CFG 566
-#define SA8775P_SLAVE_QM_CFG 567
-#define SA8775P_SLAVE_QM_MPU_CFG 568
-#define SA8775P_SLAVE_QUP_0 569
-#define SA8775P_SLAVE_QUP_1 570
-#define SA8775P_SLAVE_QUP_2 571
-#define SA8775P_SLAVE_QUP_3 572
-#define SA8775P_SLAVE_SAIL_THROTTLE_CFG 573
-#define SA8775P_SLAVE_SDC1 574
-#define SA8775P_SLAVE_SECURITY 575
-#define SA8775P_SLAVE_SNOC_THROTTLE_CFG 576
-#define SA8775P_SLAVE_TCSR 577
-#define SA8775P_SLAVE_TLMM 578
-#define SA8775P_SLAVE_TSC_CFG 579
-#define SA8775P_SLAVE_UFS_CARD_CFG 580
-#define SA8775P_SLAVE_UFS_MEM_CFG 581
-#define SA8775P_SLAVE_USB2 582
-#define SA8775P_SLAVE_USB3_0 583
-#define SA8775P_SLAVE_USB3_1 584
-#define SA8775P_SLAVE_VENUS_CFG 585
-#define SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG 586
-#define SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG 587
-#define SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG 588
-#define SA8775P_SLAVE_A1NOC_SNOC 589
-#define SA8775P_SLAVE_A2NOC_SNOC 590
-#define SA8775P_SLAVE_DDRSS_CFG 591
-#define SA8775P_SLAVE_GEM_NOC_CNOC 592
-#define SA8775P_SLAVE_GEM_NOC_CFG 593
-#define SA8775P_SLAVE_SNOC_GEM_NOC_GC 594
-#define SA8775P_SLAVE_SNOC_GEM_NOC_SF 595
-#define SA8775P_SLAVE_GP_DSP_SAIL_NOC 596
-#define SA8775P_SLAVE_GPDSP_NOC_CFG 597
-#define SA8775P_SLAVE_HCP_A 598
-#define SA8775P_SLAVE_LLCC 599
-#define SA8775P_SLAVE_MNOC_HF_MEM_NOC 600
-#define SA8775P_SLAVE_MNOC_SF_MEM_NOC 601
-#define SA8775P_SLAVE_CNOC_MNOC_HF_CFG 602
-#define SA8775P_SLAVE_CNOC_MNOC_SF_CFG 603
-#define SA8775P_SLAVE_CDSP_MEM_NOC 604
-#define SA8775P_SLAVE_CDSPB_MEM_NOC 605
-#define SA8775P_SLAVE_HCP_B 606
-#define SA8775P_SLAVE_GEM_NOC_PCIE_CNOC 607
-#define SA8775P_SLAVE_PCIE_ANOC_CFG 608
-#define SA8775P_SLAVE_ANOC_PCIE_GEM_NOC 609
-#define SA8775P_SLAVE_SNOC_CFG 610
-#define SA8775P_SLAVE_LPASS_SNOC 611
-#define SA8775P_SLAVE_QUP_CORE_0 612
-#define SA8775P_SLAVE_QUP_CORE_1 613
-#define SA8775P_SLAVE_QUP_CORE_2 614
-#define SA8775P_SLAVE_QUP_CORE_3 615
-#define SA8775P_SLAVE_BOOT_IMEM 616
-#define SA8775P_SLAVE_IMEM 617
-#define SA8775P_SLAVE_PIMEM 618
-#define SA8775P_SLAVE_SERVICE_NSP_NOC 619
-#define SA8775P_SLAVE_SERVICE_NSPB_NOC 620
-#define SA8775P_SLAVE_SERVICE_GEM_NOC_1 621
-#define SA8775P_SLAVE_SERVICE_MNOC_HF 622
-#define SA8775P_SLAVE_SERVICE_MNOC_SF 623
-#define SA8775P_SLAVE_SERVICES_LPASS_AML_NOC 624
-#define SA8775P_SLAVE_SERVICE_LPASS_AG_NOC 625
-#define SA8775P_SLAVE_SERVICE_GEM_NOC_2 626
-#define SA8775P_SLAVE_SERVICE_SNOC 627
-#define SA8775P_SLAVE_SERVICE_GEM_NOC 628
-#define SA8775P_SLAVE_SERVICE_GEM_NOC2 629
-#define SA8775P_SLAVE_PCIE_0 630
-#define SA8775P_SLAVE_PCIE_1 631
-#define SA8775P_SLAVE_QDSS_STM 632
-#define SA8775P_SLAVE_TCU 633
+static struct qcom_icc_node qxm_qup3;
+static struct qcom_icc_node xm_emac_0;
+static struct qcom_icc_node xm_emac_1;
+static struct qcom_icc_node xm_sdc1;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node xm_usb2_2;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node xm_usb3_1;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qup0;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node qhm_qup2;
+static struct qcom_icc_node qnm_cnoc_datapath;
+static struct qcom_icc_node qxm_crypto_0;
+static struct qcom_icc_node qxm_crypto_1;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node xm_qdss_etr_0;
+static struct qcom_icc_node xm_qdss_etr_1;
+static struct qcom_icc_node xm_ufs_card;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qup0_core_master;
+static struct qcom_icc_node qup1_core_master;
+static struct qcom_icc_node qup2_core_master;
+static struct qcom_icc_node qup3_core_master;
+static struct qcom_icc_node qup0_core_slave;
+static struct qcom_icc_node qup1_core_slave;
+static struct qcom_icc_node qup2_core_slave;
+static struct qcom_icc_node qup3_core_slave;
+static struct qcom_icc_node qnm_gemnoc_cnoc;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node qhs_ahb2phy0;
+static struct qcom_icc_node qhs_ahb2phy1;
+static struct qcom_icc_node qhs_ahb2phy2;
+static struct qcom_icc_node qhs_ahb2phy3;
+static struct qcom_icc_node qhs_anoc_throttle_cfg;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qhs_boot_rom;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_camera_nrt_throttle_cfg;
+static struct qcom_icc_node qhs_camera_rt_throttle_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_compute0_cfg;
+static struct qcom_icc_node qhs_compute1_cfg;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mmcx;
+static struct qcom_icc_node qhs_cpr_mx;
+static struct qcom_icc_node qhs_cpr_nspcx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_cx_rdpm;
+static struct qcom_icc_node qhs_display0_cfg;
+static struct qcom_icc_node qhs_display0_rt_throttle_cfg;
+static struct qcom_icc_node qhs_display1_cfg;
+static struct qcom_icc_node qhs_display1_rt_throttle_cfg;
+static struct qcom_icc_node qhs_emac0_cfg;
+static struct qcom_icc_node qhs_emac1_cfg;
+static struct qcom_icc_node qhs_gp_dsp0_cfg;
+static struct qcom_icc_node qhs_gp_dsp1_cfg;
+static struct qcom_icc_node qhs_gpdsp0_throttle_cfg;
+static struct qcom_icc_node qhs_gpdsp1_throttle_cfg;
+static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_hwkm;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_ipc_router;
+static struct qcom_icc_node qhs_lpass_cfg;
+static struct qcom_icc_node qhs_lpass_throttle_cfg;
+static struct qcom_icc_node qhs_mx_rdpm;
+static struct qcom_icc_node qhs_mxc_rdpm;
+static struct qcom_icc_node qhs_pcie0_cfg;
+static struct qcom_icc_node qhs_pcie1_cfg;
+static struct qcom_icc_node qhs_pcie_rsc_cfg;
+static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg;
+static struct qcom_icc_node qhs_pcie_throttle_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_pke_wrapper_cfg;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qm_cfg;
+static struct qcom_icc_node qhs_qm_mpu_cfg;
+static struct qcom_icc_node qhs_qup0;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_qup2;
+static struct qcom_icc_node qhs_qup3;
+static struct qcom_icc_node qhs_sail_throttle_cfg;
+static struct qcom_icc_node qhs_sdc1;
+static struct qcom_icc_node qhs_security;
+static struct qcom_icc_node qhs_snoc_throttle_cfg;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_tsc_cfg;
+static struct qcom_icc_node qhs_ufs_card_cfg;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb2_0;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_usb3_1;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_venus_cvp_throttle_cfg;
+static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg;
+static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg;
+static struct qcom_icc_node qns_ddrss_cfg;
+static struct qcom_icc_node qns_gpdsp_noc_cfg;
+static struct qcom_icc_node qns_mnoc_hf_cfg;
+static struct qcom_icc_node qns_mnoc_sf_cfg;
+static struct qcom_icc_node qns_pcie_anoc_cfg;
+static struct qcom_icc_node qns_snoc_cfg;
+static struct qcom_icc_node qxs_boot_imem;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node xs_pcie_0;
+static struct qcom_icc_node xs_pcie_1;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
+static struct qcom_icc_node qnm_cnoc_dc_noc;
+static struct qcom_icc_node qhs_llcc;
+static struct qcom_icc_node qns_gemnoc;
+static struct qcom_icc_node alm_gpu_tcu;
+static struct qcom_icc_node alm_pcie_tcu;
+static struct qcom_icc_node alm_sys_tcu;
+static struct qcom_icc_node chm_apps;
+static struct qcom_icc_node qnm_cmpnoc0;
+static struct qcom_icc_node qnm_cmpnoc1;
+static struct qcom_icc_node qnm_gemnoc_cfg;
+static struct qcom_icc_node qnm_gpdsp_sail;
+static struct qcom_icc_node qnm_gpu;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qns_gem_noc_cnoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_pcie;
+static struct qcom_icc_node srvc_even_gemnoc;
+static struct qcom_icc_node srvc_odd_gemnoc;
+static struct qcom_icc_node srvc_sys_gemnoc;
+static struct qcom_icc_node srvc_sys_gemnoc_2;
+static struct qcom_icc_node qxm_dsp0;
+static struct qcom_icc_node qxm_dsp1;
+static struct qcom_icc_node qns_gp_dsp_sail_noc;
+static struct qcom_icc_node qhm_config_noc;
+static struct qcom_icc_node qxm_lpass_dsp;
+static struct qcom_icc_node qhs_lpass_core;
+static struct qcom_icc_node qhs_lpass_lpi;
+static struct qcom_icc_node qhs_lpass_mpu;
+static struct qcom_icc_node qhs_lpass_top;
+static struct qcom_icc_node qns_sysnoc;
+static struct qcom_icc_node srvc_niu_aml_noc;
+static struct qcom_icc_node srvc_niu_lpass_agnoc;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qnm_camnoc_hf;
+static struct qcom_icc_node qnm_camnoc_icp;
+static struct qcom_icc_node qnm_camnoc_sf;
+static struct qcom_icc_node qnm_mdp0_0;
+static struct qcom_icc_node qnm_mdp0_1;
+static struct qcom_icc_node qnm_mdp1_0;
+static struct qcom_icc_node qnm_mdp1_1;
+static struct qcom_icc_node qnm_mnoc_hf_cfg;
+static struct qcom_icc_node qnm_mnoc_sf_cfg;
+static struct qcom_icc_node qnm_video0;
+static struct qcom_icc_node qnm_video1;
+static struct qcom_icc_node qnm_video_cvp;
+static struct qcom_icc_node qnm_video_v_cpu;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node qns_mem_noc_sf;
+static struct qcom_icc_node srvc_mnoc_hf;
+static struct qcom_icc_node srvc_mnoc_sf;
+static struct qcom_icc_node qhm_nsp_noc_config;
+static struct qcom_icc_node qxm_nsp;
+static struct qcom_icc_node qns_hcp;
+static struct qcom_icc_node qns_nsp_gemnoc;
+static struct qcom_icc_node service_nsp_noc;
+static struct qcom_icc_node qhm_nspb_noc_config;
+static struct qcom_icc_node qxm_nspb;
+static struct qcom_icc_node qns_nspb_gemnoc;
+static struct qcom_icc_node qns_nspb_hcp;
+static struct qcom_icc_node service_nspb_noc;
+static struct qcom_icc_node xm_pcie3_0;
+static struct qcom_icc_node xm_pcie3_1;
+static struct qcom_icc_node qns_pcie_mem_noc;
+static struct qcom_icc_node qhm_gic;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_lpass_noc;
+static struct qcom_icc_node qnm_snoc_cfg;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node srvc_snoc;
static struct qcom_icc_node qxm_qup3 = {
.name = "qxm_qup3",
- .id = SA8775P_MASTER_QUP_3,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_A1NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_emac_0 = {
.name = "xm_emac_0",
- .id = SA8775P_MASTER_EMAC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_A1NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_emac_1 = {
.name = "xm_emac_1",
- .id = SA8775P_MASTER_EMAC_1,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_A1NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
- .id = SA8775P_MASTER_SDC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_A1NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SA8775P_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_A1NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_usb2_2 = {
.name = "xm_usb2_2",
- .id = SA8775P_MASTER_USB2,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_A1NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SA8775P_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_A1NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_usb3_1 = {
.name = "xm_usb3_1",
- .id = SA8775P_MASTER_USB3_1,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_A1NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SA8775P_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_SLAVE_A2NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
- .id = SA8775P_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_SLAVE_A2NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = SA8775P_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_SLAVE_A2NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
static struct qcom_icc_node qhm_qup2 = {
.name = "qhm_qup2",
- .id = SA8775P_MASTER_QUP_2,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_SLAVE_A2NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
static struct qcom_icc_node qnm_cnoc_datapath = {
.name = "qnm_cnoc_datapath",
- .id = SA8775P_MASTER_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_A2NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
static struct qcom_icc_node qxm_crypto_0 = {
.name = "qxm_crypto_0",
- .id = SA8775P_MASTER_CRYPTO_CORE0,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_A2NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
static struct qcom_icc_node qxm_crypto_1 = {
.name = "qxm_crypto_1",
- .id = SA8775P_MASTER_CRYPTO_CORE1,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_A2NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SA8775P_MASTER_IPA,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_A2NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
static struct qcom_icc_node xm_qdss_etr_0 = {
.name = "xm_qdss_etr_0",
- .id = SA8775P_MASTER_QDSS_ETR_0,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_A2NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
static struct qcom_icc_node xm_qdss_etr_1 = {
.name = "xm_qdss_etr_1",
- .id = SA8775P_MASTER_QDSS_ETR_1,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_A2NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
static struct qcom_icc_node xm_ufs_card = {
.name = "xm_ufs_card",
- .id = SA8775P_MASTER_UFS_CARD,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_A2NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
- .id = SA8775P_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_SLAVE_QUP_CORE_0 },
+ .link_nodes = (struct qcom_icc_node *[]) { &qup0_core_slave },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
- .id = SA8775P_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_SLAVE_QUP_CORE_1 },
+ .link_nodes = (struct qcom_icc_node *[]) { &qup1_core_slave },
};
static struct qcom_icc_node qup2_core_master = {
.name = "qup2_core_master",
- .id = SA8775P_MASTER_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_SLAVE_QUP_CORE_2 },
+ .link_nodes = (struct qcom_icc_node *[]) { &qup2_core_slave },
};
static struct qcom_icc_node qup3_core_master = {
.name = "qup3_core_master",
- .id = SA8775P_MASTER_QUP_CORE_3,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_SLAVE_QUP_CORE_3 },
+ .link_nodes = (struct qcom_icc_node *[]) { &qup3_core_slave },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
- .id = SA8775P_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
.num_links = 82,
- .links = { SA8775P_SLAVE_AHB2PHY_0,
- SA8775P_SLAVE_AHB2PHY_1,
- SA8775P_SLAVE_AHB2PHY_2,
- SA8775P_SLAVE_AHB2PHY_3,
- SA8775P_SLAVE_ANOC_THROTTLE_CFG,
- SA8775P_SLAVE_AOSS,
- SA8775P_SLAVE_APPSS,
- SA8775P_SLAVE_BOOT_ROM,
- SA8775P_SLAVE_CAMERA_CFG,
- SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG,
- SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG,
- SA8775P_SLAVE_CLK_CTL,
- SA8775P_SLAVE_CDSP_CFG,
- SA8775P_SLAVE_CDSP1_CFG,
- SA8775P_SLAVE_RBCPR_CX_CFG,
- SA8775P_SLAVE_RBCPR_MMCX_CFG,
- SA8775P_SLAVE_RBCPR_MX_CFG,
- SA8775P_SLAVE_CPR_NSPCX,
- SA8775P_SLAVE_CRYPTO_0_CFG,
- SA8775P_SLAVE_CX_RDPM,
- SA8775P_SLAVE_DISPLAY_CFG,
- SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG,
- SA8775P_SLAVE_DISPLAY1_CFG,
- SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG,
- SA8775P_SLAVE_EMAC_CFG,
- SA8775P_SLAVE_EMAC1_CFG,
- SA8775P_SLAVE_GP_DSP0_CFG,
- SA8775P_SLAVE_GP_DSP1_CFG,
- SA8775P_SLAVE_GPDSP0_THROTTLE_CFG,
- SA8775P_SLAVE_GPDSP1_THROTTLE_CFG,
- SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG,
- SA8775P_SLAVE_GFX3D_CFG,
- SA8775P_SLAVE_HWKM,
- SA8775P_SLAVE_IMEM_CFG,
- SA8775P_SLAVE_IPA_CFG,
- SA8775P_SLAVE_IPC_ROUTER_CFG,
- SA8775P_SLAVE_LPASS,
- SA8775P_SLAVE_LPASS_THROTTLE_CFG,
- SA8775P_SLAVE_MX_RDPM,
- SA8775P_SLAVE_MXC_RDPM,
- SA8775P_SLAVE_PCIE_0_CFG,
- SA8775P_SLAVE_PCIE_1_CFG,
- SA8775P_SLAVE_PCIE_RSC_CFG,
- SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG,
- SA8775P_SLAVE_PCIE_THROTTLE_CFG,
- SA8775P_SLAVE_PDM,
- SA8775P_SLAVE_PIMEM_CFG,
- SA8775P_SLAVE_PKA_WRAPPER_CFG,
- SA8775P_SLAVE_QDSS_CFG,
- SA8775P_SLAVE_QM_CFG,
- SA8775P_SLAVE_QM_MPU_CFG,
- SA8775P_SLAVE_QUP_0,
- SA8775P_SLAVE_QUP_1,
- SA8775P_SLAVE_QUP_2,
- SA8775P_SLAVE_QUP_3,
- SA8775P_SLAVE_SAIL_THROTTLE_CFG,
- SA8775P_SLAVE_SDC1,
- SA8775P_SLAVE_SECURITY,
- SA8775P_SLAVE_SNOC_THROTTLE_CFG,
- SA8775P_SLAVE_TCSR,
- SA8775P_SLAVE_TLMM,
- SA8775P_SLAVE_TSC_CFG,
- SA8775P_SLAVE_UFS_CARD_CFG,
- SA8775P_SLAVE_UFS_MEM_CFG,
- SA8775P_SLAVE_USB2,
- SA8775P_SLAVE_USB3_0,
- SA8775P_SLAVE_USB3_1,
- SA8775P_SLAVE_VENUS_CFG,
- SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG,
- SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
- SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
- SA8775P_SLAVE_DDRSS_CFG,
- SA8775P_SLAVE_GPDSP_NOC_CFG,
- SA8775P_SLAVE_CNOC_MNOC_HF_CFG,
- SA8775P_SLAVE_CNOC_MNOC_SF_CFG,
- SA8775P_SLAVE_PCIE_ANOC_CFG,
- SA8775P_SLAVE_SNOC_CFG,
- SA8775P_SLAVE_BOOT_IMEM,
- SA8775P_SLAVE_IMEM,
- SA8775P_SLAVE_PIMEM,
- SA8775P_SLAVE_QDSS_STM,
- SA8775P_SLAVE_TCU
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &qhs_ahb2phy0, &qhs_ahb2phy1,
+ &qhs_ahb2phy2, &qhs_ahb2phy3,
+ &qhs_anoc_throttle_cfg, &qhs_aoss,
+ &qhs_apss, &qhs_boot_rom,
+ &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg,
+ &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl,
+ &qhs_compute0_cfg, &qhs_compute1_cfg,
+ &qhs_cpr_cx, &qhs_cpr_mmcx,
+ &qhs_cpr_mx, &qhs_cpr_nspcx,
+ &qhs_crypto0_cfg, &qhs_cx_rdpm,
+ &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg,
+ &qhs_display1_cfg, &qhs_display1_rt_throttle_cfg,
+ &qhs_emac0_cfg, &qhs_emac1_cfg,
+ &qhs_gp_dsp0_cfg, &qhs_gp_dsp1_cfg,
+ &qhs_gpdsp0_throttle_cfg, &qhs_gpdsp1_throttle_cfg,
+ &qhs_gpu_tcu_throttle_cfg, &qhs_gpuss_cfg,
+ &qhs_hwkm, &qhs_imem_cfg,
+ &qhs_ipa, &qhs_ipc_router,
+ &qhs_lpass_cfg, &qhs_lpass_throttle_cfg,
+ &qhs_mx_rdpm, &qhs_mxc_rdpm,
+ &qhs_pcie0_cfg, &qhs_pcie1_cfg,
+ &qhs_pcie_rsc_cfg, &qhs_pcie_tcu_throttle_cfg,
+ &qhs_pcie_throttle_cfg, &qhs_pdm,
+ &qhs_pimem_cfg, &qhs_pke_wrapper_cfg,
+ &qhs_qdss_cfg, &qhs_qm_cfg,
+ &qhs_qm_mpu_cfg, &qhs_qup0,
+ &qhs_qup1, &qhs_qup2,
+ &qhs_qup3, &qhs_sail_throttle_cfg,
+ &qhs_sdc1, &qhs_security,
+ &qhs_snoc_throttle_cfg, &qhs_tcsr,
+ &qhs_tlmm, &qhs_tsc_cfg,
+ &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg,
+ &qhs_usb2_0, &qhs_usb3_0,
+ &qhs_usb3_1, &qhs_venus_cfg,
+ &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg,
+ &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg,
+ &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg,
+ &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg,
+ &qns_snoc_cfg, &qxs_boot_imem,
+ &qxs_imem, &qxs_pimem,
+ &xs_qdss_stm, &xs_sys_tcu_cfg },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = SA8775P_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 16,
.num_links = 2,
- .links = { SA8775P_SLAVE_PCIE_0,
- SA8775P_SLAVE_PCIE_1
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &xs_pcie_0, &xs_pcie_1 },
};
static struct qcom_icc_node qnm_cnoc_dc_noc = {
.name = "qnm_cnoc_dc_noc",
- .id = SA8775P_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
.num_links = 2,
- .links = { SA8775P_SLAVE_LLCC_CFG,
- SA8775P_SLAVE_GEM_NOC_CFG
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &qhs_llcc, &qns_gemnoc },
};
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
- .id = SA8775P_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
.num_links = 2,
- .links = { SA8775P_SLAVE_GEM_NOC_CNOC,
- SA8775P_SLAVE_LLCC
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node alm_pcie_tcu = {
.name = "alm_pcie_tcu",
- .id = SA8775P_MASTER_PCIE_TCU,
.channels = 1,
.buswidth = 8,
.num_links = 2,
- .links = { SA8775P_SLAVE_GEM_NOC_CNOC,
- SA8775P_SLAVE_LLCC
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
- .id = SA8775P_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
.num_links = 2,
- .links = { SA8775P_SLAVE_GEM_NOC_CNOC,
- SA8775P_SLAVE_LLCC
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
- .id = SA8775P_MASTER_APPSS_PROC,
.channels = 4,
.buswidth = 32,
.num_links = 3,
- .links = { SA8775P_SLAVE_GEM_NOC_CNOC,
- SA8775P_SLAVE_LLCC,
- SA8775P_SLAVE_GEM_NOC_PCIE_CNOC
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
};
static struct qcom_icc_node qnm_cmpnoc0 = {
.name = "qnm_cmpnoc0",
- .id = SA8775P_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
.num_links = 2,
- .links = { SA8775P_SLAVE_GEM_NOC_CNOC,
- SA8775P_SLAVE_LLCC
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node qnm_cmpnoc1 = {
.name = "qnm_cmpnoc1",
- .id = SA8775P_MASTER_COMPUTE_NOC_1,
.channels = 2,
.buswidth = 32,
.num_links = 2,
- .links = { SA8775P_SLAVE_GEM_NOC_CNOC,
- SA8775P_SLAVE_LLCC
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node qnm_gemnoc_cfg = {
.name = "qnm_gemnoc_cfg",
- .id = SA8775P_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 4,
- .links = { SA8775P_SLAVE_SERVICE_GEM_NOC_1,
- SA8775P_SLAVE_SERVICE_GEM_NOC_2,
- SA8775P_SLAVE_SERVICE_GEM_NOC,
- SA8775P_SLAVE_SERVICE_GEM_NOC2
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &srvc_even_gemnoc, &srvc_odd_gemnoc,
+ &srvc_sys_gemnoc, &srvc_sys_gemnoc_2 },
};
static struct qcom_icc_node qnm_gpdsp_sail = {
.name = "qnm_gpdsp_sail",
- .id = SA8775P_MASTER_GPDSP_SAIL,
.channels = 1,
.buswidth = 16,
.num_links = 2,
- .links = { SA8775P_SLAVE_GEM_NOC_CNOC,
- SA8775P_SLAVE_LLCC
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
- .id = SA8775P_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
.num_links = 2,
- .links = { SA8775P_SLAVE_GEM_NOC_CNOC,
- SA8775P_SLAVE_LLCC
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SA8775P_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
.num_links = 2,
- .links = { SA8775P_SLAVE_LLCC,
- SA8775P_SLAVE_GEM_NOC_PCIE_CNOC
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc, &qns_pcie },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SA8775P_MASTER_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
.num_links = 3,
- .links = { SA8775P_SLAVE_GEM_NOC_CNOC,
- SA8775P_SLAVE_LLCC,
- SA8775P_SLAVE_GEM_NOC_PCIE_CNOC
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = SA8775P_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 32,
.num_links = 2,
- .links = { SA8775P_SLAVE_GEM_NOC_CNOC,
- SA8775P_SLAVE_LLCC
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SA8775P_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_LLCC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SA8775P_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
.num_links = 3,
- .links = { SA8775P_SLAVE_GEM_NOC_CNOC,
- SA8775P_SLAVE_LLCC,
- SA8775P_SLAVE_GEM_NOC_PCIE_CNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
};
static struct qcom_icc_node qxm_dsp0 = {
.name = "qxm_dsp0",
- .id = SA8775P_MASTER_DSP0,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SA8775P_SLAVE_GP_DSP_SAIL_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gp_dsp_sail_noc },
};
static struct qcom_icc_node qxm_dsp1 = {
.name = "qxm_dsp1",
- .id = SA8775P_MASTER_DSP1,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SA8775P_SLAVE_GP_DSP_SAIL_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gp_dsp_sail_noc },
};
static struct qcom_icc_node qhm_config_noc = {
.name = "qhm_config_noc",
- .id = SA8775P_MASTER_CNOC_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
.num_links = 6,
- .links = { SA8775P_SLAVE_LPASS_CORE_CFG,
- SA8775P_SLAVE_LPASS_LPI_CFG,
- SA8775P_SLAVE_LPASS_MPU_CFG,
- SA8775P_SLAVE_LPASS_TOP_CFG,
- SA8775P_SLAVE_SERVICES_LPASS_AML_NOC,
- SA8775P_SLAVE_SERVICE_LPASS_AG_NOC
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &qhs_lpass_core, &qhs_lpass_lpi,
+ &qhs_lpass_mpu, &qhs_lpass_top,
+ &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc },
};
static struct qcom_icc_node qxm_lpass_dsp = {
.name = "qxm_lpass_dsp",
- .id = SA8775P_MASTER_LPASS_PROC,
.channels = 1,
.buswidth = 8,
.num_links = 4,
- .links = { SA8775P_SLAVE_LPASS_TOP_CFG,
- SA8775P_SLAVE_LPASS_SNOC,
- SA8775P_SLAVE_SERVICES_LPASS_AML_NOC,
- SA8775P_SLAVE_SERVICE_LPASS_AG_NOC
- },
+ .link_nodes = (struct qcom_icc_node *[]) { &qhs_lpass_top, &qns_sysnoc,
+ &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SA8775P_MASTER_LLCC,
.channels = 8,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_SLAVE_EBI1 },
+ .link_nodes = (struct qcom_icc_node *[]) { &ebi },
};
static struct qcom_icc_node qnm_camnoc_hf = {
.name = "qnm_camnoc_hf",
- .id = SA8775P_MASTER_CAMNOC_HF,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
};
static struct qcom_icc_node qnm_camnoc_icp = {
.name = "qnm_camnoc_icp",
- .id = SA8775P_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
};
static struct qcom_icc_node qnm_camnoc_sf = {
.name = "qnm_camnoc_sf",
- .id = SA8775P_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
};
static struct qcom_icc_node qnm_mdp0_0 = {
.name = "qnm_mdp0_0",
- .id = SA8775P_MASTER_MDP0,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
};
static struct qcom_icc_node qnm_mdp0_1 = {
.name = "qnm_mdp0_1",
- .id = SA8775P_MASTER_MDP1,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
};
static struct qcom_icc_node qnm_mdp1_0 = {
.name = "qnm_mdp1_0",
- .id = SA8775P_MASTER_MDP_CORE1_0,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
};
static struct qcom_icc_node qnm_mdp1_1 = {
.name = "qnm_mdp1_1",
- .id = SA8775P_MASTER_MDP_CORE1_1,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
};
static struct qcom_icc_node qnm_mnoc_hf_cfg = {
.name = "qnm_mnoc_hf_cfg",
- .id = SA8775P_MASTER_CNOC_MNOC_HF_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_SLAVE_SERVICE_MNOC_HF },
+ .link_nodes = (struct qcom_icc_node *[]) { &srvc_mnoc_hf },
};
static struct qcom_icc_node qnm_mnoc_sf_cfg = {
.name = "qnm_mnoc_sf_cfg",
- .id = SA8775P_MASTER_CNOC_MNOC_SF_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_SLAVE_SERVICE_MNOC_SF },
+ .link_nodes = (struct qcom_icc_node *[]) { &srvc_mnoc_sf },
};
static struct qcom_icc_node qnm_video0 = {
.name = "qnm_video0",
- .id = SA8775P_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
};
static struct qcom_icc_node qnm_video1 = {
.name = "qnm_video1",
- .id = SA8775P_MASTER_VIDEO_P1,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
};
static struct qcom_icc_node qnm_video_cvp = {
.name = "qnm_video_cvp",
- .id = SA8775P_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
};
static struct qcom_icc_node qnm_video_v_cpu = {
.name = "qnm_video_v_cpu",
- .id = SA8775P_MASTER_VIDEO_V_PROC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
};
static struct qcom_icc_node qhm_nsp_noc_config = {
.name = "qhm_nsp_noc_config",
- .id = SA8775P_MASTER_CDSP_NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_SLAVE_SERVICE_NSP_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &service_nsp_noc },
};
static struct qcom_icc_node qxm_nsp = {
.name = "qxm_nsp",
- .id = SA8775P_MASTER_CDSP_PROC,
.channels = 2,
.buswidth = 32,
.num_links = 2,
- .links = { SA8775P_SLAVE_HCP_A, SLAVE_CDSP_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_hcp, &qns_nsp_gemnoc },
};
static struct qcom_icc_node qhm_nspb_noc_config = {
.name = "qhm_nspb_noc_config",
- .id = SA8775P_MASTER_CDSPB_NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_SLAVE_SERVICE_NSPB_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &service_nspb_noc },
};
static struct qcom_icc_node qxm_nspb = {
.name = "qxm_nspb",
- .id = SA8775P_MASTER_CDSP_PROC_B,
.channels = 2,
.buswidth = 32,
.num_links = 2,
- .links = { SA8775P_SLAVE_HCP_B, SLAVE_CDSPB_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_nspb_hcp, &qns_nspb_gemnoc },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
- .id = SA8775P_MASTER_PCIE_0,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SA8775P_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc },
};
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
- .id = SA8775P_MASTER_PCIE_1,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc },
};
static struct qcom_icc_node qhm_gic = {
.name = "qhm_gic",
- .id = SA8775P_MASTER_GIC_AHB,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SA8775P_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SA8775P_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
};
static struct qcom_icc_node qnm_lpass_noc = {
.name = "qnm_lpass_noc",
- .id = SA8775P_MASTER_LPASS_ANOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
};
static struct qcom_icc_node qnm_snoc_cfg = {
.name = "qnm_snoc_cfg",
- .id = SA8775P_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_SLAVE_SERVICE_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &srvc_snoc },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = SA8775P_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SA8775P_MASTER_GIC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SA8775P_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_MASTER_A1NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre1_noc },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SA8775P_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SA8775P_MASTER_A2NOC_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre2_noc },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
- .id = SA8775P_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
- .id = SA8775P_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qup2_core_slave = {
.name = "qup2_core_slave",
- .id = SA8775P_SLAVE_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qup3_core_slave = {
.name = "qup3_core_slave",
- .id = SA8775P_SLAVE_QUP_CORE_3,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
- .id = SA8775P_SLAVE_AHB2PHY_0,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ahb2phy1 = {
.name = "qhs_ahb2phy1",
- .id = SA8775P_SLAVE_AHB2PHY_1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ahb2phy2 = {
.name = "qhs_ahb2phy2",
- .id = SA8775P_SLAVE_AHB2PHY_2,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ahb2phy3 = {
.name = "qhs_ahb2phy3",
- .id = SA8775P_SLAVE_AHB2PHY_3,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_anoc_throttle_cfg = {
.name = "qhs_anoc_throttle_cfg",
- .id = SA8775P_SLAVE_ANOC_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SA8775P_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SA8775P_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node qhs_boot_rom = {
.name = "qhs_boot_rom",
- .id = SA8775P_SLAVE_BOOT_ROM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SA8775P_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {
.name = "qhs_camera_nrt_throttle_cfg",
- .id = SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
.name = "qhs_camera_rt_throttle_cfg",
- .id = SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SA8775P_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_compute0_cfg = {
.name = "qhs_compute0_cfg",
- .id = SA8775P_SLAVE_CDSP_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_MASTER_CDSP_NOC_CFG },
+ .link_nodes = (struct qcom_icc_node *[]) { &qhm_nsp_noc_config },
};
static struct qcom_icc_node qhs_compute1_cfg = {
.name = "qhs_compute1_cfg",
- .id = SA8775P_SLAVE_CDSP1_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_MASTER_CDSPB_NOC_CFG },
+ .link_nodes = (struct qcom_icc_node *[]) { &qhm_nspb_noc_config },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SA8775P_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_cpr_mmcx = {
.name = "qhs_cpr_mmcx",
- .id = SA8775P_SLAVE_RBCPR_MMCX_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
- .id = SA8775P_SLAVE_RBCPR_MX_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_cpr_nspcx = {
.name = "qhs_cpr_nspcx",
- .id = SA8775P_SLAVE_CPR_NSPCX,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SA8775P_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_cx_rdpm = {
.name = "qhs_cx_rdpm",
- .id = SA8775P_SLAVE_CX_RDPM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_display0_cfg = {
.name = "qhs_display0_cfg",
- .id = SA8775P_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_display0_rt_throttle_cfg = {
.name = "qhs_display0_rt_throttle_cfg",
- .id = SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_display1_cfg = {
.name = "qhs_display1_cfg",
- .id = SA8775P_SLAVE_DISPLAY1_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_display1_rt_throttle_cfg = {
.name = "qhs_display1_rt_throttle_cfg",
- .id = SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_emac0_cfg = {
.name = "qhs_emac0_cfg",
- .id = SA8775P_SLAVE_EMAC_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_emac1_cfg = {
.name = "qhs_emac1_cfg",
- .id = SA8775P_SLAVE_EMAC1_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_gp_dsp0_cfg = {
.name = "qhs_gp_dsp0_cfg",
- .id = SA8775P_SLAVE_GP_DSP0_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_gp_dsp1_cfg = {
.name = "qhs_gp_dsp1_cfg",
- .id = SA8775P_SLAVE_GP_DSP1_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = {
.name = "qhs_gpdsp0_throttle_cfg",
- .id = SA8775P_SLAVE_GPDSP0_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_gpdsp1_throttle_cfg = {
.name = "qhs_gpdsp1_throttle_cfg",
- .id = SA8775P_SLAVE_GPDSP1_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = {
.name = "qhs_gpu_tcu_throttle_cfg",
- .id = SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SA8775P_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node qhs_hwkm = {
.name = "qhs_hwkm",
- .id = SA8775P_SLAVE_HWKM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SA8775P_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SA8775P_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
- .id = SA8775P_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_lpass_cfg = {
.name = "qhs_lpass_cfg",
- .id = SA8775P_SLAVE_LPASS,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_MASTER_CNOC_LPASS_AG_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qhm_config_noc },
};
static struct qcom_icc_node qhs_lpass_throttle_cfg = {
.name = "qhs_lpass_throttle_cfg",
- .id = SA8775P_SLAVE_LPASS_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_mx_rdpm = {
.name = "qhs_mx_rdpm",
- .id = SA8775P_SLAVE_MX_RDPM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_mxc_rdpm = {
.name = "qhs_mxc_rdpm",
- .id = SA8775P_SLAVE_MXC_RDPM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
- .id = SA8775P_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
- .id = SA8775P_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pcie_rsc_cfg = {
.name = "qhs_pcie_rsc_cfg",
- .id = SA8775P_SLAVE_PCIE_RSC_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = {
.name = "qhs_pcie_tcu_throttle_cfg",
- .id = SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pcie_throttle_cfg = {
.name = "qhs_pcie_throttle_cfg",
- .id = SA8775P_SLAVE_PCIE_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SA8775P_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SA8775P_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pke_wrapper_cfg = {
.name = "qhs_pke_wrapper_cfg",
- .id = SA8775P_SLAVE_PKA_WRAPPER_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SA8775P_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qm_cfg = {
.name = "qhs_qm_cfg",
- .id = SA8775P_SLAVE_QM_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qm_mpu_cfg = {
.name = "qhs_qm_mpu_cfg",
- .id = SA8775P_SLAVE_QM_MPU_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
- .id = SA8775P_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = SA8775P_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qup2 = {
.name = "qhs_qup2",
- .id = SA8775P_SLAVE_QUP_2,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qup3 = {
.name = "qhs_qup3",
- .id = SA8775P_SLAVE_QUP_3,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_sail_throttle_cfg = {
.name = "qhs_sail_throttle_cfg",
- .id = SA8775P_SLAVE_SAIL_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_sdc1 = {
.name = "qhs_sdc1",
- .id = SA8775P_SLAVE_SDC1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_security = {
.name = "qhs_security",
- .id = SA8775P_SLAVE_SECURITY,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_snoc_throttle_cfg = {
.name = "qhs_snoc_throttle_cfg",
- .id = SA8775P_SLAVE_SNOC_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SA8775P_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = SA8775P_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_tsc_cfg = {
.name = "qhs_tsc_cfg",
- .id = SA8775P_SLAVE_TSC_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ufs_card_cfg = {
.name = "qhs_ufs_card_cfg",
- .id = SA8775P_SLAVE_UFS_CARD_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SA8775P_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_usb2_0 = {
.name = "qhs_usb2_0",
- .id = SA8775P_SLAVE_USB2,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SA8775P_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_usb3_1 = {
.name = "qhs_usb3_1",
- .id = SA8775P_SLAVE_USB3_1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SA8775P_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
.name = "qhs_venus_cvp_throttle_cfg",
- .id = SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = {
.name = "qhs_venus_v_cpu_throttle_cfg",
- .id = SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = {
.name = "qhs_venus_vcodec_throttle_cfg",
- .id = SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_ddrss_cfg = {
.name = "qns_ddrss_cfg",
- .id = SA8775P_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_MASTER_CNOC_DC_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_cnoc_dc_noc },
};
static struct qcom_icc_node qns_gpdsp_noc_cfg = {
.name = "qns_gpdsp_noc_cfg",
- .id = SA8775P_SLAVE_GPDSP_NOC_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_mnoc_hf_cfg = {
.name = "qns_mnoc_hf_cfg",
- .id = SA8775P_SLAVE_CNOC_MNOC_HF_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_MASTER_CNOC_MNOC_HF_CFG },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_hf_cfg },
};
static struct qcom_icc_node qns_mnoc_sf_cfg = {
.name = "qns_mnoc_sf_cfg",
- .id = SA8775P_SLAVE_CNOC_MNOC_SF_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_MASTER_CNOC_MNOC_SF_CFG },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_sf_cfg },
};
static struct qcom_icc_node qns_pcie_anoc_cfg = {
.name = "qns_pcie_anoc_cfg",
- .id = SA8775P_SLAVE_PCIE_ANOC_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_snoc_cfg = {
.name = "qns_snoc_cfg",
- .id = SA8775P_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_MASTER_SNOC_CFG },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_cfg },
};
static struct qcom_icc_node qxs_boot_imem = {
.name = "qxs_boot_imem",
- .id = SA8775P_SLAVE_BOOT_IMEM,
.channels = 1,
.buswidth = 16,
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SA8775P_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = SA8775P_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
- .id = SA8775P_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 16,
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
- .id = SA8775P_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 32,
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SA8775P_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SA8775P_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
- .id = SA8775P_SLAVE_LLCC_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_gemnoc = {
.name = "qns_gemnoc",
- .id = SA8775P_SLAVE_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SA8775P_MASTER_GEM_NOC_CFG },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_cfg },
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
- .id = SA8775P_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SA8775P_MASTER_GEM_NOC_CNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_cnoc },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SA8775P_SLAVE_LLCC,
.channels = 6,
.buswidth = 16,
.num_links = 1,
- .links = { SA8775P_MASTER_LLCC },
+ .link_nodes = (struct qcom_icc_node *[]) { &llcc_mc },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
- .id = SA8775P_SLAVE_GEM_NOC_PCIE_CNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SA8775P_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_pcie },
};
static struct qcom_icc_node srvc_even_gemnoc = {
.name = "srvc_even_gemnoc",
- .id = SA8775P_SLAVE_SERVICE_GEM_NOC_1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node srvc_odd_gemnoc = {
.name = "srvc_odd_gemnoc",
- .id = SA8775P_SLAVE_SERVICE_GEM_NOC_2,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node srvc_sys_gemnoc = {
.name = "srvc_sys_gemnoc",
- .id = SA8775P_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node srvc_sys_gemnoc_2 = {
.name = "srvc_sys_gemnoc_2",
- .id = SA8775P_SLAVE_SERVICE_GEM_NOC2,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_gp_dsp_sail_noc = {
.name = "qns_gp_dsp_sail_noc",
- .id = SA8775P_SLAVE_GP_DSP_SAIL_NOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SA8775P_MASTER_GPDSP_SAIL },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_gpdsp_sail },
};
static struct qcom_icc_node qhs_lpass_core = {
.name = "qhs_lpass_core",
- .id = SA8775P_SLAVE_LPASS_CORE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_lpass_lpi = {
.name = "qhs_lpass_lpi",
- .id = SA8775P_SLAVE_LPASS_LPI_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_lpass_mpu = {
.name = "qhs_lpass_mpu",
- .id = SA8775P_SLAVE_LPASS_MPU_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_lpass_top = {
.name = "qhs_lpass_top",
- .id = SA8775P_SLAVE_LPASS_TOP_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_sysnoc = {
.name = "qns_sysnoc",
- .id = SA8775P_SLAVE_LPASS_SNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SA8775P_MASTER_LPASS_ANOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_lpass_noc },
};
static struct qcom_icc_node srvc_niu_aml_noc = {
.name = "srvc_niu_aml_noc",
- .id = SA8775P_SLAVE_SERVICES_LPASS_AML_NOC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node srvc_niu_lpass_agnoc = {
.name = "srvc_niu_lpass_agnoc",
- .id = SA8775P_SLAVE_SERVICE_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SA8775P_SLAVE_EBI1,
.channels = 8,
.buswidth = 4,
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SA8775P_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_hf },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
- .id = SA8775P_SLAVE_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_sf },
};
static struct qcom_icc_node srvc_mnoc_hf = {
.name = "srvc_mnoc_hf",
- .id = SA8775P_SLAVE_SERVICE_MNOC_HF,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node srvc_mnoc_sf = {
.name = "srvc_mnoc_sf",
- .id = SA8775P_SLAVE_SERVICE_MNOC_SF,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_hcp = {
.name = "qns_hcp",
- .id = SA8775P_SLAVE_HCP_A,
.channels = 2,
.buswidth = 32,
};
static struct qcom_icc_node qns_nsp_gemnoc = {
.name = "qns_nsp_gemnoc",
- .id = SA8775P_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_MASTER_COMPUTE_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_cmpnoc0 },
};
static struct qcom_icc_node service_nsp_noc = {
.name = "service_nsp_noc",
- .id = SA8775P_SLAVE_SERVICE_NSP_NOC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_nspb_gemnoc = {
.name = "qns_nspb_gemnoc",
- .id = SA8775P_SLAVE_CDSPB_MEM_NOC,
.channels = 2,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_MASTER_COMPUTE_NOC_1 },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_cmpnoc1 },
};
static struct qcom_icc_node qns_nspb_hcp = {
.name = "qns_nspb_hcp",
- .id = SA8775P_SLAVE_HCP_B,
.channels = 2,
.buswidth = 32,
};
static struct qcom_icc_node service_nspb_noc = {
.name = "service_nspb_noc",
- .id = SA8775P_SLAVE_SERVICE_NSPB_NOC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_pcie_mem_noc = {
.name = "qns_pcie_mem_noc",
- .id = SA8775P_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SA8775P_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_pcie },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = SA8775P_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SA8775P_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_gc },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SA8775P_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SA8775P_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_sf },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SA8775P_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
};
@@ -2113,6 +1841,7 @@ static const struct qcom_icc_desc sa8775p_aggre1_noc = {
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
+ .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
@@ -2140,6 +1869,7 @@ static const struct qcom_icc_desc sa8775p_aggre2_noc = {
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
+ .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
@@ -2164,6 +1894,7 @@ static const struct qcom_icc_desc sa8775p_clk_virt = {
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
+ .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const config_noc_bcms[] = {
@@ -2269,6 +2000,7 @@ static const struct qcom_icc_desc sa8775p_config_noc = {
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
.num_bcms = ARRAY_SIZE(config_noc_bcms),
+ .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const dc_noc_bcms[] = {
@@ -2285,6 +2017,7 @@ static const struct qcom_icc_desc sa8775p_dc_noc = {
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
+ .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
@@ -2321,6 +2054,7 @@ static const struct qcom_icc_desc sa8775p_gem_noc = {
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
+ .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = {
@@ -2339,6 +2073,7 @@ static const struct qcom_icc_desc sa8775p_gpdsp_anoc = {
.num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
.bcms = gpdsp_anoc_bcms,
.num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms),
+ .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
@@ -2362,6 +2097,7 @@ static const struct qcom_icc_desc sa8775p_lpass_ag_noc = {
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
+ .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
@@ -2379,6 +2115,7 @@ static const struct qcom_icc_desc sa8775p_mc_virt = {
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
+ .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
@@ -2411,6 +2148,7 @@ static const struct qcom_icc_desc sa8775p_mmss_noc = {
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
+ .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const nspa_noc_bcms[] = {
@@ -2431,6 +2169,7 @@ static const struct qcom_icc_desc sa8775p_nspa_noc = {
.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
.bcms = nspa_noc_bcms,
.num_bcms = ARRAY_SIZE(nspa_noc_bcms),
+ .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const nspb_noc_bcms[] = {
@@ -2451,6 +2190,7 @@ static const struct qcom_icc_desc sa8775p_nspb_noc = {
.num_nodes = ARRAY_SIZE(nspb_noc_nodes),
.bcms = nspb_noc_bcms,
.num_bcms = ARRAY_SIZE(nspb_noc_bcms),
+ .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
@@ -2468,6 +2208,7 @@ static const struct qcom_icc_desc sa8775p_pcie_anoc = {
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
+ .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const system_noc_bcms[] = {
@@ -2496,6 +2237,7 @@ static const struct qcom_icc_desc sa8775p_system_noc = {
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
.num_bcms = ARRAY_SIZE(system_noc_bcms),
+ .alloc_dyn_id = true,
};
static const struct of_device_id qnoc_of_match[] = {
--
2.43.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH V10 6/7] arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider
2025-03-24 18:31 [PATCH V10 0/7]Add EPSS L3 provider support on SA8775P SoC Raviteja Laggyshetty
` (4 preceding siblings ...)
2025-03-24 18:32 ` [PATCH V10 5/7] interconnect: qcom: sa8775p: " Raviteja Laggyshetty
@ 2025-03-24 18:32 ` Raviteja Laggyshetty
2025-03-26 17:41 ` Dmitry Baryshkov
2025-03-24 18:32 ` [PATCH V10 7/7] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3 Raviteja Laggyshetty
6 siblings, 1 reply; 14+ messages in thread
From: Raviteja Laggyshetty @ 2025-03-24 18:32 UTC (permalink / raw)
To: Georgi Djakov, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio, Raviteja Laggyshetty,
Odelu Kukatla, Mike Tipton, Jagadeesh Kona
Cc: Jeff Johnson, Sibi Sankar, linux-arm-msm, linux-pm, devicetree,
linux-kernel, Konrad Dybcio
Add Epoch Subsystem (EPSS) L3 interconnect provider node on SA8775P
SoCs. L3 instances on this SoC are same as SM8250 and SC7280 SoCs.
These SoCs use EPSS_L3_PERF register instead of REG_L3_VOTE register for
programming the perf level. This is taken care in the data associated
with the target specific compatible. Since, the HW is same in the all
SoCs with EPSS support, using the same generic compatible for all.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index a904960359d7..fac5dfb147fd 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/firmware/qcom,scm.h>
@@ -4797,6 +4798,15 @@ rpmhpd_opp_turbo_l1: opp-9 {
};
};
+ epss_l3_cl0: interconnect@18590000 {
+ compatible = "qcom,sa8775p-epss-l3",
+ "qcom,epss-l3";
+ reg = <0x0 0x18590000 0x0 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,sa8775p-cpufreq-epss",
"qcom,cpufreq-epss";
@@ -4814,6 +4824,15 @@ cpufreq_hw: cpufreq@18591000 {
#freq-domain-cells = <1>;
};
+ epss_l3_cl1: interconnect@18592000 {
+ compatible = "qcom,sa8775p-epss-l3",
+ "qcom,epss-l3";
+ reg = <0x0 0x18592000 0x0 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
remoteproc_gpdsp0: remoteproc@20c00000 {
compatible = "qcom,sa8775p-gpdsp0-pas";
reg = <0x0 0x20c00000 0x0 0x10000>;
--
2.43.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH V10 7/7] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
2025-03-24 18:31 [PATCH V10 0/7]Add EPSS L3 provider support on SA8775P SoC Raviteja Laggyshetty
` (5 preceding siblings ...)
2025-03-24 18:32 ` [PATCH V10 6/7] arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider Raviteja Laggyshetty
@ 2025-03-24 18:32 ` Raviteja Laggyshetty
2025-03-26 17:42 ` Dmitry Baryshkov
6 siblings, 1 reply; 14+ messages in thread
From: Raviteja Laggyshetty @ 2025-03-24 18:32 UTC (permalink / raw)
To: Georgi Djakov, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio, Raviteja Laggyshetty,
Odelu Kukatla, Mike Tipton, Jagadeesh Kona
Cc: Jeff Johnson, Sibi Sankar, linux-arm-msm, linux-pm, devicetree,
linux-kernel, Shivnandan Kumar
From: Jagadeesh Kona <quic_jkona@quicinc.com>
Add OPP tables required to scale DDR and L3 per freq-domain
on SA8775P platform.
If a single OPP table is used for both CPU domains, then
_allocate_opp_table() won't be invoked for CPU4 but instead
CPU4 will be added as device under the CPU0 OPP table. Due
to this, dev_pm_opp_of_find_icc_paths() won't be invoked for
CPU4 device and hence CPU4 won't be able to independently scale
it's interconnects. Both CPU0 and CPU4 devices will scale the
same ICC path which can lead to one device overwriting the BW
vote placed by other device. Hence CPU0 and CPU4 require separate
OPP tables to allow independent scaling of DDR and L3 frequencies
for each CPU domain, with the final DDR and L3 frequencies being
an aggregate of both.
Co-developed-by: Shivnandan Kumar <quic_kshivnan@quicinc.com>
Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com>
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 210 ++++++++++++++++++++++++++
1 file changed, 210 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index fac5dfb147fd..800db236a1e0 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -52,6 +52,11 @@ cpu0: cpu@0 {
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl0 MASTER_EPSS_L3_APPS
+ &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -76,6 +81,11 @@ cpu1: cpu@100 {
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl0 MASTER_EPSS_L3_APPS
+ &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -95,6 +105,11 @@ cpu2: cpu@200 {
next-level-cache = <&l2_2>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl0 MASTER_EPSS_L3_APPS
+ &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
l2_2: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -114,6 +129,11 @@ cpu3: cpu@300 {
next-level-cache = <&l2_3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl0 MASTER_EPSS_L3_APPS
+ &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
l2_3: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -133,6 +153,11 @@ cpu4: cpu@10000 {
next-level-cache = <&l2_4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl1 MASTER_EPSS_L3_APPS
+ &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
l2_4: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -158,6 +183,11 @@ cpu5: cpu@10100 {
next-level-cache = <&l2_5>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl1 MASTER_EPSS_L3_APPS
+ &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
l2_5: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -177,6 +207,11 @@ cpu6: cpu@10200 {
next-level-cache = <&l2_6>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl1 MASTER_EPSS_L3_APPS
+ &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
l2_6: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -196,6 +231,11 @@ cpu7: cpu@10300 {
next-level-cache = <&l2_7>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl1 MASTER_EPSS_L3_APPS
+ &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
l2_7: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -285,6 +325,176 @@ cluster_sleep_apss_rsc_pc: cluster-sleep-1 {
};
};
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1267200000 {
+ opp-hz = /bits/ 64 <1267200000>;
+ opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
+ };
+
+ opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
+ };
+
+ opp-1459200000 {
+ opp-hz = /bits/ 64 <1459200000>;
+ opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
+ };
+
+ opp-1536000000 {
+ opp-hz = /bits/ 64 <1536000000>;
+ opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
+ };
+
+ opp-1632000000 {
+ opp-hz = /bits/ 64 <1632000000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-1862400000 {
+ opp-hz = /bits/ 64 <1862400000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-1939200000 {
+ opp-hz = /bits/ 64 <1939200000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-2112000000 {
+ opp-hz = /bits/ 64 <2112000000>;
+ opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
+ };
+
+ opp-2188800000 {
+ opp-hz = /bits/ 64 <2188800000>;
+ opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
+ };
+
+ opp-2265600000 {
+ opp-hz = /bits/ 64 <2265600000>;
+ opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
+ };
+
+ opp-2361600000 {
+ opp-hz = /bits/ 64 <2361600000>;
+ opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
+ };
+
+ opp-2457600000 {
+ opp-hz = /bits/ 64 <2457600000>;
+ opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
+ };
+
+ opp-2553600000 {
+ opp-hz = /bits/ 64 <2553600000>;
+ opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>;
+ };
+ };
+
+ cpu4_opp_table: opp-table-cpu4 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1267200000 {
+ opp-hz = /bits/ 64 <1267200000>;
+ opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
+ };
+
+ opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
+ };
+
+ opp-1459200000 {
+ opp-hz = /bits/ 64 <1459200000>;
+ opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
+ };
+
+ opp-1536000000 {
+ opp-hz = /bits/ 64 <1536000000>;
+ opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
+ };
+
+ opp-1632000000 {
+ opp-hz = /bits/ 64 <1632000000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-1862400000 {
+ opp-hz = /bits/ 64 <1862400000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-1939200000 {
+ opp-hz = /bits/ 64 <1939200000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-2112000000 {
+ opp-hz = /bits/ 64 <2112000000>;
+ opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
+ };
+
+ opp-2188800000 {
+ opp-hz = /bits/ 64 <2188800000>;
+ opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
+ };
+
+ opp-2265600000 {
+ opp-hz = /bits/ 64 <2265600000>;
+ opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
+ };
+
+ opp-2361600000 {
+ opp-hz = /bits/ 64 <2361600000>;
+ opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
+ };
+
+ opp-2457600000 {
+ opp-hz = /bits/ 64 <2457600000>;
+ opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
+ };
+
+ opp-2553600000 {
+ opp-hz = /bits/ 64 <2553600000>;
+ opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>;
+ };
+ };
+
dummy-sink {
compatible = "arm,coresight-dummy-sink";
--
2.43.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V10 4/7] interconnect: qcom: icc-rpmh: Add dynamic icc node id support
2025-03-24 18:32 ` [PATCH V10 4/7] interconnect: qcom: icc-rpmh: Add dynamic icc node id support Raviteja Laggyshetty
@ 2025-03-26 17:41 ` Dmitry Baryshkov
0 siblings, 0 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2025-03-26 17:41 UTC (permalink / raw)
To: Raviteja Laggyshetty
Cc: Georgi Djakov, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio, Odelu Kukatla, Mike Tipton,
Jagadeesh Kona, Jeff Johnson, Sibi Sankar, linux-arm-msm,
linux-pm, devicetree, linux-kernel
On Mon, Mar 24, 2025 at 06:32:00PM +0000, Raviteja Laggyshetty wrote:
> Interconnect framework relies on static IDs for creating,
> linking and maintaning the topology. This dependency on static
> IDs prevents creating two instances of same provider. To overcome
> the dependency on static IDs, dynamic ID support is being added.
> To facilitate dynamic node ID support, the driver now uses
> node pointers for links instead of static node IDs and icc_node
> pointer is added as member in qcom_icc_node structure to track
> the node creation.
>
> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
> ---
> drivers/interconnect/qcom/icc-rpmh.c | 17 ++++++++++++++---
> drivers/interconnect/qcom/icc-rpmh.h | 5 +++++
> 2 files changed, 19 insertions(+), 3 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V10 5/7] interconnect: qcom: sa8775p: Add dynamic icc node id support
2025-03-24 18:32 ` [PATCH V10 5/7] interconnect: qcom: sa8775p: " Raviteja Laggyshetty
@ 2025-03-26 17:41 ` Dmitry Baryshkov
0 siblings, 0 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2025-03-26 17:41 UTC (permalink / raw)
To: Raviteja Laggyshetty
Cc: Georgi Djakov, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio, Odelu Kukatla, Mike Tipton,
Jagadeesh Kona, Jeff Johnson, Sibi Sankar, linux-arm-msm,
linux-pm, devicetree, linux-kernel
On Mon, Mar 24, 2025 at 06:32:01PM +0000, Raviteja Laggyshetty wrote:
> To facilitate dynamic id allocation, discard the static IDs
> from node data and set alloc_dyn_id in descriptor structure
> to indicate dynamic ID allocation. Update the topology to use
> node pointers for links instead of static IDs and forward declare
> the node pointer to avoid undefined references.
>
> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
> ---
> drivers/interconnect/qcom/sa8775p.c | 952 ++++++++++------------------
> 1 file changed, 347 insertions(+), 605 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V10 6/7] arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider
2025-03-24 18:32 ` [PATCH V10 6/7] arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider Raviteja Laggyshetty
@ 2025-03-26 17:41 ` Dmitry Baryshkov
0 siblings, 0 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2025-03-26 17:41 UTC (permalink / raw)
To: Raviteja Laggyshetty
Cc: Georgi Djakov, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio, Odelu Kukatla, Mike Tipton,
Jagadeesh Kona, Jeff Johnson, Sibi Sankar, linux-arm-msm,
linux-pm, devicetree, linux-kernel, Konrad Dybcio
On Mon, Mar 24, 2025 at 06:32:02PM +0000, Raviteja Laggyshetty wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SA8775P
> SoCs. L3 instances on this SoC are same as SM8250 and SC7280 SoCs.
> These SoCs use EPSS_L3_PERF register instead of REG_L3_VOTE register for
> programming the perf level. This is taken care in the data associated
> with the target specific compatible. Since, the HW is same in the all
> SoCs with EPSS support, using the same generic compatible for all.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V10 7/7] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
2025-03-24 18:32 ` [PATCH V10 7/7] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3 Raviteja Laggyshetty
@ 2025-03-26 17:42 ` Dmitry Baryshkov
0 siblings, 0 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2025-03-26 17:42 UTC (permalink / raw)
To: Raviteja Laggyshetty
Cc: Georgi Djakov, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio, Odelu Kukatla, Mike Tipton,
Jagadeesh Kona, Jeff Johnson, Sibi Sankar, linux-arm-msm,
linux-pm, devicetree, linux-kernel, Shivnandan Kumar
On Mon, Mar 24, 2025 at 06:32:03PM +0000, Raviteja Laggyshetty wrote:
> From: Jagadeesh Kona <quic_jkona@quicinc.com>
>
> Add OPP tables required to scale DDR and L3 per freq-domain
> on SA8775P platform.
>
> If a single OPP table is used for both CPU domains, then
> _allocate_opp_table() won't be invoked for CPU4 but instead
> CPU4 will be added as device under the CPU0 OPP table. Due
> to this, dev_pm_opp_of_find_icc_paths() won't be invoked for
> CPU4 device and hence CPU4 won't be able to independently scale
> it's interconnects. Both CPU0 and CPU4 devices will scale the
> same ICC path which can lead to one device overwriting the BW
> vote placed by other device. Hence CPU0 and CPU4 require separate
> OPP tables to allow independent scaling of DDR and L3 frequencies
> for each CPU domain, with the final DDR and L3 frequencies being
> an aggregate of both.
>
> Co-developed-by: Shivnandan Kumar <quic_kshivnan@quicinc.com>
> Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com>
> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 210 ++++++++++++++++++++++++++
> 1 file changed, 210 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V10 2/7] interconnect: core: Add dynamic id allocation support
2025-03-24 18:31 ` [PATCH V10 2/7] interconnect: core: Add dynamic id allocation support Raviteja Laggyshetty
@ 2025-04-14 9:57 ` Georgi Djakov
0 siblings, 0 replies; 14+ messages in thread
From: Georgi Djakov @ 2025-04-14 9:57 UTC (permalink / raw)
To: Raviteja Laggyshetty, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio, Odelu Kukatla, Mike Tipton,
Jagadeesh Kona
Cc: Jeff Johnson, Sibi Sankar, linux-arm-msm, linux-pm, devicetree,
linux-kernel
On 24.03.25 20:31, Raviteja Laggyshetty wrote:
> The current interconnect framework relies on static IDs for node
> creation and registration, which limits topologies with multiple
> instances of the same interconnect provider. To address this,
> introduce icc_node_create_dyn() and icc_link_nodes() APIs to
> dynamically allocate IDs for interconnect nodes during creation
> and link. This change removes the dependency on static IDs,
> allowing multiple instances of the same hardware, such as EPSS L3.
>
Hi Raviteja,
Thank you for working on this!
> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
> ---
> drivers/interconnect/core.c | 83 ++++++++++++++++++++++++++-
> include/linux/interconnect-provider.h | 12 ++++
> include/linux/interconnect.h | 3 +
> 3 files changed, 97 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c
> index 9d5404a07e8a..d4c40c2b3ec1 100644
> --- a/drivers/interconnect/core.c
> +++ b/drivers/interconnect/core.c
> @@ -20,6 +20,8 @@
>
> #include "internal.h"
>
> +#define ICC_DYN_ID_START 10000
> +
> #define CREATE_TRACE_POINTS
> #include "trace.h"
>
> @@ -826,7 +828,12 @@ static struct icc_node *icc_node_create_nolock(int id)
> if (!node)
> return ERR_PTR(-ENOMEM);
>
> - id = idr_alloc(&icc_idr, node, id, id + 1, GFP_KERNEL);
> + /* dynamic id allocation */
> + if (id == ICC_ALLOC_DYN_ID)
> + id = idr_alloc(&icc_idr, node, ICC_DYN_ID_START, 0, GFP_KERNEL);
> + else
> + id = idr_alloc(&icc_idr, node, id, id + 1, GFP_KERNEL);
> +
> if (id < 0) {
> WARN(1, "%s: couldn't get idr\n", __func__);
> kfree(node);
> @@ -838,6 +845,26 @@ static struct icc_node *icc_node_create_nolock(int id)
> return node;
> }
>
> +/**
> + * icc_node_create_dyn() - create a node with dynamic id
> + * @id: node id
This function does not take any arguments. Please remove.
> + *
> + * Return: icc_node pointer on success, or ERR_PTR() on error
> + */
> +struct icc_node *icc_node_create_dyn(void)
> +{
> + struct icc_node *node;
> +
> + mutex_lock(&icc_lock);
> +
> + node = icc_node_create_nolock(ICC_ALLOC_DYN_ID);
> +
> + mutex_unlock(&icc_lock);
> +
> + return node;
> +}
> +EXPORT_SYMBOL_GPL(icc_node_create_dyn);
BR,
Georgi
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V10 3/7] interconnect: qcom: Add multidev EPSS L3 support
2025-03-24 18:31 ` [PATCH V10 3/7] interconnect: qcom: Add multidev EPSS L3 support Raviteja Laggyshetty
@ 2025-04-14 9:58 ` Georgi Djakov
0 siblings, 0 replies; 14+ messages in thread
From: Georgi Djakov @ 2025-04-14 9:58 UTC (permalink / raw)
To: Raviteja Laggyshetty, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio, Odelu Kukatla, Mike Tipton,
Jagadeesh Kona
Cc: Jeff Johnson, Sibi Sankar, linux-arm-msm, linux-pm, devicetree,
linux-kernel
On 24.03.25 20:31, Raviteja Laggyshetty wrote:
> EPSS on SA8775P has two instances, necessitating the creation of two
> device nodes with different compatibles due to the unique ICC node ID
> and name limitations in the interconnect framework. Add multidevice
> support for the OSM-L3 provider to dynamically obtain unique node IDs
> and register with the framework.
> EPSS topology includes a single master-slave pair within the same
> provider, the node linking logic is simplified by directly connecting
> the master node to the slave node.
>
> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
> ---
> drivers/interconnect/qcom/osm-l3.c | 36 ++++++++++--------------------
> 1 file changed, 12 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
> index 6a656ed44d49..43e67d2116b9 100644
> --- a/drivers/interconnect/qcom/osm-l3.c
> +++ b/drivers/interconnect/qcom/osm-l3.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> #include <linux/args.h>
> @@ -48,16 +49,10 @@ struct qcom_osm_l3_icc_provider {
> /**
> * struct qcom_osm_l3_node - Qualcomm specific interconnect nodes
> * @name: the node name used in debugfs
> - * @links: an array of nodes where we can go next while traversing
> - * @id: a unique node identifier
> - * @num_links: the total number of @links
> * @buswidth: width of the interconnect between a node and the bus
> */
> struct qcom_osm_l3_node {
> const char *name;
> - u16 links[OSM_L3_MAX_LINKS];
Please remove also the #define for OSM_L3_MAX_LINKS, as it's unused now.
> - u16 id;
> - u16 num_links;
> u16 buswidth;
> };
>
BR,
Georgi
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2025-04-14 9:58 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2025-03-24 18:31 [PATCH V10 0/7]Add EPSS L3 provider support on SA8775P SoC Raviteja Laggyshetty
2025-03-24 18:31 ` [PATCH V10 1/7] dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P Raviteja Laggyshetty
2025-03-24 18:31 ` [PATCH V10 2/7] interconnect: core: Add dynamic id allocation support Raviteja Laggyshetty
2025-04-14 9:57 ` Georgi Djakov
2025-03-24 18:31 ` [PATCH V10 3/7] interconnect: qcom: Add multidev EPSS L3 support Raviteja Laggyshetty
2025-04-14 9:58 ` Georgi Djakov
2025-03-24 18:32 ` [PATCH V10 4/7] interconnect: qcom: icc-rpmh: Add dynamic icc node id support Raviteja Laggyshetty
2025-03-26 17:41 ` Dmitry Baryshkov
2025-03-24 18:32 ` [PATCH V10 5/7] interconnect: qcom: sa8775p: " Raviteja Laggyshetty
2025-03-26 17:41 ` Dmitry Baryshkov
2025-03-24 18:32 ` [PATCH V10 6/7] arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider Raviteja Laggyshetty
2025-03-26 17:41 ` Dmitry Baryshkov
2025-03-24 18:32 ` [PATCH V10 7/7] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3 Raviteja Laggyshetty
2025-03-26 17:42 ` Dmitry Baryshkov
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