[PATCH v2 0/2] drm/msm/a6xx: use correct timestamp counter on A750 GPU

[PATCH v2 0/2] drm/msm/a6xx: use correct timestamp counter on A750 GPU

[Neil Armstrong]

The A750 uses a different counter register as used on the downstream
driver:

static u64 gen7_9_0_read_alwayson(struct adreno_device *adreno_dev)
{
...
	/* Always use the GMU AO counter when doing a AHB read */
	gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_HI, &hi);
	gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_LO, &lo);
...
}

gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_LO		0x1f880
gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_HI		0x1f881

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Changes in v2:
- Fix swapped H/L registers in XML
- Link to v1: https://patch.msgid.link/20260908-topic-sm8650-gmu-a750-timestamp-reg-v1-0-284880d6e68b@linaro.org

---
Neil Armstrong (2):
      drm/msm/a6xx: Add CX AO Counter registers used for a750 GPUs
      drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs

 drivers/gpu/drm/msm/adreno/a6xx_gpu.c             | 12 +++++++++---
 drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml |  2 ++
 2 files changed, 11 insertions(+), 3 deletions(-)
---
base-commit: df2908090cda368b01ff43709f51890076c56157
change-id: 20260908-topic-sm8650-gmu-a750-timestamp-reg-2e7575e6279d

Best regards,
--  
Neil Armstrong <neil.armstrong@linaro.org>

[PATCH v2 1/2] drm/msm/a6xx: Add CX AO Counter registers used for a750 GPUs

[Neil Armstrong]

The a750 uses the CX AO Counters instead of the GMU_ALWAYS_ON_COUNTER
register on A6xx and other A7xx GPUs.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
index 33404eb18fd0..b3082738c99d 100644
--- a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
+++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
@@ -141,6 +141,8 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
 	<reg32 offset="0x1f9f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
 	<reg32 offset="0x1f957" name="GMU_LLM_GLM_SLEEP_CTRL"/>
 	<reg32 offset="0x1f958" name="GMU_LLM_GLM_SLEEP_STATUS"/>
+	<reg32 offset="0x1f880" name="GMU_CX_AO_COUNTER_L" variants="A7XX"/>
+	<reg32 offset="0x1f881" name="GMU_CX_AO_COUNTER_H" variants="A7XX"/>
 	<reg32 offset="0x1f888" name="GMU_ALWAYS_ON_COUNTER_L" variants="A6XX-A7XX"/>
 	<reg32 offset="0x1f840" name="GMU_ALWAYS_ON_COUNTER_L" variants="A8XX-"/>
 	<reg32 offset="0x1f889" name="GMU_ALWAYS_ON_COUNTER_H" variants="A6XX-A7XX"/>

-- 
2.34.1

[PATCH v2 2/2] drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs

[Neil Armstrong]

The a750 uses the GMU CX AO Counters instead of the GMU_ALWAYS_ON_COUNTER
register on A6xx and other A7xx GPUs, use it when running a A750 GPU.

The GMU_ALWAYS_ON_COUNTER at offset 0x1f888 doesn't seem to exist
on the SM8650 A750 GMU and returns 0, but the CX AO counter at offset
0x1f880 returns some proper timestamp data.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index f9de9329dee3..081e79ea4652 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -23,9 +23,15 @@ static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu)
 	u64 count_hi, count_lo, temp;
 
 	do {
-		count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
-		count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
-		temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
+		if (adreno_is_a750_family(adreno_gpu)) {
+			count_hi = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
+			count_lo = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_L);
+			temp = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
+		} else {
+			count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
+			count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
+			temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
+		}
 	} while (unlikely(count_hi != temp));
 
 	return (count_hi << 32) | count_lo;

-- 
2.34.1

Re: [PATCH v2 0/2] drm/msm/a6xx: use correct timestamp counter on A750 GPU

[Neil Armstrong]

Hi Rob, Akhil,

On 9/9/26 15:07, Neil Armstrong wrote:
> The A750 uses a different counter register as used on the downstream
> driver:
> 
> static u64 gen7_9_0_read_alwayson(struct adreno_device *adreno_dev)
> {
> ...
> 	/* Always use the GMU AO counter when doing a AHB read */
> 	gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_HI, &hi);
> 	gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_LO, &lo);
> ...
> }
> 
> gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_LO		0x1f880
> gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_HI		0x1f881
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> Changes in v2:
> - Fix swapped H/L registers in XML
> - Link to v1: https://patch.msgid.link/20260908-topic-sm8650-gmu-a750-timestamp-reg-v1-0-284880d6e68b@linaro.org

Gentle ping for review

Thanks,
Neil

> 
> ---
> Neil Armstrong (2):
>        drm/msm/a6xx: Add CX AO Counter registers used for a750 GPUs
>        drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs
> 
>   drivers/gpu/drm/msm/adreno/a6xx_gpu.c             | 12 +++++++++---
>   drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml |  2 ++
>   2 files changed, 11 insertions(+), 3 deletions(-)
> ---
> base-commit: df2908090cda368b01ff43709f51890076c56157
> change-id: 20260908-topic-sm8650-gmu-a750-timestamp-reg-2e7575e6279d
> 
> Best regards,
> --
> Neil Armstrong <neil.armstrong@linaro.org>
> 

Re: [PATCH v2 0/2] drm/msm/a6xx: use correct timestamp counter on A750 GPU

[Akhil P Oommen]

On 9/9/2026 6:37 PM, Neil Armstrong wrote:
> The A750 uses a different counter register as used on the downstream
> driver:
> 
> static u64 gen7_9_0_read_alwayson(struct adreno_device *adreno_dev)
> {
> ...
> 	/* Always use the GMU AO counter when doing a AHB read */
> 	gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_HI, &hi);
> 	gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_LO, &lo);
> ...
> }
> 
> gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_LO		0x1f880
> gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_HI		0x1f881
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>

This is correct. There was a register shuffling in the gmu_cx block in a750 and another shuffling later in gen8 family.

It is a good idea to review other GMU_CX* register offsets with KGSL. Also, please consider including a fixes tag.

-Akhil.


> ---
> Changes in v2:
> - Fix swapped H/L registers in XML
> - Link to v1: https://patch.msgid.link/20260908-topic-sm8650-gmu-a750-timestamp-reg-v1-0-284880d6e68b@linaro.org
> 
> ---
> Neil Armstrong (2):
>       drm/msm/a6xx: Add CX AO Counter registers used for a750 GPUs
>       drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs
> 
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c             | 12 +++++++++---
>  drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml |  2 ++
>  2 files changed, 11 insertions(+), 3 deletions(-)
> ---
> base-commit: df2908090cda368b01ff43709f51890076c56157
> change-id: 20260908-topic-sm8650-gmu-a750-timestamp-reg-2e7575e6279d
> 
> Best regards,
> --  
> Neil Armstrong <neil.armstrong@linaro.org>

Re: [PATCH v2 0/2] drm/msm/a6xx: use correct timestamp counter on A750 GPU

[Neil Armstrong]

On 9/15/26 23:20, Akhil P Oommen wrote:
> 
> 
> On 9/9/2026 6:37 PM, Neil Armstrong wrote:
>> The A750 uses a different counter register as used on the downstream
>> driver:
>>
>> static u64 gen7_9_0_read_alwayson(struct adreno_device *adreno_dev)
>> {
>> ...
>> 	/* Always use the GMU AO counter when doing a AHB read */
>> 	gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_HI, &hi);
>> 	gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_LO, &lo);
>> ...
>> }
>>
>> gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_LO		0x1f880
>> gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_HI		0x1f881
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> 
> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> 
> This is correct. There was a register shuffling in the gmu_cx block in a750 and another shuffling later in gen8 family.
> 
> It is a good idea to review other GMU_CX* register offsets with KGSL. Also, please consider including a fixes tag.

OK thanks,
Neil

> 
> -Akhil.
> 
> 
>> ---
>> Changes in v2:
>> - Fix swapped H/L registers in XML
>> - Link to v1: https://patch.msgid.link/20260908-topic-sm8650-gmu-a750-timestamp-reg-v1-0-284880d6e68b@linaro.org
>>
>> ---
>> Neil Armstrong (2):
>>        drm/msm/a6xx: Add CX AO Counter registers used for a750 GPUs
>>        drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs
>>
>>   drivers/gpu/drm/msm/adreno/a6xx_gpu.c             | 12 +++++++++---
>>   drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml |  2 ++
>>   2 files changed, 11 insertions(+), 3 deletions(-)
>> ---
>> base-commit: df2908090cda368b01ff43709f51890076c56157
>> change-id: 20260908-topic-sm8650-gmu-a750-timestamp-reg-2e7575e6279d
>>
>> Best regards,
>> --
>> Neil Armstrong <neil.armstrong@linaro.org>
>