Re: [PATCH v2 2/6] clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL

["Satya Priya Kakitapalli (Temp)" <quic_skakitap@quicinc.com>]

On 7/6/2024 7:09 PM, Konrad Dybcio wrote:
> On 2.07.2024 5:50 PM, Satya Priya Kakitapalli wrote:
>> The Zonda PLL has a 16 bit signed alpha and in the cases where the alpha
>> value is greater than 0.5, the L value needs to be adjusted accordingly.
>> Thus update the logic for the same.
>>
>> Also, fix zonda set_rate failure when PLL is disabled. Currently,
>> clk_zonda_pll_set_rate polls for the PLL to lock even if the PLL is
>> disabled. However, if the PLL is disabled then LOCK_DET will never
>> assert and we'll return an error. There is no reason to poll LOCK_DET
>> if the PLL is already disabled, so skip polling in this case.
>>
>> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
>> ---
> [...]
>
>> @@ -2077,9 +2089,15 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
>>   	if (ret < 0)
>>   		return ret;
>>   
>> +	if (a & BIT(15))
>> +		zonda_pll_adjust_l_val(rate, prate, &l);
> A random check for a seemingly random, undocumented bit only confuses the reader


Sure, I'll define a macro for this.


Thanks.