From: Paolo Bonzini <pbonzini@redhat.com>
To: "Huang, Kai" <kai.huang@intel.com>,
"thomas.lendacky@amd.com" <thomas.lendacky@amd.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>
Cc: "Christopherson, Sean J" <sean.j.christopherson@intel.com>,
"stable@vger.kernel.org" <stable@vger.kernel.org>
Subject: Re: [PATCH v2] KVM: x86: use CPUID to locate host page table reserved bits
Date: Wed, 11 Dec 2019 10:07:55 +0100 [thread overview]
Message-ID: <62438ac9-e186-32a7-d12f-5806054d56b2@redhat.com> (raw)
In-Reply-To: <3efabf0da4954239662e90ea08d99212a654977a.camel@intel.com>
On 11/12/19 01:11, Huang, Kai wrote:
>> kvm_get_shadow_phys_bits() must be conservative in that:
>>
>> 1) if a bit is reserved it _can_ return a value higher than its index
>>
>> 2) if a bit is used by the processor (for physical address or anything
>> else) it _must_ return a value higher than its index.
>>
>> In the SEV case we're not obeying (2), because the function returns 43
>> when the C bit is bit 47. The patch fixes that.
> Could we guarantee that C-bit is always below bits reported by CPUID?
That's a question for AMD. :) The C bit can move (and probably will,
otherwise they wouldn't have bothered adding it to CPUID) in future
generations of the processor.
Paolo
next prev parent reply other threads:[~2019-12-11 9:08 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-04 15:40 Paolo Bonzini
2019-12-04 15:48 ` Sean Christopherson
2019-12-10 9:19 ` Paolo Bonzini
2019-12-10 15:37 ` Sean Christopherson
2019-12-04 15:57 ` Tom Lendacky
2019-12-10 3:53 ` Huang, Kai
2019-12-10 9:18 ` Paolo Bonzini
2019-12-10 9:17 ` Paolo Bonzini
2019-12-11 0:11 ` Huang, Kai
2019-12-11 9:07 ` Paolo Bonzini [this message]
2019-12-11 20:48 ` Tom Lendacky
2019-12-11 23:16 ` Huang, Kai
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