[PATCH v2 0/2] arm64: dts: freescale: Re-enable A72 cluster on i.MX8QM boards

[PATCH v2 0/2] arm64: dts: freescale: Re-enable A72 cluster on i.MX8QM boards

[Peng Fan (OSS)]

The ERR050104 cache coherency workaround for the NXP i.MX8QuadMax and
i.MX8QuadPlus SoCs has been merged upstream as commit d44e08dab27d
("arm64: errata: Add NXP i.MX8QM/8QP workaround for A53 cache coherency
issue").

The workaround addresses a hardware defect where the upper address bits
of the ARADDR and ACADDR buses within the Cortex-A53 subsystem were
incorrectly connected, causing TLBI and IC maintenance operations
exchanged between the A53 and A72 clusters to be corrupted.

Before the software workaround was available, affected board DTS files
worked around this at the DT level by removing the Cortex-A72 CPU nodes
(cpu@100, cpu@101), the cpu-map topology, and associated cpu1-thermal
zones, effectively running the SoC as a single A53-only cluster.

With the kernel-side fix now in place, this series removes the DT-level
workarounds and restores full SMP support with both A53 and A72 clusters.
The PMIC thermal cooling-device maps are also updated to include A72_0
and A72_1 so both clusters participate in thermal management.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Changes in v2:
- patch 1: update PMIC thermal cooling-device map to include A72_0/A72_1
- patch 2: replace manual DT node deletion removal with a proper revert
  of commit 5d20f1ccb339 ("arm64: dts: imx8qm-tqma8qm-mba8x: Disable
  Cortex-A72 cluster"), which also restores the cpu1-thermal zone in
  imx8qm-tqma8qm-mba8x.dts as originally intended
- Link to v1: https://patch.msgid.link/20261022-8qm-v1-0-2a597cb3debd@nxp.com

---
Peng Fan (2):
      arm64: dts: imx8qm-mek: Re-enable A72 cluster after ERR050104 workaround
      Revert "arm64: dts: imx8qm-tqma8qm-mba8x: Disable Cortex-A72 cluster"

 arch/arm64/boot/dts/freescale/imx8qm-mek.dts       | 14 ++------
 .../boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts    | 39 ++++++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi  | 13 ++------
 3 files changed, 45 insertions(+), 21 deletions(-)
---
base-commit: 4403278e4ea2f654f8130a5c03eb8b4516a0f201
change-id: 20261022-8qm-875d0b4b3e7d

Best regards,
--  
Peng Fan <peng.fan@nxp.com>

[PATCH v2 1/2] arm64: dts: imx8qm-mek: Re-enable A72 cluster after ERR050104 workaround

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

The ERR050104 cache coherency workaround for i.MX8QM/8QP has been
merged upstream (d44e08dab27d). The workaround addresses the incorrect
wiring of upper address bits in the A53 subsystem that corrupts TLBI and
IC maintenance operations between A53 and A72 clusters.

Previously the A72 CPUs (cpu@100, cpu@101), the cpu-map, and the
cpu1-thermal zone were removed from the MEK board DT to avoid incorrect
cross-cluster coherency maintenance. With the software workaround in
place, restore all deleted nodes and add A72_0/A72_1 to the PMIC thermal
cooling-device map so both clusters are properly managed.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 9e49ac377162b..d346958965026 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -17,16 +17,6 @@ chosen {
 		stdout-path = &lpuart0;
 	};
 
-	cpus {
-		/delete-node/ cpu-map;
-		/delete-node/ cpu@100;
-		/delete-node/ cpu@101;
-	};
-
-	thermal-zones {
-		/delete-node/ cpu1-thermal;
-	};
-
 	memory@80000000 {
 		device_type = "memory";
 		reg = <0x00000000 0x80000000 0 0x40000000>;
@@ -995,7 +985,9 @@ map0 {
 				cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 						 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 						 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-						 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+						 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						 <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						 <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 			};
 		};
 	};

-- 
2.34.1

Re: [PATCH v2 1/2] arm64: dts: imx8qm-mek: Re-enable A72 cluster after ERR050104 workaround

[Alexander Stein]

Hi Peng,

Am Freitag, 23. Oktober 2026, 04:56:59 Mitteleuropäische Sommerzeit schrieb Peng Fan (OSS):
> From: Peng Fan <peng.fan@nxp.com>
> 
> The ERR050104 cache coherency workaround for i.MX8QM/8QP has been
> merged upstream (d44e08dab27d). The workaround addresses the incorrect
> wiring of upper address bits in the A53 subsystem that corrupts TLBI and
> IC maintenance operations between A53 and A72 clusters.
> 
> Previously the A72 CPUs (cpu@100, cpu@101), the cpu-map, and the
> cpu1-thermal zone were removed from the MEK board DT to avoid incorrect
> cross-cluster coherency maintenance. With the software workaround in
> place, restore all deleted nodes and add A72_0/A72_1 to the PMIC thermal
> cooling-device map so both clusters are properly managed.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Maybe it's woth mentioning you are essentially also reverting commit
bce07345481cd ("arm64: dts: imx8qm-mek: delete A72 thermal zone").

But either way:
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Best regards
Alexander

> ---
>  arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 14 +++-----------
>  1 file changed, 3 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> index 9e49ac377162b..d346958965026 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> @@ -17,16 +17,6 @@ chosen {
>  		stdout-path = &lpuart0;
>  	};
>  
> -	cpus {
> -		/delete-node/ cpu-map;
> -		/delete-node/ cpu@100;
> -		/delete-node/ cpu@101;
> -	};
> -
> -	thermal-zones {
> -		/delete-node/ cpu1-thermal;
> -	};
> -
>  	memory@80000000 {
>  		device_type = "memory";
>  		reg = <0x00000000 0x80000000 0 0x40000000>;
> @@ -995,7 +985,9 @@ map0 {
>  				cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>  						 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>  						 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> -						 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +						 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +						 <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +						 <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>  			};
>  		};
>  	};
> 
> 


-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/

[PATCH v2 2/2] Revert "arm64: dts: imx8qm-tqma8qm-mba8x: Disable Cortex-A72 cluster"

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

The ERR050104 cache coherency workaround for i.MX8QM/8QP has been
merged upstream (d44e08dab27d). The workaround addresses the incorrect
wiring of upper address bits in the A53 subsystem that corrupts TLBI
and IC maintenance operations between A53 and A72 clusters.

With the software workaround in place, the DT-level workaround applied
by commit 5d20f1ccb339 ("arm64: dts: imx8qm-tqma8qm-mba8x: Disable
Cortex-A72 cluster") is no longer needed.

This reverts commit 5d20f1ccb339.

Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 .../boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts    | 39 ++++++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi  | 13 ++------
 2 files changed, 42 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts
index ab3b244b684fd..bf972010a88e7 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts
@@ -298,6 +298,45 @@ map3 {
 				};
 			};
 		};
+
+		cpu1-thermal {
+			trips {
+				soc_active1_0: trip-active0 {
+					temperature = <40000>;
+					hysteresis = <5000>;
+					type = "active";
+				};
+
+				soc_active1_1: trip-active1 {
+					temperature = <48000>;
+					hysteresis = <3000>;
+					type = "active";
+				};
+
+				soc_active1_2: trip-active2 {
+					temperature = <60000>;
+					hysteresis = <10000>;
+					type = "active";
+				};
+			};
+
+			cooling-maps {
+				map1 {
+					trip = <&soc_active1_0>;
+					cooling-device = <&fan0 1 1>;
+				};
+
+				map2 {
+					trip = <&soc_active1_1>;
+					cooling-device = <&fan0 2 2>;
+				};
+
+				map3 {
+					trip = <&soc_active1_2>;
+					cooling-device = <&fan0 3 3>;
+				};
+			};
+		};
 	};
 };
 
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi
index f0e398eb2aad7..d94605c999915 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi
@@ -15,13 +15,6 @@ / {
 	model = "TQ-Systems i.MX8QM TQMa8QM";
 	compatible = "tq,imx8qm-tqma8qm", "fsl,imx8qm";
 
-	/* Due to missing workaround for ERR050104 */
-	cpus {
-		/delete-node/ cpu-map;
-		/delete-node/ cpu@100;
-		/delete-node/ cpu@101;
-	};
-
 	memory@80000000 {
 		device_type = "memory";
 		/*
@@ -181,8 +174,6 @@ &mu2_m0 {
 };
 
 &thermal_zones {
-	/delete-node/ cpu1-thermal;
-
 	pmic0-thermal {
 		polling-delay-passive = <250>;
 		polling-delay = <2000>;
@@ -208,7 +199,9 @@ map0 {
 					<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 					<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 					<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-					<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 			};
 		};
 	};

-- 
2.34.1