Re: [PATCH v3] x86/boot: Avoid writing to cr4 twice in startup_64()

["H. Peter Anvin" <hpa@zytor.com>]

On 2025-07-15 11:16, Khalid Ali wrote:
> From: Khalid Ali <khaliidcaliy@gmail.com>
> 
> When Initializing cr4 bit PSE and PGE, cr4 is written twice for	
> each bit. This is redundancy.
> 
> Instead, set both bits first and write CR4 once, avoiding redundant
> writes. This makes consistent with cr0 writes, which is set bits and
> write once.
> 
> Signed-off-by: Khalid Ali <khaliidcaliy@gmail.com>
> ---
>   arch/x86/kernel/head_64.S | 7 ++-----
>   1 file changed, 2 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
> index 4390a28f7dad..dfb5390e5c9a 100644
> --- a/arch/x86/kernel/head_64.S
> +++ b/arch/x86/kernel/head_64.S
> @@ -222,12 +222,9 @@ SYM_INNER_LABEL(common_startup_64, SYM_L_LOCAL)
>   
>   	/* Even if ignored in long mode, set PSE uniformly on all logical CPUs. */
>   	btsl	$X86_CR4_PSE_BIT, %ecx
> -	movq	%rcx, %cr4
> -
> -	/*
> -	 * Set CR4.PGE to re-enable global translations.
> -	 */
> +	/* Set CR4.PGE to re-enable global translations. */
>   	btsl	$X86_CR4_PGE_BIT, %ecx
> +	
>   	movq	%rcx, %cr4
>   
>   #ifdef CONFIG_SMP

The double write is intentional:

         /*
          * Create a mask of CR4 bits to preserve. Omit PGE in order to 
flush
          * global 1:1 translations from the TLBs.
          *
          * From the SDM:
          * "If CR4.PGE is changing from 0 to 1, there were no global TLB
          *  entries before the execution; if CR4.PGE is changing from 1 
to 0,
          *  there will be no global TLB entries after the execution."
          */
         movl    $(X86_CR4_PAE | X86_CR4_LA57), %edx