From: Andrew Cooper <andrew.cooper3@citrix.com>
To: khaliidcaliy@gmail.com
Cc: ardb@kernel.org, bp@alien8.de, brgerst@gmail.com,
dave.hansen@linux.intel.com, hpa@zytor.com,
linux-kernel@vger.kernel.org, mingo@redhat.com,
tglx@linutronix.de, ubizjak@gmail.com, x86@kernel.org
Subject: Re: [PATCH v3] x86/boot: Avoid writing to cr4 twice in startup_64()
Date: Tue, 15 Jul 2025 22:21:20 +0100 [thread overview]
Message-ID: <927f2b0a-7e64-40f2-9773-cba9b1d328a5@citrix.com> (raw)
In-Reply-To: <20250715181709.1040-1-khaliidcaliy@gmail.com>
> diff
> <https://lore.kernel.org/lkml/20250715181709.1040-1-khaliidcaliy@gmail.com/#iZ31arch:x86:kernel:head_64.S>
> --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index
> 4390a28f7dad..dfb5390e5c9a 100644 --- a/arch/x86/kernel/head_64.S +++
> b/arch/x86/kernel/head_64.S @@ -222,12 +222,9 @@
> SYM_INNER_LABEL(common_startup_64, SYM_L_LOCAL)
> /* Even if ignored in long mode, set PSE uniformly on all logical CPUs. */
> btsl $X86_CR4_PSE_BIT, %ecx
> - movq %rcx, %cr4 - - /* - * Set CR4.PGE to re-enable global
> translations. - */ + /* Set CR4.PGE to re-enable global translations. */ btsl $X86_CR4_PGE_BIT, %ecx
> + movq %rcx, %cr4
The comments are at best misleading, but you've broken the TLB flush
being performed which depends on the double write.
This logic is intentionally performing a write with CR4.PGE=0 followed
by one with CR4.PGE=1 to flush all global mappings.
~Andrew
next prev parent reply other threads:[~2025-07-15 21:21 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-15 18:16 Khalid Ali
2025-07-15 18:45 ` Nikolay Borisov
2025-07-15 19:05 ` [tip: x86/cleanups] x86/boot: Avoid redundant %cr4 write " tip-bot2 for Khalid Ali
2025-07-15 20:30 ` [PATCH v3] x86/boot: Avoid writing to cr4 twice " H. Peter Anvin
2025-07-15 20:31 ` H. Peter Anvin
2025-07-15 21:21 ` Andrew Cooper [this message]
2025-07-16 1:45 ` Borislav Petkov
2025-07-16 9:07 ` Khalid Ali
2025-07-16 13:27 ` Borislav Petkov
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