From: Dan Williams <dan.j.williams@intel.com>
To: "Huang, Ying" <ying.huang@intel.com>,
Dan Williams <dan.j.williams@intel.com>
Cc: Dave Jiang <dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Davidlohr Bueso <dave@stgolabs.net>,
"Gregory Price" <gourry@gourry.net>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Alejandro Lucero <alucerop@amd.com>,
Ben Cheatham <benjamin.cheatham@amd.com>
Subject: Re: [PATCH 2/5] cxl: Rename CXL_DECODER_HOSTONLYMEM/DEVMEM
Date: Fri, 18 Oct 2024 14:17:51 -0700 [thread overview]
Message-ID: <6712d07f3300b_10a03294bd@dwillia2-mobl3.amr.corp.intel.com.notmuch> (raw)
In-Reply-To: <87bjzi6iig.fsf@yhuang6-desk2.ccr.corp.intel.com>
Huang, Ying wrote:
> Hi, Dan,
>
> Dan Williams <dan.j.williams@intel.com> writes:
>
> > Huang Ying wrote:
> >> Previously, CXL type3 devices (memory expanders) use host only
> >> coherence (HDM-H), while CXL type2 devices (accelerators) use dev
> >> coherence (HDM-D). So the name of the target device type of a cxl
> >> decoder is CXL_DECODER_HOSTONLYMEM for type3 devices and
> >> CXL_DECODER_DEVMEM for type2 devices. However, this isn't true
> >> anymore. CXL type3 devices can use dev coherence + back
> >> invalidation (HDM-DB) too.
> >>
> >> To avoid confusion between the device type and coherence, the patch
> >> renames CXL_DECODER_HOSTONLYMEM/DEVMEM to CXL_DECODER_EXPANDER/ACCEL.
> >
> > This does not look like an improvement to me. Type-3 devices that
> > support back-invalidate are DEVMEM devices. The device plays a role in
> > the coherence.
> >
> > Your explanation is the reverse of this commit:
> >
> > 5aa39a9165cf cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}
> >
> > ...so I am confused what motivated this rename?
>
> Sorry, I am confused about the target_type and coherence and forgot to
> check the history. In some places, current kernel still hints
> target_type (CXL_DECODER_HOSTONLYMEM/DEVMEM) as expander/accelerator.
> Should we change them to avoid confusion in the future?
>
> $ grep expander -r drivers/cxl/
> drivers/cxl/cxl.h:346: * @target_type: accelerator vs expander (type2 vs type3) selector
> drivers/cxl/core/region.c:2450: * @type: select whether this is an expander or accelerator (type-2 or type-3)
> drivers/cxl/core/port.c:141: return sysfs_emit(buf, "expander\n");
>
> The last one is
>
> static ssize_t target_type_show(struct device *dev,
> struct device_attribute *attr, char *buf)
> {
> struct cxl_decoder *cxld = to_cxl_decoder(dev);
>
> switch (cxld->target_type) {
> case CXL_DECODER_DEVMEM:
> return sysfs_emit(buf, "accelerator\n");
> case CXL_DECODER_HOSTONLYMEM:
> return sysfs_emit(buf, "expander\n");
> }
> return -ENXIO;
> }
> static DEVICE_ATTR_RO(target_type);
>
> for decoder device. This is a testing ABI documented in,
>
> Documentation/ABI/testing/sysfs-bus-cxl
>
> Is it OK to change this?
No, why does it need to change?
It is unfortunate, but ABI's are forever. The place to clarify that this
decoder is participating in HDM-D[B] vs HDM-H protocol rather than being
an "accelerator" or "expander" device would be in user tooling like
cxl-cli. sysfs is just a transport, not a UI.
next prev parent reply other threads:[~2024-10-18 21:17 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-15 6:57 [PATCH 0/5] cxl: Some preparation work for type2 accelerators support Huang Ying
2024-10-15 6:57 ` [PATCH 1/5] cxl: Rename ACPI_CEDT_CFMWS_RESTRICT_TYPE2/TYPE3 Huang Ying
2024-10-15 6:57 ` [PATCH 2/5] cxl: Rename CXL_DECODER_HOSTONLYMEM/DEVMEM Huang Ying
2024-10-17 22:21 ` Dan Williams
2024-10-18 6:18 ` Huang, Ying
2024-10-18 21:17 ` Dan Williams [this message]
2024-10-21 4:40 ` Huang, Ying
2024-10-15 6:57 ` [PATCH 3/5] cxl: Separate coherence from target type Huang Ying
2024-10-17 22:25 ` Dan Williams
2024-10-15 6:57 ` [PATCH 4/5] cxl: Set type of region to that of the first endpoint Huang Ying
2024-10-17 22:33 ` Dan Williams
2024-10-18 6:50 ` Huang, Ying
2024-10-18 21:19 ` Dan Williams
2024-10-21 6:33 ` Huang, Ying
2024-10-21 9:47 ` Alejandro Lucero Palau
2024-10-15 6:57 ` [PATCH 5/5] cxl: Avoid to create dax regions for type2 accelerators Huang Ying
2024-10-15 8:51 ` Alejandro Lucero Palau
2024-10-17 6:29 ` Huang, Ying
2024-10-17 7:27 ` Alejandro Lucero Palau
2024-10-17 7:48 ` Huang, Ying
2024-10-18 9:57 ` Jonathan Cameron
2024-10-21 11:37 ` Huang, Ying
2024-10-17 23:15 ` Dan Williams
2024-10-21 11:52 ` Huang, Ying
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