* [PATCH V2] clk: sprd: Fix thm_parents incorrect configuration
@ 2023-08-24 9:26 Zhifeng Tang
2023-09-11 20:31 ` Stephen Boyd
0 siblings, 1 reply; 3+ messages in thread
From: Zhifeng Tang @ 2023-08-24 9:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Orson Zhai, Baolin Wang,
Chunyan Zhang, Zhifeng Tang, Cixi Geng
Cc: linux-clk, linux-kernel, Zhifeng Tang, Wenming Wu
The thm*_clk have two clock sources 32k and 250k,excluding 32m.
Fixes: af3bd36573e3 ("clk: sprd: Add clocks support for UMS512")
Signed-off-by: Zhifeng Tang <zhifeng.tang@unisoc.com>
Acked-by: Chunyan Zhang <zhang.lyra@gmail.com>
Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>
---
V2: add Fixes tag.
---
drivers/clk/sprd/ums512-clk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sprd/ums512-clk.c b/drivers/clk/sprd/ums512-clk.c
index fc25bdd85e4e..f43bb10bd5ae 100644
--- a/drivers/clk/sprd/ums512-clk.c
+++ b/drivers/clk/sprd/ums512-clk.c
@@ -800,7 +800,7 @@ static SPRD_MUX_CLK_DATA(uart1_clk, "uart1-clk", uart_parents,
0x250, 0, 3, UMS512_MUX_FLAG);
static const struct clk_parent_data thm_parents[] = {
- { .fw_name = "ext-32m" },
+ { .fw_name = "ext-32k" },
{ .hw = &clk_250k.hw },
};
static SPRD_MUX_CLK_DATA(thm0_clk, "thm0-clk", thm_parents,
--
2.17.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH V2] clk: sprd: Fix thm_parents incorrect configuration
2023-08-24 9:26 [PATCH V2] clk: sprd: Fix thm_parents incorrect configuration Zhifeng Tang
@ 2023-09-11 20:31 ` Stephen Boyd
0 siblings, 0 replies; 3+ messages in thread
From: Stephen Boyd @ 2023-09-11 20:31 UTC (permalink / raw)
To: Baolin Wang, Chunyan Zhang, Cixi Geng, Michael Turquette,
Orson Zhai, Zhifeng Tang
Cc: linux-clk, linux-kernel, Zhifeng Tang, Wenming Wu
Quoting Zhifeng Tang (2023-08-24 02:26:24)
> The thm*_clk have two clock sources 32k and 250k,excluding 32m.
>
> Fixes: af3bd36573e3 ("clk: sprd: Add clocks support for UMS512")
> Signed-off-by: Zhifeng Tang <zhifeng.tang@unisoc.com>
> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com>
> Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>
> ---
Applied to clk-fixes
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH V2] clk: sprd: Fix thm_parents incorrect configuration
@ 2023-08-24 7:29 Zhifeng Tang
0 siblings, 0 replies; 3+ messages in thread
From: Zhifeng Tang @ 2023-08-24 7:29 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Orson Zhai, Baolin Wang,
Chunyan Zhang, Zhifeng Tang, Cixi Geng
Cc: linux-clk, linux-kernel, Zhifeng Tang, Wenming Wu
The thm*_clk have two clock sources 32k and 250k,excluding 32m.
Fixes: af3bd36573e3 ("clk: sprd: Add clocks support for UMS512")
---
V2: add Fixes tag.
---
Signed-off-by: Zhifeng Tang <zhifeng.tang@unisoc.com>
---
drivers/clk/sprd/ums512-clk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sprd/ums512-clk.c b/drivers/clk/sprd/ums512-clk.c
index fc25bdd85e4e..f43bb10bd5ae 100644
--- a/drivers/clk/sprd/ums512-clk.c
+++ b/drivers/clk/sprd/ums512-clk.c
@@ -800,7 +800,7 @@ static SPRD_MUX_CLK_DATA(uart1_clk, "uart1-clk", uart_parents,
0x250, 0, 3, UMS512_MUX_FLAG);
static const struct clk_parent_data thm_parents[] = {
- { .fw_name = "ext-32m" },
+ { .fw_name = "ext-32k" },
{ .hw = &clk_250k.hw },
};
static SPRD_MUX_CLK_DATA(thm0_clk, "thm0-clk", thm_parents,
--
2.17.1
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-09-11 21:58 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-08-24 9:26 [PATCH V2] clk: sprd: Fix thm_parents incorrect configuration Zhifeng Tang
2023-09-11 20:31 ` Stephen Boyd
-- strict thread matches above, loose matches on Subject: below --
2023-08-24 7:29 Zhifeng Tang
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®