* [PATCH v7 1/2] dt-bindings: PCI: dw: rockchip: Add rk3576 support
@ 2025-02-25 10:26 Kever Yang
2025-02-25 10:26 ` [PATCH v7 2/2] arm64: dts: rockchip: Add rk3576 pcie nodes Kever Yang
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Kever Yang @ 2025-02-25 10:26 UTC (permalink / raw)
To: heiko
Cc: linux-rockchip, Kever Yang, Sebastian Reichel, Simon Xue,
Conor Dooley, Rob Herring, Bjorn Helgaas, linux-pci,
Krzysztof Wilczyński, linux-kernel, Krzysztof Kozlowski,
devicetree, Lorenzo Pieralisi, Shawn Lin, Manivannan Sadhasivam,
linux-arm-kernel
rk3576 is using DWC PCIe controller, with msi interrupt directly to GIC
instead of using GIC ITS, so
- no ITS support is required and the 'msi-map' is not required,
- a new 'msi' interrupt is needed.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
Changes in v7:
- Move the rk3576 device specific schema out of common.yaml
Changes in v6:
- Fix make dt_binding_check and make CHECK_DTBS=y
Changes in v5:
- Add constraints per device for interrupt-names due to the interrupt is
different from rk3588.
Changes in v4:
- Fix wrong indentation in dt_binding_check report by Rob
Changes in v3:
- Fix dtb check broken on rk3588
- Update commit message
Changes in v2:
- remove required 'msi-map'
- add interrupt name 'msi'
.../bindings/pci/rockchip-dw-pcie-common.yaml | 10 +++-
.../bindings/pci/rockchip-dw-pcie.yaml | 55 +++++++++++++++++--
2 files changed, 57 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
index cc9adfc7611c..2150bd8b5fc2 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
@@ -65,7 +65,11 @@ properties:
tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
nf_err_rx, f_err_rx, radm_qoverflow
- description:
- eDMA write channel 0 interrupt
+ If the matching interrupt name is "msi", then this is the combinded
+ MSI line interrupt, which is to support MSI interrupts output to GIC
+ controller via GIC SPI interrupt instead of GIC its interrupt.
+ If the matching interrupt name is "dma0", then this is the eDMA write
+ channel 0 interrupt.
- description:
eDMA write channel 1 interrupt
- description:
@@ -81,7 +85,9 @@ properties:
- const: msg
- const: legacy
- const: err
- - const: dma0
+ - enum:
+ - msi
+ - dma0
- const: dma1
- const: dma2
- const: dma3
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
index 550d8a684af3..4764a0173ae4 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
@@ -16,16 +16,13 @@ description: |+
PCIe IP and thus inherits all the common properties defined in
snps,dw-pcie.yaml.
-allOf:
- - $ref: /schemas/pci/snps,dw-pcie.yaml#
- - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
-
properties:
compatible:
oneOf:
- const: rockchip,rk3568-pcie
- items:
- enum:
+ - rockchip,rk3576-pcie
- rockchip,rk3588-pcie
- const: rockchip,rk3568-pcie
@@ -71,8 +68,54 @@ properties:
vpcie3v3-supply: true
-required:
- - msi-map
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
+ - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3576-pcie
+ then:
+ required:
+ - msi-map
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3576-pcie
+ then:
+ properties:
+ interrupts:
+ minItems: 6
+ maxItems: 6
+ interrupt-names:
+ items:
+ - const: sys
+ - const: pmc
+ - const: msg
+ - const: legacy
+ - const: err
+ - const: msi
+ else:
+ properties:
+ interrupts:
+ minItems: 5
+ interrupt-names:
+ minItems: 5
+ items:
+ - const: sys
+ - const: pmc
+ - const: msg
+ - const: legacy
+ - const: err
+ - const: dma0
+ - const: dma1
+ - const: dma2
+ - const: dma3
+
unevaluatedProperties: false
--
2.25.1
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v7 2/2] arm64: dts: rockchip: Add rk3576 pcie nodes 2025-02-25 10:26 [PATCH v7 1/2] dt-bindings: PCI: dw: rockchip: Add rk3576 support Kever Yang @ 2025-02-25 10:26 ` Kever Yang 2025-04-08 3:01 ` Shawn Lin 2025-02-25 17:20 ` [PATCH v7 1/2] dt-bindings: PCI: dw: rockchip: Add rk3576 support Rob Herring (Arm) 2025-02-25 21:51 ` Sebastian Reichel 2 siblings, 1 reply; 5+ messages in thread From: Kever Yang @ 2025-02-25 10:26 UTC (permalink / raw) To: heiko Cc: linux-rockchip, Kever Yang, devicetree, Conor Dooley, Finley Xiao, Frank Wang, Rob Herring, Liang Chen, Detlev Casanova, linux-kernel, Krzysztof Kozlowski, Yifeng Zhao, linux-arm-kernel rk3576 has two pcie controllers, both are pcie2x1 work with naneng-combphy. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> --- Changes in v7: - re-order the properties. Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: - Update the subject Changes in v2: - Update clock and reset names and sequence to pass DTB check arch/arm64/boot/dts/rockchip/rk3576.dtsi | 108 +++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 4dde954043ef..79e24b2c3c60 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1127,6 +1127,114 @@ qos_npu_m1ro: qos@27f22100 { reg = <0x0 0x27f22100 0x0 0x20>; }; + pcie0: pcie@2a200000 { + compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; + reg = <0x0 0x22000000 0x0 0x00400000>, + <0x0 0x2a200000 0x0 0x00010000>, + <0x0 0x20000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, + <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, + <&cru CLK_PCIE0_AUX>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <2>; + num-ib-windows = <8>; + num-viewport = <8>; + num-ob-windows = <2>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3576_PD_PHP>; + ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000 + 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000 + 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pcie1: pcie@2a210000 { + compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; + reg = <0x0 0x22400000 0x0 0x00400000>, + <0x0 0x2a210000 0x0 0x00010000>, + <0x0 0x21000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, + <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, + <&cru CLK_PCIE1_AUX>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <2>; + num-ib-windows = <8>; + num-viewport = <8>; + num-ob-windows = <2>; + num-lanes = <1>; + phys = <&combphy1_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3576_PD_SUBPHP>; + ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000 + 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000 + 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>; + }; + }; + gmac0: ethernet@2a220000 { compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; reg = <0x0 0x2a220000 0x0 0x10000>; -- 2.25.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v7 2/2] arm64: dts: rockchip: Add rk3576 pcie nodes 2025-02-25 10:26 ` [PATCH v7 2/2] arm64: dts: rockchip: Add rk3576 pcie nodes Kever Yang @ 2025-04-08 3:01 ` Shawn Lin 0 siblings, 0 replies; 5+ messages in thread From: Shawn Lin @ 2025-04-08 3:01 UTC (permalink / raw) To: Kever Yang, heiko Cc: shawn.lin, linux-rockchip, devicetree, Conor Dooley, Finley Xiao, Frank Wang, Rob Herring, Liang Chen, Detlev Casanova, linux-kernel, Krzysztof Kozlowski, Yifeng Zhao, linux-arm-kernel 在 2025/02/25 星期二 18:26, Kever Yang 写道: > rk3576 has two pcie controllers, both are pcie2x1 work with > naneng-combphy. > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > --- > One thing need to be mentioned, defconfig set: CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m CONFIG_PHY_ROCKCHIP_PCIE=m So the phy is missing leads deferred probe pending. With setting CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y, pcie works fine, so Tested-by: Shawn Lin <Shawn.lin@rock-chips.com> > Changes in v7: > - re-order the properties. > > Changes in v6: None > Changes in v5: None > Changes in v4: None > Changes in v3: > - Update the subject > > Changes in v2: > - Update clock and reset names and sequence to pass DTB check > > arch/arm64/boot/dts/rockchip/rk3576.dtsi | 108 +++++++++++++++++++++++ > 1 file changed, 108 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi > index 4dde954043ef..79e24b2c3c60 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi > @@ -1127,6 +1127,114 @@ qos_npu_m1ro: qos@27f22100 { > reg = <0x0 0x27f22100 0x0 0x20>; > }; > > + pcie0: pcie@2a200000 { > + compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; > + reg = <0x0 0x22000000 0x0 0x00400000>, > + <0x0 0x2a200000 0x0 0x00010000>, > + <0x0 0x20000000 0x0 0x00100000>; > + reg-names = "dbi", "apb", "config"; > + bus-range = <0x0 0xf>; > + clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, > + <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, > + <&cru CLK_PCIE0_AUX>; > + clock-names = "aclk_mst", "aclk_slv", > + "aclk_dbi", "pclk", > + "aux"; > + device_type = "pci"; > + interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie0_intc 0>, > + <0 0 0 2 &pcie0_intc 1>, > + <0 0 0 3 &pcie0_intc 2>, > + <0 0 0 4 &pcie0_intc 3>; > + linux,pci-domain = <0>; > + max-link-speed = <2>; > + num-ib-windows = <8>; > + num-viewport = <8>; > + num-ob-windows = <2>; > + num-lanes = <1>; > + phys = <&combphy0_ps PHY_TYPE_PCIE>; > + phy-names = "pcie-phy"; > + power-domains = <&power RK3576_PD_PHP>; > + ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000 > + 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000 > + 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; > + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; > + reset-names = "pwr", "pipe"; > + #address-cells = <3>; > + #size-cells = <2>; > + status = "disabled"; > + > + pcie0_intc: legacy-interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; > + }; > + }; > + > + pcie1: pcie@2a210000 { > + compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; > + reg = <0x0 0x22400000 0x0 0x00400000>, > + <0x0 0x2a210000 0x0 0x00010000>, > + <0x0 0x21000000 0x0 0x00100000>; > + reg-names = "dbi", "apb", "config"; > + bus-range = <0x20 0x2f>; > + clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, > + <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, > + <&cru CLK_PCIE1_AUX>; > + clock-names = "aclk_mst", "aclk_slv", > + "aclk_dbi", "pclk", > + "aux"; > + device_type = "pci"; > + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, > + <0 0 0 2 &pcie1_intc 1>, > + <0 0 0 3 &pcie1_intc 2>, > + <0 0 0 4 &pcie1_intc 3>; > + linux,pci-domain = <0>; > + max-link-speed = <2>; > + num-ib-windows = <8>; > + num-viewport = <8>; > + num-ob-windows = <2>; > + num-lanes = <1>; > + phys = <&combphy1_psu PHY_TYPE_PCIE>; > + phy-names = "pcie-phy"; > + power-domains = <&power RK3576_PD_SUBPHP>; > + ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000 > + 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000 > + 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; > + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; > + reset-names = "pwr", "pipe"; > + #address-cells = <3>; > + #size-cells = <2>; > + status = "disabled"; > + > + pcie1_intc: legacy-interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>; > + }; > + }; > + > gmac0: ethernet@2a220000 { > compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; > reg = <0x0 0x2a220000 0x0 0x10000>; ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v7 1/2] dt-bindings: PCI: dw: rockchip: Add rk3576 support 2025-02-25 10:26 [PATCH v7 1/2] dt-bindings: PCI: dw: rockchip: Add rk3576 support Kever Yang 2025-02-25 10:26 ` [PATCH v7 2/2] arm64: dts: rockchip: Add rk3576 pcie nodes Kever Yang @ 2025-02-25 17:20 ` Rob Herring (Arm) 2025-02-25 21:51 ` Sebastian Reichel 2 siblings, 0 replies; 5+ messages in thread From: Rob Herring (Arm) @ 2025-02-25 17:20 UTC (permalink / raw) To: Kever Yang Cc: linux-kernel, Shawn Lin, Conor Dooley, Manivannan Sadhasivam, linux-arm-kernel, Bjorn Helgaas, devicetree, linux-pci, heiko, Krzysztof Kozlowski, Simon Xue, Sebastian Reichel, linux-rockchip, Lorenzo Pieralisi, Krzysztof Wilczyński On Tue, 25 Feb 2025 18:26:10 +0800, Kever Yang wrote: > rk3576 is using DWC PCIe controller, with msi interrupt directly to GIC > instead of using GIC ITS, so > - no ITS support is required and the 'msi-map' is not required, > - a new 'msi' interrupt is needed. > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > > Changes in v7: > - Move the rk3576 device specific schema out of common.yaml > > Changes in v6: > - Fix make dt_binding_check and make CHECK_DTBS=y > > Changes in v5: > - Add constraints per device for interrupt-names due to the interrupt is > different from rk3588. > > Changes in v4: > - Fix wrong indentation in dt_binding_check report by Rob > > Changes in v3: > - Fix dtb check broken on rk3588 > - Update commit message > > Changes in v2: > - remove required 'msi-map' > - add interrupt name 'msi' > > .../bindings/pci/rockchip-dw-pcie-common.yaml | 10 +++- > .../bindings/pci/rockchip-dw-pcie.yaml | 55 +++++++++++++++++-- > 2 files changed, 57 insertions(+), 8 deletions(-) > Reviewed-by: Rob Herring (Arm) <robh@kernel.org> ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v7 1/2] dt-bindings: PCI: dw: rockchip: Add rk3576 support 2025-02-25 10:26 [PATCH v7 1/2] dt-bindings: PCI: dw: rockchip: Add rk3576 support Kever Yang 2025-02-25 10:26 ` [PATCH v7 2/2] arm64: dts: rockchip: Add rk3576 pcie nodes Kever Yang 2025-02-25 17:20 ` [PATCH v7 1/2] dt-bindings: PCI: dw: rockchip: Add rk3576 support Rob Herring (Arm) @ 2025-02-25 21:51 ` Sebastian Reichel 2 siblings, 0 replies; 5+ messages in thread From: Sebastian Reichel @ 2025-02-25 21:51 UTC (permalink / raw) To: Kever Yang Cc: heiko, linux-rockchip, Simon Xue, Conor Dooley, Rob Herring, Bjorn Helgaas, linux-pci, Krzysztof Wilczyński, linux-kernel, Krzysztof Kozlowski, devicetree, Lorenzo Pieralisi, Shawn Lin, Manivannan Sadhasivam, linux-arm-kernel Hello Kever, On Tue, Feb 25, 2025 at 06:26:10PM +0800, Kever Yang wrote: > rk3576 is using DWC PCIe controller, with msi interrupt directly to GIC > instead of using GIC ITS, so > - no ITS support is required and the 'msi-map' is not required, > - a new 'msi' interrupt is needed. > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- You should either drop my Signed-off-by or add Co-developed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Both options are fine with me, but the current one does not make much sense :) Greetings, -- Sebastian > > Changes in v7: > - Move the rk3576 device specific schema out of common.yaml > > Changes in v6: > - Fix make dt_binding_check and make CHECK_DTBS=y > > Changes in v5: > - Add constraints per device for interrupt-names due to the interrupt is > different from rk3588. > > Changes in v4: > - Fix wrong indentation in dt_binding_check report by Rob > > Changes in v3: > - Fix dtb check broken on rk3588 > - Update commit message > > Changes in v2: > - remove required 'msi-map' > - add interrupt name 'msi' > > .../bindings/pci/rockchip-dw-pcie-common.yaml | 10 +++- > .../bindings/pci/rockchip-dw-pcie.yaml | 55 +++++++++++++++++-- > 2 files changed, 57 insertions(+), 8 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml > index cc9adfc7611c..2150bd8b5fc2 100644 > --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml > +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml > @@ -65,7 +65,11 @@ properties: > tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, > nf_err_rx, f_err_rx, radm_qoverflow > - description: > - eDMA write channel 0 interrupt > + If the matching interrupt name is "msi", then this is the combinded > + MSI line interrupt, which is to support MSI interrupts output to GIC > + controller via GIC SPI interrupt instead of GIC its interrupt. > + If the matching interrupt name is "dma0", then this is the eDMA write > + channel 0 interrupt. > - description: > eDMA write channel 1 interrupt > - description: > @@ -81,7 +85,9 @@ properties: > - const: msg > - const: legacy > - const: err > - - const: dma0 > + - enum: > + - msi > + - dma0 > - const: dma1 > - const: dma2 > - const: dma3 > diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > index 550d8a684af3..4764a0173ae4 100644 > --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > @@ -16,16 +16,13 @@ description: |+ > PCIe IP and thus inherits all the common properties defined in > snps,dw-pcie.yaml. > > -allOf: > - - $ref: /schemas/pci/snps,dw-pcie.yaml# > - - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# > - > properties: > compatible: > oneOf: > - const: rockchip,rk3568-pcie > - items: > - enum: > + - rockchip,rk3576-pcie > - rockchip,rk3588-pcie > - const: rockchip,rk3568-pcie > > @@ -71,8 +68,54 @@ properties: > > vpcie3v3-supply: true > > -required: > - - msi-map > +allOf: > + - $ref: /schemas/pci/snps,dw-pcie.yaml# > + - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# > + - if: > + not: > + properties: > + compatible: > + contains: > + const: rockchip,rk3576-pcie > + then: > + required: > + - msi-map > + > + - if: > + properties: > + compatible: > + contains: > + const: rockchip,rk3576-pcie > + then: > + properties: > + interrupts: > + minItems: 6 > + maxItems: 6 > + interrupt-names: > + items: > + - const: sys > + - const: pmc > + - const: msg > + - const: legacy > + - const: err > + - const: msi > + else: > + properties: > + interrupts: > + minItems: 5 > + interrupt-names: > + minItems: 5 > + items: > + - const: sys > + - const: pmc > + - const: msg > + - const: legacy > + - const: err > + - const: dma0 > + - const: dma1 > + - const: dma2 > + - const: dma3 > + > > unevaluatedProperties: false > > -- > 2.25.1 > > ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-04-08 3:16 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2025-02-25 10:26 [PATCH v7 1/2] dt-bindings: PCI: dw: rockchip: Add rk3576 support Kever Yang 2025-02-25 10:26 ` [PATCH v7 2/2] arm64: dts: rockchip: Add rk3576 pcie nodes Kever Yang 2025-04-08 3:01 ` Shawn Lin 2025-02-25 17:20 ` [PATCH v7 1/2] dt-bindings: PCI: dw: rockchip: Add rk3576 support Rob Herring (Arm) 2025-02-25 21:51 ` Sebastian Reichel
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