* [PATCH v7 01/43] dt-bindings: display: mediatek: dpi: Add MT8195 and MT8188 compat
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
@ 2025-02-17 15:47 ` AngeloGioacchino Del Regno
2025-03-02 10:34 ` Chun-Kuang Hu
2025-02-17 15:47 ` [PATCH v7 02/43] drm/mediatek: mtk_dpi: Add support for Pattern Generator in debugfs AngeloGioacchino Del Regno
` (42 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:47 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin, Krzysztof Kozlowski
Add compatibles for the Digital Parallel Interface (DPI) block
found in the MT8195 and MT8188 SoCs: inside of the chip, this one
is directly connected to the HDMI block.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index 0f1e556dc8ef..5670715efa5c 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -27,6 +27,7 @@ properties:
- mediatek,mt8188-dp-intf
- mediatek,mt8192-dpi
- mediatek,mt8195-dp-intf
+ - mediatek,mt8195-dpi
- items:
- enum:
- mediatek,mt6795-dpi
@@ -35,6 +36,10 @@ properties:
- enum:
- mediatek,mt8365-dpi
- const: mediatek,mt8192-dpi
+ - items:
+ - enum:
+ - mediatek,mt8188-dpi
+ - const: mediatek,mt8195-dpi
reg:
maxItems: 1
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 01/43] dt-bindings: display: mediatek: dpi: Add MT8195 and MT8188 compat
2025-02-17 15:47 ` [PATCH v7 01/43] dt-bindings: display: mediatek: dpi: Add MT8195 and MT8188 compat AngeloGioacchino Del Regno
@ 2025-03-02 10:34 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-03-02 10:34 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin, Krzysztof Kozlowski
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:49寫道：
>
> Add compatibles for the Digital Parallel Interface (DPI) block
> found in the MT8195 and MT8188 SoCs: inside of the chip, this one
> is directly connected to the HDMI block.
Applied to mediatek-drm-next [1], thanks.
[1] https://web.git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> index 0f1e556dc8ef..5670715efa5c 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> @@ -27,6 +27,7 @@ properties:
> - mediatek,mt8188-dp-intf
> - mediatek,mt8192-dpi
> - mediatek,mt8195-dp-intf
> + - mediatek,mt8195-dpi
> - items:
> - enum:
> - mediatek,mt6795-dpi
> @@ -35,6 +36,10 @@ properties:
> - enum:
> - mediatek,mt8365-dpi
> - const: mediatek,mt8192-dpi
> + - items:
> + - enum:
> + - mediatek,mt8188-dpi
> + - const: mediatek,mt8195-dpi
>
> reg:
> maxItems: 1
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 02/43] drm/mediatek: mtk_dpi: Add support for Pattern Generator in debugfs
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
2025-02-17 15:47 ` [PATCH v7 01/43] dt-bindings: display: mediatek: dpi: Add MT8195 and MT8188 compat AngeloGioacchino Del Regno
@ 2025-02-17 15:47 ` AngeloGioacchino Del Regno
2025-03-02 10:38 ` Chun-Kuang Hu
2025-02-17 15:47 ` [PATCH v7 03/43] drm/mediatek: mtk_dpi: Use an array for pixclk factor calculation AngeloGioacchino Del Regno
` (41 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:47 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
This IP includes a Pattern Generator which is useful for debugging
and testing purposes: add the relevant register and bits to the
mtk_dpi_regs.h header, and implement support for it in mtk_dpi.
Adding this required to introduce a .debugfs_init() callback for
the DPI bridge, which creates a "dpi_test_pattern" file in the
directory of the appropriate connector.
The pattern generator can generate various internal patterns and
this submission includes support for:
- 256 or 1024 shades of gray in a Vertical or Horizontal Pattern
- Vertical Color Bars
- Frame border
- Dot Moire
This generator also supports filling the entire screen with one
custom color, but support for that is not included in this commit.
Enabling and disabling this generator can be done by sending a
string to the dpi_test_pattern debugfs file; the pattern is
expected to be formatted as follows:
<enable (1) or disable (0)> <pattern number>
where the pattern number can be a number from 0 to 7, excluding 5.
Of course 5 is excluded because that activates custom color fill
which, again, is not supported in this commit.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 108 ++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 4 +
2 files changed, 112 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 1864eb02dbf5..fc937490feda 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -4,8 +4,10 @@
* Author: Jie Qiu <jie.qiu@mediatek.com>
*/
+#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/component.h>
+#include <linux/debugfs.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/media-bus-format.h>
@@ -166,6 +168,18 @@ static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
writel(tmp, dpi->regs + offset);
}
+static void mtk_dpi_test_pattern_en(struct mtk_dpi *dpi, u8 type, bool enable)
+{
+ u32 val;
+
+ if (enable)
+ val = FIELD_PREP(DPI_PAT_SEL, type) | DPI_PAT_EN;
+ else
+ val = 0;
+
+ mtk_dpi_mask(dpi, DPI_PATTERN0, val, DPI_PAT_SEL | DPI_PAT_EN);
+}
+
static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset)
{
mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST);
@@ -767,6 +781,99 @@ mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge,
return MODE_OK;
}
+static int mtk_dpi_debug_tp_show(struct seq_file *m, void *arg)
+{
+ struct mtk_dpi *dpi = m->private;
+ bool en;
+ u32 val;
+
+ if (!dpi)
+ return -EINVAL;
+
+ val = readl(dpi->regs + DPI_PATTERN0);
+ en = val & DPI_PAT_EN;
+ val = FIELD_GET(DPI_PAT_SEL, val);
+
+ seq_printf(m, "DPI Test Pattern: %s\n", en ? "Enabled" : "Disabled");
+
+ if (en) {
+ seq_printf(m, "Internal pattern %d: ", val);
+ switch (val) {
+ case 0:
+ seq_puts(m, "256 Vertical Gray\n");
+ break;
+ case 1:
+ seq_puts(m, "1024 Vertical Gray\n");
+ break;
+ case 2:
+ seq_puts(m, "256 Horizontal Gray\n");
+ break;
+ case 3:
+ seq_puts(m, "1024 Horizontal Gray\n");
+ break;
+ case 4:
+ seq_puts(m, "Vertical Color bars\n");
+ break;
+ case 6:
+ seq_puts(m, "Frame border\n");
+ break;
+ case 7:
+ seq_puts(m, "Dot moire\n");
+ break;
+ default:
+ seq_puts(m, "Invalid selection\n");
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static ssize_t mtk_dpi_debug_tp_write(struct file *file, const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ struct seq_file *m = file->private_data;
+ u32 en, type;
+ char buf[6];
+
+ if (!m || !m->private || *offp || len > sizeof(buf) - 1)
+ return -EINVAL;
+
+ memset(buf, 0, sizeof(buf));
+ if (copy_from_user(buf, ubuf, len))
+ return -EFAULT;
+
+ if (sscanf(buf, "%u %u", &en, &type) != 2)
+ return -EINVAL;
+
+ if (en < 0 || en > 1 || type < 0 || type > 7)
+ return -EINVAL;
+
+ mtk_dpi_test_pattern_en((struct mtk_dpi *)m->private, type, en);
+ return len;
+}
+
+static int mtk_dpi_debug_tp_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, mtk_dpi_debug_tp_show, inode->i_private);
+}
+
+static const struct file_operations mtk_dpi_debug_tp_fops = {
+ .owner = THIS_MODULE,
+ .open = mtk_dpi_debug_tp_open,
+ .read = seq_read,
+ .write = mtk_dpi_debug_tp_write,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static void mtk_dpi_debugfs_init(struct drm_bridge *bridge, struct dentry *root)
+{
+ struct mtk_dpi *dpi = bridge_to_dpi(bridge);
+
+ debugfs_create_file("dpi_test_pattern", 0640, root, dpi, &mtk_dpi_debug_tp_fops);
+}
+
static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
.attach = mtk_dpi_bridge_attach,
.mode_set = mtk_dpi_bridge_mode_set,
@@ -779,6 +886,7 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
.atomic_reset = drm_atomic_helper_bridge_reset,
+ .debugfs_init = mtk_dpi_debugfs_init,
};
void mtk_dpi_start(struct device *dev)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index 62bd4931b344..a0b1d18bbbf7 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -235,4 +235,8 @@
#define MATRIX_SEL_RGB_TO_JPEG 0
#define MATRIX_SEL_RGB_TO_BT601 2
+#define DPI_PATTERN0 0xf00
+#define DPI_PAT_EN BIT(0)
+#define DPI_PAT_SEL GENMASK(6, 4)
+
#endif /* __MTK_DPI_REGS_H */
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 02/43] drm/mediatek: mtk_dpi: Add support for Pattern Generator in debugfs
2025-02-17 15:47 ` [PATCH v7 02/43] drm/mediatek: mtk_dpi: Add support for Pattern Generator in debugfs AngeloGioacchino Del Regno
@ 2025-03-02 10:38 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-03-02 10:38 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:49寫道：
>
> This IP includes a Pattern Generator which is useful for debugging
> and testing purposes: add the relevant register and bits to the
> mtk_dpi_regs.h header, and implement support for it in mtk_dpi.
>
> Adding this required to introduce a .debugfs_init() callback for
> the DPI bridge, which creates a "dpi_test_pattern" file in the
> directory of the appropriate connector.
>
> The pattern generator can generate various internal patterns and
> this submission includes support for:
> - 256 or 1024 shades of gray in a Vertical or Horizontal Pattern
> - Vertical Color Bars
> - Frame border
> - Dot Moire
>
> This generator also supports filling the entire screen with one
> custom color, but support for that is not included in this commit.
>
> Enabling and disabling this generator can be done by sending a
> string to the dpi_test_pattern debugfs file; the pattern is
> expected to be formatted as follows:
>
> <enable (1) or disable (0)> <pattern number>
>
> where the pattern number can be a number from 0 to 7, excluding 5.
>
> Of course 5 is excluded because that activates custom color fill
> which, again, is not supported in this commit.
Applied to mediatek-drm-next [1], thanks.
[1] https://web.git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 108 ++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 4 +
> 2 files changed, 112 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 1864eb02dbf5..fc937490feda 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -4,8 +4,10 @@
> * Author: Jie Qiu <jie.qiu@mediatek.com>
> */
>
> +#include <linux/bitfield.h>
> #include <linux/clk.h>
> #include <linux/component.h>
> +#include <linux/debugfs.h>
> #include <linux/interrupt.h>
> #include <linux/kernel.h>
> #include <linux/media-bus-format.h>
> @@ -166,6 +168,18 @@ static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
> writel(tmp, dpi->regs + offset);
> }
>
> +static void mtk_dpi_test_pattern_en(struct mtk_dpi *dpi, u8 type, bool enable)
> +{
> + u32 val;
> +
> + if (enable)
> + val = FIELD_PREP(DPI_PAT_SEL, type) | DPI_PAT_EN;
> + else
> + val = 0;
> +
> + mtk_dpi_mask(dpi, DPI_PATTERN0, val, DPI_PAT_SEL | DPI_PAT_EN);
> +}
> +
> static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset)
> {
> mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST);
> @@ -767,6 +781,99 @@ mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge,
> return MODE_OK;
> }
>
> +static int mtk_dpi_debug_tp_show(struct seq_file *m, void *arg)
> +{
> + struct mtk_dpi *dpi = m->private;
> + bool en;
> + u32 val;
> +
> + if (!dpi)
> + return -EINVAL;
> +
> + val = readl(dpi->regs + DPI_PATTERN0);
> + en = val & DPI_PAT_EN;
> + val = FIELD_GET(DPI_PAT_SEL, val);
> +
> + seq_printf(m, "DPI Test Pattern: %s\n", en ? "Enabled" : "Disabled");
> +
> + if (en) {
> + seq_printf(m, "Internal pattern %d: ", val);
> + switch (val) {
> + case 0:
> + seq_puts(m, "256 Vertical Gray\n");
> + break;
> + case 1:
> + seq_puts(m, "1024 Vertical Gray\n");
> + break;
> + case 2:
> + seq_puts(m, "256 Horizontal Gray\n");
> + break;
> + case 3:
> + seq_puts(m, "1024 Horizontal Gray\n");
> + break;
> + case 4:
> + seq_puts(m, "Vertical Color bars\n");
> + break;
> + case 6:
> + seq_puts(m, "Frame border\n");
> + break;
> + case 7:
> + seq_puts(m, "Dot moire\n");
> + break;
> + default:
> + seq_puts(m, "Invalid selection\n");
> + break;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static ssize_t mtk_dpi_debug_tp_write(struct file *file, const char __user *ubuf,
> + size_t len, loff_t *offp)
> +{
> + struct seq_file *m = file->private_data;
> + u32 en, type;
> + char buf[6];
> +
> + if (!m || !m->private || *offp || len > sizeof(buf) - 1)
> + return -EINVAL;
> +
> + memset(buf, 0, sizeof(buf));
> + if (copy_from_user(buf, ubuf, len))
> + return -EFAULT;
> +
> + if (sscanf(buf, "%u %u", &en, &type) != 2)
> + return -EINVAL;
> +
> + if (en < 0 || en > 1 || type < 0 || type > 7)
> + return -EINVAL;
> +
> + mtk_dpi_test_pattern_en((struct mtk_dpi *)m->private, type, en);
> + return len;
> +}
> +
> +static int mtk_dpi_debug_tp_open(struct inode *inode, struct file *file)
> +{
> + return single_open(file, mtk_dpi_debug_tp_show, inode->i_private);
> +}
> +
> +static const struct file_operations mtk_dpi_debug_tp_fops = {
> + .owner = THIS_MODULE,
> + .open = mtk_dpi_debug_tp_open,
> + .read = seq_read,
> + .write = mtk_dpi_debug_tp_write,
> + .llseek = seq_lseek,
> + .release = single_release,
> +};
> +
> +static void mtk_dpi_debugfs_init(struct drm_bridge *bridge, struct dentry *root)
> +{
> + struct mtk_dpi *dpi = bridge_to_dpi(bridge);
> +
> + debugfs_create_file("dpi_test_pattern", 0640, root, dpi, &mtk_dpi_debug_tp_fops);
> +}
> +
> static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
> .attach = mtk_dpi_bridge_attach,
> .mode_set = mtk_dpi_bridge_mode_set,
> @@ -779,6 +886,7 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
> .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> .atomic_reset = drm_atomic_helper_bridge_reset,
> + .debugfs_init = mtk_dpi_debugfs_init,
> };
>
> void mtk_dpi_start(struct device *dev)
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> index 62bd4931b344..a0b1d18bbbf7 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> @@ -235,4 +235,8 @@
> #define MATRIX_SEL_RGB_TO_JPEG 0
> #define MATRIX_SEL_RGB_TO_BT601 2
>
> +#define DPI_PATTERN0 0xf00
> +#define DPI_PAT_EN BIT(0)
> +#define DPI_PAT_SEL GENMASK(6, 4)
> +
> #endif /* __MTK_DPI_REGS_H */
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 03/43] drm/mediatek: mtk_dpi: Use an array for pixclk factor calculation
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
2025-02-17 15:47 ` [PATCH v7 01/43] dt-bindings: display: mediatek: dpi: Add MT8195 and MT8188 compat AngeloGioacchino Del Regno
2025-02-17 15:47 ` [PATCH v7 02/43] drm/mediatek: mtk_dpi: Add support for Pattern Generator in debugfs AngeloGioacchino Del Regno
@ 2025-02-17 15:47 ` AngeloGioacchino Del Regno
2025-03-02 10:53 ` Chun-Kuang Hu
2025-03-02 11:03 ` Chun-Kuang Hu
2025-02-17 15:47 ` [PATCH v7 04/43] drm/mediatek: mtk_dpi: Move pixel clock setting flow to function AngeloGioacchino Del Regno
` (40 subsequent siblings)
43 siblings, 2 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:47 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
Setting the TVD PLL clock requires to multiply the target pixel
clock by a specific constant factor to achieve the target PLL
frequency, and this is done to reduce jitter to acceptable levels.
On all MediaTek SoCs, the factor is not retrieved by any real kind
of calculation but rather by checking if the target pixel clock
is less than a specified frequency, hence assigning a function
pointer for just a bunch of if branches does enlarge the code
size for little reason.
Remove all SoC-specific functions, add a structure `mtk_dpi_factor`
that holds a clock frequency and corresponding PLL factor, and
declare the constraints for each SoC in form of an array of said
structure.
Instead of function pointers, this structure (and its size) is then
assigned to each SoC's platform data.
The "calculation" is then performed with a new static function
mtk_dpi_calculate_factor(dpi, mode_clk) that iterates through all
of the entries of the aforementioned array and returns the right
factor.
If no factor is found, the lowest possible factor is returned,
mimicking the same flow as all of the old per-SoC calculation
functions.
This commit brings no functional change.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 103 +++++++++++++++--------------
1 file changed, 52 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index fc937490feda..41fdc193891a 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -118,9 +118,15 @@ struct mtk_dpi_yc_limit {
u16 c_bottom;
};
+struct mtk_dpi_factor {
+ u32 clock;
+ u8 factor;
+};
+
/**
* struct mtk_dpi_conf - Configuration of mediatek dpi.
- * @cal_factor: Callback function to calculate factor value.
+ * @dpi_factor: SoC-specific pixel clock PLL factor values.
+ * @num_dpi_factor: Number of pixel clock PLL factor values.
* @reg_h_fre_con: Register address of frequency control.
* @max_clock_khz: Max clock frequency supported for this SoCs in khz units.
* @edge_sel_en: Enable of edge selection.
@@ -141,7 +147,8 @@ struct mtk_dpi_yc_limit {
* @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
*/
struct mtk_dpi_conf {
- unsigned int (*cal_factor)(int clock);
+ const struct mtk_dpi_factor *dpi_factor;
+ const u8 num_dpi_factor;
u32 reg_h_fre_con;
u32 max_clock_khz;
bool edge_sel_en;
@@ -516,6 +523,20 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
return ret;
}
+static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode_clk)
+{
+ const struct mtk_dpi_factor *dpi_factor = dpi->conf->dpi_factor;
+ int i;
+
+ for (i = 0; i < dpi->conf->num_dpi_factor; i++) {
+ if (mode_clk <= dpi_factor[i].clock)
+ return dpi_factor[i].factor;
+ }
+
+ /* If no match try the lowest possible factor */
+ return dpi_factor[dpi->conf->num_dpi_factor - 1].factor;
+}
+
static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
struct drm_display_mode *mode)
{
@@ -530,7 +551,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
unsigned int factor;
/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
- factor = dpi->conf->cal_factor(mode->clock);
+ factor = mtk_dpi_calculate_factor(dpi, mode_clk);
drm_display_mode_to_videomode(mode, &vm);
pll_rate = vm.pixelclock * factor;
@@ -965,48 +986,6 @@ static const struct component_ops mtk_dpi_component_ops = {
.unbind = mtk_dpi_unbind,
};
-static unsigned int mt8173_calculate_factor(int clock)
-{
- if (clock <= 27000)
- return 3 << 4;
- else if (clock <= 84000)
- return 3 << 3;
- else if (clock <= 167000)
- return 3 << 2;
- else
- return 3 << 1;
-}
-
-static unsigned int mt2701_calculate_factor(int clock)
-{
- if (clock <= 64000)
- return 4;
- else if (clock <= 128000)
- return 2;
- else
- return 1;
-}
-
-static unsigned int mt8183_calculate_factor(int clock)
-{
- if (clock <= 27000)
- return 8;
- else if (clock <= 167000)
- return 4;
- else
- return 2;
-}
-
-static unsigned int mt8195_dpintf_calculate_factor(int clock)
-{
- if (clock < 70000)
- return 4;
- else if (clock < 200000)
- return 2;
- else
- return 1;
-}
-
static const u32 mt8173_output_fmts[] = {
MEDIA_BUS_FMT_RGB888_1X24,
};
@@ -1021,8 +1000,25 @@ static const u32 mt8195_output_fmts[] = {
MEDIA_BUS_FMT_YUYV8_1X16,
};
+static const struct mtk_dpi_factor dpi_factor_mt2701[] = {
+ { 64000, 4 }, { 128000, 2 }, { U32_MAX, 1 }
+};
+
+static const struct mtk_dpi_factor dpi_factor_mt8173[] = {
+ { 27000, 48 }, { 84000, 24 }, { 167000, 12 }, { U32_MAX, 6 }
+};
+
+static const struct mtk_dpi_factor dpi_factor_mt8183[] = {
+ { 27000, 8 }, { 167000, 4 }, { U32_MAX, 2 }
+};
+
+static const struct mtk_dpi_factor dpi_factor_mt8195_dp_intf[] = {
+ { 70000 - 1, 4 }, { 200000 - 1, 2 }, { U32_MAX, 1 }
+};
+
static const struct mtk_dpi_conf mt8173_conf = {
- .cal_factor = mt8173_calculate_factor,
+ .dpi_factor = dpi_factor_mt8173,
+ .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8173),
.reg_h_fre_con = 0xe0,
.max_clock_khz = 300000,
.output_fmts = mt8173_output_fmts,
@@ -1039,7 +1035,8 @@ static const struct mtk_dpi_conf mt8173_conf = {
};
static const struct mtk_dpi_conf mt2701_conf = {
- .cal_factor = mt2701_calculate_factor,
+ .dpi_factor = dpi_factor_mt2701,
+ .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt2701),
.reg_h_fre_con = 0xb0,
.edge_sel_en = true,
.max_clock_khz = 150000,
@@ -1057,7 +1054,8 @@ static const struct mtk_dpi_conf mt2701_conf = {
};
static const struct mtk_dpi_conf mt8183_conf = {
- .cal_factor = mt8183_calculate_factor,
+ .dpi_factor = dpi_factor_mt8183,
+ .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
.reg_h_fre_con = 0xe0,
.max_clock_khz = 100000,
.output_fmts = mt8183_output_fmts,
@@ -1074,7 +1072,8 @@ static const struct mtk_dpi_conf mt8183_conf = {
};
static const struct mtk_dpi_conf mt8186_conf = {
- .cal_factor = mt8183_calculate_factor,
+ .dpi_factor = dpi_factor_mt8183,
+ .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
.reg_h_fre_con = 0xe0,
.max_clock_khz = 150000,
.output_fmts = mt8183_output_fmts,
@@ -1092,7 +1091,8 @@ static const struct mtk_dpi_conf mt8186_conf = {
};
static const struct mtk_dpi_conf mt8192_conf = {
- .cal_factor = mt8183_calculate_factor,
+ .dpi_factor = dpi_factor_mt8183,
+ .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
.reg_h_fre_con = 0xe0,
.max_clock_khz = 150000,
.output_fmts = mt8183_output_fmts,
@@ -1109,7 +1109,8 @@ static const struct mtk_dpi_conf mt8192_conf = {
};
static const struct mtk_dpi_conf mt8195_dpintf_conf = {
- .cal_factor = mt8195_dpintf_calculate_factor,
+ .dpi_factor = dpi_factor_mt8195_dp_intf,
+ .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf),
.max_clock_khz = 600000,
.output_fmts = mt8195_output_fmts,
.num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 03/43] drm/mediatek: mtk_dpi: Use an array for pixclk factor calculation
2025-02-17 15:47 ` [PATCH v7 03/43] drm/mediatek: mtk_dpi: Use an array for pixclk factor calculation AngeloGioacchino Del Regno
@ 2025-03-02 10:53 ` Chun-Kuang Hu
2025-03-02 11:03 ` Chun-Kuang Hu
1 sibling, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-03-02 10:53 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:49寫道：
>
> Setting the TVD PLL clock requires to multiply the target pixel
> clock by a specific constant factor to achieve the target PLL
> frequency, and this is done to reduce jitter to acceptable levels.
>
> On all MediaTek SoCs, the factor is not retrieved by any real kind
> of calculation but rather by checking if the target pixel clock
> is less than a specified frequency, hence assigning a function
> pointer for just a bunch of if branches does enlarge the code
> size for little reason.
>
> Remove all SoC-specific functions, add a structure `mtk_dpi_factor`
> that holds a clock frequency and corresponding PLL factor, and
> declare the constraints for each SoC in form of an array of said
> structure.
> Instead of function pointers, this structure (and its size) is then
> assigned to each SoC's platform data.
>
> The "calculation" is then performed with a new static function
> mtk_dpi_calculate_factor(dpi, mode_clk) that iterates through all
> of the entries of the aforementioned array and returns the right
> factor.
>
> If no factor is found, the lowest possible factor is returned,
> mimicking the same flow as all of the old per-SoC calculation
> functions.
>
> This commit brings no functional change.
After fix build error, applied to mediatek-drm-next [1], thanks.
[1] https://web.git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 103 +++++++++++++++--------------
> 1 file changed, 52 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index fc937490feda..41fdc193891a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -118,9 +118,15 @@ struct mtk_dpi_yc_limit {
> u16 c_bottom;
> };
>
> +struct mtk_dpi_factor {
> + u32 clock;
> + u8 factor;
> +};
> +
> /**
> * struct mtk_dpi_conf - Configuration of mediatek dpi.
> - * @cal_factor: Callback function to calculate factor value.
> + * @dpi_factor: SoC-specific pixel clock PLL factor values.
> + * @num_dpi_factor: Number of pixel clock PLL factor values.
> * @reg_h_fre_con: Register address of frequency control.
> * @max_clock_khz: Max clock frequency supported for this SoCs in khz units.
> * @edge_sel_en: Enable of edge selection.
> @@ -141,7 +147,8 @@ struct mtk_dpi_yc_limit {
> * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
> */
> struct mtk_dpi_conf {
> - unsigned int (*cal_factor)(int clock);
> + const struct mtk_dpi_factor *dpi_factor;
> + const u8 num_dpi_factor;
> u32 reg_h_fre_con;
> u32 max_clock_khz;
> bool edge_sel_en;
> @@ -516,6 +523,20 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
> return ret;
> }
>
> +static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode_clk)
> +{
> + const struct mtk_dpi_factor *dpi_factor = dpi->conf->dpi_factor;
> + int i;
> +
> + for (i = 0; i < dpi->conf->num_dpi_factor; i++) {
> + if (mode_clk <= dpi_factor[i].clock)
> + return dpi_factor[i].factor;
> + }
> +
> + /* If no match try the lowest possible factor */
> + return dpi_factor[dpi->conf->num_dpi_factor - 1].factor;
> +}
> +
> static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> struct drm_display_mode *mode)
> {
> @@ -530,7 +551,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> unsigned int factor;
>
> /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
> - factor = dpi->conf->cal_factor(mode->clock);
> + factor = mtk_dpi_calculate_factor(dpi, mode_clk);
> drm_display_mode_to_videomode(mode, &vm);
> pll_rate = vm.pixelclock * factor;
>
> @@ -965,48 +986,6 @@ static const struct component_ops mtk_dpi_component_ops = {
> .unbind = mtk_dpi_unbind,
> };
>
> -static unsigned int mt8173_calculate_factor(int clock)
> -{
> - if (clock <= 27000)
> - return 3 << 4;
> - else if (clock <= 84000)
> - return 3 << 3;
> - else if (clock <= 167000)
> - return 3 << 2;
> - else
> - return 3 << 1;
> -}
> -
> -static unsigned int mt2701_calculate_factor(int clock)
> -{
> - if (clock <= 64000)
> - return 4;
> - else if (clock <= 128000)
> - return 2;
> - else
> - return 1;
> -}
> -
> -static unsigned int mt8183_calculate_factor(int clock)
> -{
> - if (clock <= 27000)
> - return 8;
> - else if (clock <= 167000)
> - return 4;
> - else
> - return 2;
> -}
> -
> -static unsigned int mt8195_dpintf_calculate_factor(int clock)
> -{
> - if (clock < 70000)
> - return 4;
> - else if (clock < 200000)
> - return 2;
> - else
> - return 1;
> -}
> -
> static const u32 mt8173_output_fmts[] = {
> MEDIA_BUS_FMT_RGB888_1X24,
> };
> @@ -1021,8 +1000,25 @@ static const u32 mt8195_output_fmts[] = {
> MEDIA_BUS_FMT_YUYV8_1X16,
> };
>
> +static const struct mtk_dpi_factor dpi_factor_mt2701[] = {
> + { 64000, 4 }, { 128000, 2 }, { U32_MAX, 1 }
> +};
> +
> +static const struct mtk_dpi_factor dpi_factor_mt8173[] = {
> + { 27000, 48 }, { 84000, 24 }, { 167000, 12 }, { U32_MAX, 6 }
> +};
> +
> +static const struct mtk_dpi_factor dpi_factor_mt8183[] = {
> + { 27000, 8 }, { 167000, 4 }, { U32_MAX, 2 }
> +};
> +
> +static const struct mtk_dpi_factor dpi_factor_mt8195_dp_intf[] = {
> + { 70000 - 1, 4 }, { 200000 - 1, 2 }, { U32_MAX, 1 }
> +};
> +
> static const struct mtk_dpi_conf mt8173_conf = {
> - .cal_factor = mt8173_calculate_factor,
> + .dpi_factor = dpi_factor_mt8173,
> + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8173),
> .reg_h_fre_con = 0xe0,
> .max_clock_khz = 300000,
> .output_fmts = mt8173_output_fmts,
> @@ -1039,7 +1035,8 @@ static const struct mtk_dpi_conf mt8173_conf = {
> };
>
> static const struct mtk_dpi_conf mt2701_conf = {
> - .cal_factor = mt2701_calculate_factor,
> + .dpi_factor = dpi_factor_mt2701,
> + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt2701),
> .reg_h_fre_con = 0xb0,
> .edge_sel_en = true,
> .max_clock_khz = 150000,
> @@ -1057,7 +1054,8 @@ static const struct mtk_dpi_conf mt2701_conf = {
> };
>
> static const struct mtk_dpi_conf mt8183_conf = {
> - .cal_factor = mt8183_calculate_factor,
> + .dpi_factor = dpi_factor_mt8183,
> + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
> .reg_h_fre_con = 0xe0,
> .max_clock_khz = 100000,
> .output_fmts = mt8183_output_fmts,
> @@ -1074,7 +1072,8 @@ static const struct mtk_dpi_conf mt8183_conf = {
> };
>
> static const struct mtk_dpi_conf mt8186_conf = {
> - .cal_factor = mt8183_calculate_factor,
> + .dpi_factor = dpi_factor_mt8183,
> + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
> .reg_h_fre_con = 0xe0,
> .max_clock_khz = 150000,
> .output_fmts = mt8183_output_fmts,
> @@ -1092,7 +1091,8 @@ static const struct mtk_dpi_conf mt8186_conf = {
> };
>
> static const struct mtk_dpi_conf mt8192_conf = {
> - .cal_factor = mt8183_calculate_factor,
> + .dpi_factor = dpi_factor_mt8183,
> + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
> .reg_h_fre_con = 0xe0,
> .max_clock_khz = 150000,
> .output_fmts = mt8183_output_fmts,
> @@ -1109,7 +1109,8 @@ static const struct mtk_dpi_conf mt8192_conf = {
> };
>
> static const struct mtk_dpi_conf mt8195_dpintf_conf = {
> - .cal_factor = mt8195_dpintf_calculate_factor,
> + .dpi_factor = dpi_factor_mt8195_dp_intf,
> + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf),
> .max_clock_khz = 600000,
> .output_fmts = mt8195_output_fmts,
> .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 03/43] drm/mediatek: mtk_dpi: Use an array for pixclk factor calculation
2025-02-17 15:47 ` [PATCH v7 03/43] drm/mediatek: mtk_dpi: Use an array for pixclk factor calculation AngeloGioacchino Del Regno
2025-03-02 10:53 ` Chun-Kuang Hu
@ 2025-03-02 11:03 ` Chun-Kuang Hu
1 sibling, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-03-02 11:03 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:49寫道：
>
> Setting the TVD PLL clock requires to multiply the target pixel
> clock by a specific constant factor to achieve the target PLL
> frequency, and this is done to reduce jitter to acceptable levels.
>
> On all MediaTek SoCs, the factor is not retrieved by any real kind
> of calculation but rather by checking if the target pixel clock
> is less than a specified frequency, hence assigning a function
> pointer for just a bunch of if branches does enlarge the code
> size for little reason.
>
> Remove all SoC-specific functions, add a structure `mtk_dpi_factor`
> that holds a clock frequency and corresponding PLL factor, and
> declare the constraints for each SoC in form of an array of said
> structure.
> Instead of function pointers, this structure (and its size) is then
> assigned to each SoC's platform data.
>
> The "calculation" is then performed with a new static function
> mtk_dpi_calculate_factor(dpi, mode_clk) that iterates through all
> of the entries of the aforementioned array and returns the right
> factor.
>
> If no factor is found, the lowest possible factor is returned,
> mimicking the same flow as all of the old per-SoC calculation
> functions.
>
> This commit brings no functional change.
After fix conflicts, applied to mediatek-drm-next [1], thanks.
[1] https://web.git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 103 +++++++++++++++--------------
> 1 file changed, 52 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index fc937490feda..41fdc193891a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -118,9 +118,15 @@ struct mtk_dpi_yc_limit {
> u16 c_bottom;
> };
>
> +struct mtk_dpi_factor {
> + u32 clock;
> + u8 factor;
> +};
> +
> /**
> * struct mtk_dpi_conf - Configuration of mediatek dpi.
> - * @cal_factor: Callback function to calculate factor value.
> + * @dpi_factor: SoC-specific pixel clock PLL factor values.
> + * @num_dpi_factor: Number of pixel clock PLL factor values.
> * @reg_h_fre_con: Register address of frequency control.
> * @max_clock_khz: Max clock frequency supported for this SoCs in khz units.
> * @edge_sel_en: Enable of edge selection.
> @@ -141,7 +147,8 @@ struct mtk_dpi_yc_limit {
> * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
> */
> struct mtk_dpi_conf {
> - unsigned int (*cal_factor)(int clock);
> + const struct mtk_dpi_factor *dpi_factor;
> + const u8 num_dpi_factor;
> u32 reg_h_fre_con;
> u32 max_clock_khz;
> bool edge_sel_en;
> @@ -516,6 +523,20 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
> return ret;
> }
>
> +static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode_clk)
> +{
> + const struct mtk_dpi_factor *dpi_factor = dpi->conf->dpi_factor;
> + int i;
> +
> + for (i = 0; i < dpi->conf->num_dpi_factor; i++) {
> + if (mode_clk <= dpi_factor[i].clock)
> + return dpi_factor[i].factor;
> + }
> +
> + /* If no match try the lowest possible factor */
> + return dpi_factor[dpi->conf->num_dpi_factor - 1].factor;
> +}
> +
> static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> struct drm_display_mode *mode)
> {
> @@ -530,7 +551,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> unsigned int factor;
>
> /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
> - factor = dpi->conf->cal_factor(mode->clock);
> + factor = mtk_dpi_calculate_factor(dpi, mode_clk);
> drm_display_mode_to_videomode(mode, &vm);
> pll_rate = vm.pixelclock * factor;
>
> @@ -965,48 +986,6 @@ static const struct component_ops mtk_dpi_component_ops = {
> .unbind = mtk_dpi_unbind,
> };
>
> -static unsigned int mt8173_calculate_factor(int clock)
> -{
> - if (clock <= 27000)
> - return 3 << 4;
> - else if (clock <= 84000)
> - return 3 << 3;
> - else if (clock <= 167000)
> - return 3 << 2;
> - else
> - return 3 << 1;
> -}
> -
> -static unsigned int mt2701_calculate_factor(int clock)
> -{
> - if (clock <= 64000)
> - return 4;
> - else if (clock <= 128000)
> - return 2;
> - else
> - return 1;
> -}
> -
> -static unsigned int mt8183_calculate_factor(int clock)
> -{
> - if (clock <= 27000)
> - return 8;
> - else if (clock <= 167000)
> - return 4;
> - else
> - return 2;
> -}
> -
> -static unsigned int mt8195_dpintf_calculate_factor(int clock)
> -{
> - if (clock < 70000)
> - return 4;
> - else if (clock < 200000)
> - return 2;
> - else
> - return 1;
> -}
> -
> static const u32 mt8173_output_fmts[] = {
> MEDIA_BUS_FMT_RGB888_1X24,
> };
> @@ -1021,8 +1000,25 @@ static const u32 mt8195_output_fmts[] = {
> MEDIA_BUS_FMT_YUYV8_1X16,
> };
>
> +static const struct mtk_dpi_factor dpi_factor_mt2701[] = {
> + { 64000, 4 }, { 128000, 2 }, { U32_MAX, 1 }
> +};
> +
> +static const struct mtk_dpi_factor dpi_factor_mt8173[] = {
> + { 27000, 48 }, { 84000, 24 }, { 167000, 12 }, { U32_MAX, 6 }
> +};
> +
> +static const struct mtk_dpi_factor dpi_factor_mt8183[] = {
> + { 27000, 8 }, { 167000, 4 }, { U32_MAX, 2 }
> +};
> +
> +static const struct mtk_dpi_factor dpi_factor_mt8195_dp_intf[] = {
> + { 70000 - 1, 4 }, { 200000 - 1, 2 }, { U32_MAX, 1 }
> +};
> +
> static const struct mtk_dpi_conf mt8173_conf = {
> - .cal_factor = mt8173_calculate_factor,
> + .dpi_factor = dpi_factor_mt8173,
> + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8173),
> .reg_h_fre_con = 0xe0,
> .max_clock_khz = 300000,
> .output_fmts = mt8173_output_fmts,
> @@ -1039,7 +1035,8 @@ static const struct mtk_dpi_conf mt8173_conf = {
> };
>
> static const struct mtk_dpi_conf mt2701_conf = {
> - .cal_factor = mt2701_calculate_factor,
> + .dpi_factor = dpi_factor_mt2701,
> + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt2701),
> .reg_h_fre_con = 0xb0,
> .edge_sel_en = true,
> .max_clock_khz = 150000,
> @@ -1057,7 +1054,8 @@ static const struct mtk_dpi_conf mt2701_conf = {
> };
>
> static const struct mtk_dpi_conf mt8183_conf = {
> - .cal_factor = mt8183_calculate_factor,
> + .dpi_factor = dpi_factor_mt8183,
> + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
> .reg_h_fre_con = 0xe0,
> .max_clock_khz = 100000,
> .output_fmts = mt8183_output_fmts,
> @@ -1074,7 +1072,8 @@ static const struct mtk_dpi_conf mt8183_conf = {
> };
>
> static const struct mtk_dpi_conf mt8186_conf = {
> - .cal_factor = mt8183_calculate_factor,
> + .dpi_factor = dpi_factor_mt8183,
> + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
> .reg_h_fre_con = 0xe0,
> .max_clock_khz = 150000,
> .output_fmts = mt8183_output_fmts,
> @@ -1092,7 +1091,8 @@ static const struct mtk_dpi_conf mt8186_conf = {
> };
>
> static const struct mtk_dpi_conf mt8192_conf = {
> - .cal_factor = mt8183_calculate_factor,
> + .dpi_factor = dpi_factor_mt8183,
> + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
> .reg_h_fre_con = 0xe0,
> .max_clock_khz = 150000,
> .output_fmts = mt8183_output_fmts,
> @@ -1109,7 +1109,8 @@ static const struct mtk_dpi_conf mt8192_conf = {
> };
>
> static const struct mtk_dpi_conf mt8195_dpintf_conf = {
> - .cal_factor = mt8195_dpintf_calculate_factor,
> + .dpi_factor = dpi_factor_mt8195_dp_intf,
> + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf),
> .max_clock_khz = 600000,
> .output_fmts = mt8195_output_fmts,
> .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 04/43] drm/mediatek: mtk_dpi: Move pixel clock setting flow to function
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (2 preceding siblings ...)
2025-02-17 15:47 ` [PATCH v7 03/43] drm/mediatek: mtk_dpi: Use an array for pixclk factor calculation AngeloGioacchino Del Regno
@ 2025-02-17 15:47 ` AngeloGioacchino Del Regno
2025-03-02 11:08 ` Chun-Kuang Hu
2025-02-17 15:47 ` [PATCH v7 05/43] drm/mediatek: mtk_dpi: Add checks for reg_h_fre_con existence AngeloGioacchino Del Regno
` (39 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:47 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
In preparation for adding support for the DPI IP found in MT8195
and in MT8188 used for HDMI, move the code flow for calculation
and setting of the DPI pixel clock to a separate function called
mtk_dpi_set_pixel_clk().
This was done because, on those platforms, the DPI instance that
is used for HDMI will get its pixel clock from the HDMI clock,
hence it is not necessary, nor desirable, to calculate or set
the pixel clock in DPI.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 43 +++++++++++++++++-------------
1 file changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 41fdc193891a..59c2e4f32a61 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -537,26 +537,17 @@ static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode_clk)
return dpi_factor[dpi->conf->num_dpi_factor - 1].factor;
}
-static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
- struct drm_display_mode *mode)
+static void mtk_dpi_set_pixel_clk(struct mtk_dpi *dpi, struct videomode *vm, int mode_clk)
{
- struct mtk_dpi_polarities dpi_pol;
- struct mtk_dpi_sync_param hsync;
- struct mtk_dpi_sync_param vsync_lodd = { 0 };
- struct mtk_dpi_sync_param vsync_leven = { 0 };
- struct mtk_dpi_sync_param vsync_rodd = { 0 };
- struct mtk_dpi_sync_param vsync_reven = { 0 };
- struct videomode vm = { 0 };
unsigned long pll_rate;
unsigned int factor;
/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
factor = mtk_dpi_calculate_factor(dpi, mode_clk);
- drm_display_mode_to_videomode(mode, &vm);
- pll_rate = vm.pixelclock * factor;
+ pll_rate = vm->pixelclock * factor;
dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
- pll_rate, vm.pixelclock);
+ pll_rate, vm->pixelclock);
clk_set_rate(dpi->tvd_clk, pll_rate);
pll_rate = clk_get_rate(dpi->tvd_clk);
@@ -566,20 +557,34 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
* pixels for each iteration: divide the clock by this number and
* adjust the display porches accordingly.
*/
- vm.pixelclock = pll_rate / factor;
- vm.pixelclock /= dpi->conf->pixels_per_iter;
+ vm->pixelclock = pll_rate / factor;
+ vm->pixelclock /= dpi->conf->pixels_per_iter;
if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
(dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
- clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
+ clk_set_rate(dpi->pixel_clk, vm->pixelclock * 2);
else
- clk_set_rate(dpi->pixel_clk, vm.pixelclock);
+ clk_set_rate(dpi->pixel_clk, vm->pixelclock);
-
- vm.pixelclock = clk_get_rate(dpi->pixel_clk);
+ vm->pixelclock = clk_get_rate(dpi->pixel_clk);
dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
- pll_rate, vm.pixelclock);
+ pll_rate, vm->pixelclock);
+}
+
+static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
+ struct drm_display_mode *mode)
+{
+ struct mtk_dpi_polarities dpi_pol;
+ struct mtk_dpi_sync_param hsync;
+ struct mtk_dpi_sync_param vsync_lodd = { 0 };
+ struct mtk_dpi_sync_param vsync_leven = { 0 };
+ struct mtk_dpi_sync_param vsync_rodd = { 0 };
+ struct mtk_dpi_sync_param vsync_reven = { 0 };
+ struct videomode vm = { 0 };
+
+ drm_display_mode_to_videomode(mode, &vm);
+ mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock);
dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 04/43] drm/mediatek: mtk_dpi: Move pixel clock setting flow to function
2025-02-17 15:47 ` [PATCH v7 04/43] drm/mediatek: mtk_dpi: Move pixel clock setting flow to function AngeloGioacchino Del Regno
@ 2025-03-02 11:08 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-03-02 11:08 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:49寫道：
>
> In preparation for adding support for the DPI IP found in MT8195
> and in MT8188 used for HDMI, move the code flow for calculation
> and setting of the DPI pixel clock to a separate function called
> mtk_dpi_set_pixel_clk().
>
> This was done because, on those platforms, the DPI instance that
> is used for HDMI will get its pixel clock from the HDMI clock,
> hence it is not necessary, nor desirable, to calculate or set
> the pixel clock in DPI.
After fix conflicts, applied to mediatek-drm-next [1], thanks.
[1] https://web.git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 43 +++++++++++++++++-------------
> 1 file changed, 24 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 41fdc193891a..59c2e4f32a61 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -537,26 +537,17 @@ static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode_clk)
> return dpi_factor[dpi->conf->num_dpi_factor - 1].factor;
> }
>
> -static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> - struct drm_display_mode *mode)
> +static void mtk_dpi_set_pixel_clk(struct mtk_dpi *dpi, struct videomode *vm, int mode_clk)
> {
> - struct mtk_dpi_polarities dpi_pol;
> - struct mtk_dpi_sync_param hsync;
> - struct mtk_dpi_sync_param vsync_lodd = { 0 };
> - struct mtk_dpi_sync_param vsync_leven = { 0 };
> - struct mtk_dpi_sync_param vsync_rodd = { 0 };
> - struct mtk_dpi_sync_param vsync_reven = { 0 };
> - struct videomode vm = { 0 };
> unsigned long pll_rate;
> unsigned int factor;
>
> /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
> factor = mtk_dpi_calculate_factor(dpi, mode_clk);
> - drm_display_mode_to_videomode(mode, &vm);
> - pll_rate = vm.pixelclock * factor;
> + pll_rate = vm->pixelclock * factor;
>
> dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
> - pll_rate, vm.pixelclock);
> + pll_rate, vm->pixelclock);
>
> clk_set_rate(dpi->tvd_clk, pll_rate);
> pll_rate = clk_get_rate(dpi->tvd_clk);
> @@ -566,20 +557,34 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> * pixels for each iteration: divide the clock by this number and
> * adjust the display porches accordingly.
> */
> - vm.pixelclock = pll_rate / factor;
> - vm.pixelclock /= dpi->conf->pixels_per_iter;
> + vm->pixelclock = pll_rate / factor;
> + vm->pixelclock /= dpi->conf->pixels_per_iter;
>
> if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
> (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
> - clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
> + clk_set_rate(dpi->pixel_clk, vm->pixelclock * 2);
> else
> - clk_set_rate(dpi->pixel_clk, vm.pixelclock);
> + clk_set_rate(dpi->pixel_clk, vm->pixelclock);
>
> -
> - vm.pixelclock = clk_get_rate(dpi->pixel_clk);
> + vm->pixelclock = clk_get_rate(dpi->pixel_clk);
>
> dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
> - pll_rate, vm.pixelclock);
> + pll_rate, vm->pixelclock);
> +}
> +
> +static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> + struct drm_display_mode *mode)
> +{
> + struct mtk_dpi_polarities dpi_pol;
> + struct mtk_dpi_sync_param hsync;
> + struct mtk_dpi_sync_param vsync_lodd = { 0 };
> + struct mtk_dpi_sync_param vsync_leven = { 0 };
> + struct mtk_dpi_sync_param vsync_rodd = { 0 };
> + struct mtk_dpi_sync_param vsync_reven = { 0 };
> + struct videomode vm = { 0 };
> +
> + drm_display_mode_to_videomode(mode, &vm);
> + mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock);
>
> dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
> dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 05/43] drm/mediatek: mtk_dpi: Add checks for reg_h_fre_con existence
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (3 preceding siblings ...)
2025-02-17 15:47 ` [PATCH v7 04/43] drm/mediatek: mtk_dpi: Move pixel clock setting flow to function AngeloGioacchino Del Regno
@ 2025-02-17 15:47 ` AngeloGioacchino Del Regno
2025-03-02 11:06 ` Chun-Kuang Hu
2025-02-17 15:47 ` [PATCH v7 06/43] drm/mediatek: mtk_dpi: Move the input_2p_en bit to platform data AngeloGioacchino Del Regno
` (38 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:47 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
In preparation for adding support for newer DPI instances which
do support direct-pin but do not have any H_FRE_CON register,
like the one found in MT8195 and MT8188, add a branch to check
if the reg_h_fre_con variable was declared in the mtk_dpi_conf
structure for the probed SoC DPI version.
As a note, this is useful specifically only for cases in which
the support_direct_pin variable is true, so mt8195-dpintf is
not affected by any issue.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 59c2e4f32a61..bb1a17f1384b 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -431,12 +431,13 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
{
- mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
+ if (dpi->conf->reg_h_fre_con)
+ mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
}
static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
{
- if (dpi->conf->edge_sel_en)
+ if (dpi->conf->edge_sel_en && dpi->conf->reg_h_fre_con)
mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
}
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 05/43] drm/mediatek: mtk_dpi: Add checks for reg_h_fre_con existence
2025-02-17 15:47 ` [PATCH v7 05/43] drm/mediatek: mtk_dpi: Add checks for reg_h_fre_con existence AngeloGioacchino Del Regno
@ 2025-03-02 11:06 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-03-02 11:06 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:49寫道：
>
> In preparation for adding support for newer DPI instances which
> do support direct-pin but do not have any H_FRE_CON register,
> like the one found in MT8195 and MT8188, add a branch to check
> if the reg_h_fre_con variable was declared in the mtk_dpi_conf
> structure for the probed SoC DPI version.
>
> As a note, this is useful specifically only for cases in which
> the support_direct_pin variable is true, so mt8195-dpintf is
> not affected by any issue.
Applied to mediatek-drm-next [1], thanks.
[1] https://web.git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 59c2e4f32a61..bb1a17f1384b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -431,12 +431,13 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
>
> static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
> {
> - mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
> + if (dpi->conf->reg_h_fre_con)
> + mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
> }
>
> static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
> {
> - if (dpi->conf->edge_sel_en)
> + if (dpi->conf->edge_sel_en && dpi->conf->reg_h_fre_con)
> mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
> }
>
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 06/43] drm/mediatek: mtk_dpi: Move the input_2p_en bit to platform data
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (4 preceding siblings ...)
2025-02-17 15:47 ` [PATCH v7 05/43] drm/mediatek: mtk_dpi: Add checks for reg_h_fre_con existence AngeloGioacchino Del Regno
@ 2025-02-17 15:47 ` AngeloGioacchino Del Regno
2025-03-02 11:14 ` Chun-Kuang Hu
2025-02-17 15:48 ` [PATCH v7 07/43] drm/mediatek: mtk_dpi: Add support for DPI input clock from HDMI AngeloGioacchino Del Regno
` (37 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:47 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
In preparation for adding support for MT8195's HDMI reserved DPI
instance, move the input_2p_en bit for DP_INTF to platform data.
While at it, remove the input_2pixel member from platform data as
having this bit implies that the 2pixel feature must be enabled.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index bb1a17f1384b..9a6c0f75f764 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -135,14 +135,14 @@ struct mtk_dpi_factor {
* @is_ck_de_pol: Support CK/DE polarity.
* @swap_input_support: Support input swap function.
* @support_direct_pin: IP supports direct connection to dpi panels.
- * @input_2pixel: Input pixel of dp_intf is 2 pixel per round, so enable this
- * config to enable this feature.
* @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH
* (no shift).
* @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift).
* @channel_swap_shift: Shift value of channel swap.
* @yuv422_en_bit: Enable bit of yuv422.
* @csc_enable_bit: Enable bit of CSC.
+ * @input_2p_en_bit: Enable bit for input two pixel per round feature.
+ If present, implies that the feature must be enabled.
* @pixels_per_iter: Quantity of transferred pixels per iteration.
* @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
*/
@@ -157,12 +157,12 @@ struct mtk_dpi_conf {
bool is_ck_de_pol;
bool swap_input_support;
bool support_direct_pin;
- bool input_2pixel;
u32 dimension_mask;
u32 hvsize_mask;
u32 channel_swap_shift;
u32 yuv422_en_bit;
u32 csc_enable_bit;
+ u32 input_2p_en_bit;
u32 pixels_per_iter;
bool edge_cfg_in_mmsys;
};
@@ -651,9 +651,9 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
mtk_dpi_dual_edge(dpi);
mtk_dpi_config_disable_edge(dpi);
}
- if (dpi->conf->input_2pixel) {
- mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN,
- DPINTF_INPUT_2P_EN);
+ if (dpi->conf->input_2p_en_bit) {
+ mtk_dpi_mask(dpi, DPI_CON, dpi->conf->input_2p_en_bit,
+ dpi->conf->input_2p_en_bit);
}
mtk_dpi_sw_reset(dpi, false);
@@ -1121,12 +1121,12 @@ static const struct mtk_dpi_conf mt8195_dpintf_conf = {
.output_fmts = mt8195_output_fmts,
.num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),
.pixels_per_iter = 4,
- .input_2pixel = true,
.dimension_mask = DPINTF_HPW_MASK,
.hvsize_mask = DPINTF_HSIZE_MASK,
.channel_swap_shift = DPINTF_CH_SWAP,
.yuv422_en_bit = DPINTF_YUV422_EN,
.csc_enable_bit = DPINTF_CSC_ENABLE,
+ .input_2p_en_bit = DPINTF_INPUT_2P_EN,
};
static int mtk_dpi_probe(struct platform_device *pdev)
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 06/43] drm/mediatek: mtk_dpi: Move the input_2p_en bit to platform data
2025-02-17 15:47 ` [PATCH v7 06/43] drm/mediatek: mtk_dpi: Move the input_2p_en bit to platform data AngeloGioacchino Del Regno
@ 2025-03-02 11:14 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-03-02 11:14 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:49寫道：
>
> In preparation for adding support for MT8195's HDMI reserved DPI
> instance, move the input_2p_en bit for DP_INTF to platform data.
>
> While at it, remove the input_2pixel member from platform data as
> having this bit implies that the 2pixel feature must be enabled.
Remember to run check patch, after fix check patch error, applied to
mediatek-drm-next [1], thanks.
[1] https://web.git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index bb1a17f1384b..9a6c0f75f764 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -135,14 +135,14 @@ struct mtk_dpi_factor {
> * @is_ck_de_pol: Support CK/DE polarity.
> * @swap_input_support: Support input swap function.
> * @support_direct_pin: IP supports direct connection to dpi panels.
> - * @input_2pixel: Input pixel of dp_intf is 2 pixel per round, so enable this
> - * config to enable this feature.
> * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH
> * (no shift).
> * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift).
> * @channel_swap_shift: Shift value of channel swap.
> * @yuv422_en_bit: Enable bit of yuv422.
> * @csc_enable_bit: Enable bit of CSC.
> + * @input_2p_en_bit: Enable bit for input two pixel per round feature.
> + If present, implies that the feature must be enabled.
> * @pixels_per_iter: Quantity of transferred pixels per iteration.
> * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
> */
> @@ -157,12 +157,12 @@ struct mtk_dpi_conf {
> bool is_ck_de_pol;
> bool swap_input_support;
> bool support_direct_pin;
> - bool input_2pixel;
> u32 dimension_mask;
> u32 hvsize_mask;
> u32 channel_swap_shift;
> u32 yuv422_en_bit;
> u32 csc_enable_bit;
> + u32 input_2p_en_bit;
> u32 pixels_per_iter;
> bool edge_cfg_in_mmsys;
> };
> @@ -651,9 +651,9 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> mtk_dpi_dual_edge(dpi);
> mtk_dpi_config_disable_edge(dpi);
> }
> - if (dpi->conf->input_2pixel) {
> - mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN,
> - DPINTF_INPUT_2P_EN);
> + if (dpi->conf->input_2p_en_bit) {
> + mtk_dpi_mask(dpi, DPI_CON, dpi->conf->input_2p_en_bit,
> + dpi->conf->input_2p_en_bit);
> }
> mtk_dpi_sw_reset(dpi, false);
>
> @@ -1121,12 +1121,12 @@ static const struct mtk_dpi_conf mt8195_dpintf_conf = {
> .output_fmts = mt8195_output_fmts,
> .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),
> .pixels_per_iter = 4,
> - .input_2pixel = true,
> .dimension_mask = DPINTF_HPW_MASK,
> .hvsize_mask = DPINTF_HSIZE_MASK,
> .channel_swap_shift = DPINTF_CH_SWAP,
> .yuv422_en_bit = DPINTF_YUV422_EN,
> .csc_enable_bit = DPINTF_CSC_ENABLE,
> + .input_2p_en_bit = DPINTF_INPUT_2P_EN,
> };
>
> static int mtk_dpi_probe(struct platform_device *pdev)
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 07/43] drm/mediatek: mtk_dpi: Add support for DPI input clock from HDMI
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (5 preceding siblings ...)
2025-02-17 15:47 ` [PATCH v7 06/43] drm/mediatek: mtk_dpi: Move the input_2p_en bit to platform data AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-27 3:45 ` CK Hu (胡俊光)
2025-03-02 11:24 ` Chun-Kuang Hu
2025-02-17 15:48 ` [PATCH v7 08/43] drm/mediatek: mtk_dpi: Support AFIFO 1T1P output and conversion AngeloGioacchino Del Regno
` (36 subsequent siblings)
43 siblings, 2 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
On some SoCs, like MT8195 and MT8188, the DPI instance that is
reserved to the HDMI Transmitter uses a different clock topology.
In this case, the DPI is clocked by the HDMI IP, and this outputs
its clock to the MM input of dpi_pixel_clk, which is essential to
enable register access to the DPI IP.
Add a `clocked_by_hdmi` member to struct mtk_dpi_conf, and check
it to avoid enabling the DPI clocks in the mediatek-drm internal
.start() callback (and avoid disabing in the .stop() component
callback): this will make sure that the clock configuration
sequence is respected during display pipeline setup by following
the bridge ops between DPI and HDMI, where the HDMI driver is
expected to enable the clocks in the bridge's pre_enable(), and
DPI in the enable() cb.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 9a6c0f75f764..9f83e82437dd 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -145,6 +145,8 @@ struct mtk_dpi_factor {
If present, implies that the feature must be enabled.
* @pixels_per_iter: Quantity of transferred pixels per iteration.
* @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
+ * @clocked_by_hdmi: HDMI IP outputs clock to dpi_pixel_clk input clock, needed
+ * for DPI registers access.
*/
struct mtk_dpi_conf {
const struct mtk_dpi_factor *dpi_factor;
@@ -165,6 +167,7 @@ struct mtk_dpi_conf {
u32 input_2p_en_bit;
u32 pixels_per_iter;
bool edge_cfg_in_mmsys;
+ bool clocked_by_hdmi;
};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -585,7 +588,9 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
struct videomode vm = { 0 };
drm_display_mode_to_videomode(mode, &vm);
- mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock);
+
+ if (!dpi->conf->clocked_by_hdmi)
+ mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock);
dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
@@ -920,14 +925,16 @@ void mtk_dpi_start(struct device *dev)
{
struct mtk_dpi *dpi = dev_get_drvdata(dev);
- mtk_dpi_power_on(dpi);
+ if (!dpi->conf->clocked_by_hdmi)
+ mtk_dpi_power_on(dpi);
}
void mtk_dpi_stop(struct device *dev)
{
struct mtk_dpi *dpi = dev_get_drvdata(dev);
- mtk_dpi_power_off(dpi);
+ if (!dpi->conf->clocked_by_hdmi)
+ mtk_dpi_power_off(dpi);
}
unsigned int mtk_dpi_encoder_index(struct device *dev)
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 07/43] drm/mediatek: mtk_dpi: Add support for DPI input clock from HDMI
2025-02-17 15:48 ` [PATCH v7 07/43] drm/mediatek: mtk_dpi: Add support for DPI input clock from HDMI AngeloGioacchino Del Regno
@ 2025-02-27 3:45 ` CK Hu (胡俊光)
2025-03-02 11:24 ` Chun-Kuang Hu
1 sibling, 0 replies; 74+ messages in thread
From: CK Hu (胡俊光) @ 2025-02-27 3:45 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, chunkuang.hu
Cc: robh, jie.qiu, tzimmermann, simona, mripard,
Jitao Shi (石记涛),
linux-mediatek, dri-devel, maarten.lankhorst, linux-kernel,
devicetree, kernel, dmitry.baryshkov, krzk+dt,
Lewis Liao (廖柏鈞),
p.zabel, conor+dt, TommyYL Chen (陳彥良),
Ives Chenjh (陳俊弘),
airlied, linux-arm-kernel, matthias.bgg,
Jason-JH Lin (林睿祥),
junzhi.zhao
On Mon, 2025-02-17 at 16:48 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
>
>
> On some SoCs, like MT8195 and MT8188, the DPI instance that is
> reserved to the HDMI Transmitter uses a different clock topology.
>
> In this case, the DPI is clocked by the HDMI IP, and this outputs
> its clock to the MM input of dpi_pixel_clk, which is essential to
> enable register access to the DPI IP.
>
> Add a `clocked_by_hdmi` member to struct mtk_dpi_conf, and check
> it to avoid enabling the DPI clocks in the mediatek-drm internal
> .start() callback (and avoid disabing in the .stop() component
> callback): this will make sure that the clock configuration
> sequence is respected during display pipeline setup by following
> the bridge ops between DPI and HDMI, where the HDMI driver is
> expected to enable the clocks in the bridge's pre_enable(), and
> DPI in the enable() cb.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 9a6c0f75f764..9f83e82437dd 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -145,6 +145,8 @@ struct mtk_dpi_factor {
> If present, implies that the feature must be enabled.
> * @pixels_per_iter: Quantity of transferred pixels per iteration.
> * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
> + * @clocked_by_hdmi: HDMI IP outputs clock to dpi_pixel_clk input clock, needed
> + * for DPI registers access.
> */
> struct mtk_dpi_conf {
> const struct mtk_dpi_factor *dpi_factor;
> @@ -165,6 +167,7 @@ struct mtk_dpi_conf {
> u32 input_2p_en_bit;
> u32 pixels_per_iter;
> bool edge_cfg_in_mmsys;
> + bool clocked_by_hdmi;
> };
>
> static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
> @@ -585,7 +588,9 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> struct videomode vm = { 0 };
>
> drm_display_mode_to_videomode(mode, &vm);
> - mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock);
> +
> + if (!dpi->conf->clocked_by_hdmi)
> + mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock);
>
> dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
> dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
> @@ -920,14 +925,16 @@ void mtk_dpi_start(struct device *dev)
> {
> struct mtk_dpi *dpi = dev_get_drvdata(dev);
>
> - mtk_dpi_power_on(dpi);
> + if (!dpi->conf->clocked_by_hdmi)
> + mtk_dpi_power_on(dpi);
> }
>
> void mtk_dpi_stop(struct device *dev)
> {
> struct mtk_dpi *dpi = dev_get_drvdata(dev);
>
> - mtk_dpi_power_off(dpi);
> + if (!dpi->conf->clocked_by_hdmi)
> + mtk_dpi_power_off(dpi);
> }
>
> unsigned int mtk_dpi_encoder_index(struct device *dev)
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 07/43] drm/mediatek: mtk_dpi: Add support for DPI input clock from HDMI
2025-02-17 15:48 ` [PATCH v7 07/43] drm/mediatek: mtk_dpi: Add support for DPI input clock from HDMI AngeloGioacchino Del Regno
2025-02-27 3:45 ` CK Hu (胡俊光)
@ 2025-03-02 11:24 ` Chun-Kuang Hu
1 sibling, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-03-02 11:24 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:49寫道：
>
> On some SoCs, like MT8195 and MT8188, the DPI instance that is
> reserved to the HDMI Transmitter uses a different clock topology.
>
> In this case, the DPI is clocked by the HDMI IP, and this outputs
> its clock to the MM input of dpi_pixel_clk, which is essential to
> enable register access to the DPI IP.
>
> Add a `clocked_by_hdmi` member to struct mtk_dpi_conf, and check
> it to avoid enabling the DPI clocks in the mediatek-drm internal
> .start() callback (and avoid disabing in the .stop() component
> callback): this will make sure that the clock configuration
> sequence is respected during display pipeline setup by following
> the bridge ops between DPI and HDMI, where the HDMI driver is
> expected to enable the clocks in the bridge's pre_enable(), and
> DPI in the enable() cb.
After fix conflicts, applied to mediatek-drm-next [1], thanks.
[1] https://web.git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 9a6c0f75f764..9f83e82437dd 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -145,6 +145,8 @@ struct mtk_dpi_factor {
> If present, implies that the feature must be enabled.
> * @pixels_per_iter: Quantity of transferred pixels per iteration.
> * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
> + * @clocked_by_hdmi: HDMI IP outputs clock to dpi_pixel_clk input clock, needed
> + * for DPI registers access.
> */
> struct mtk_dpi_conf {
> const struct mtk_dpi_factor *dpi_factor;
> @@ -165,6 +167,7 @@ struct mtk_dpi_conf {
> u32 input_2p_en_bit;
> u32 pixels_per_iter;
> bool edge_cfg_in_mmsys;
> + bool clocked_by_hdmi;
> };
>
> static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
> @@ -585,7 +588,9 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> struct videomode vm = { 0 };
>
> drm_display_mode_to_videomode(mode, &vm);
> - mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock);
> +
> + if (!dpi->conf->clocked_by_hdmi)
> + mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock);
>
> dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
> dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
> @@ -920,14 +925,16 @@ void mtk_dpi_start(struct device *dev)
> {
> struct mtk_dpi *dpi = dev_get_drvdata(dev);
>
> - mtk_dpi_power_on(dpi);
> + if (!dpi->conf->clocked_by_hdmi)
> + mtk_dpi_power_on(dpi);
> }
>
> void mtk_dpi_stop(struct device *dev)
> {
> struct mtk_dpi *dpi = dev_get_drvdata(dev);
>
> - mtk_dpi_power_off(dpi);
> + if (!dpi->conf->clocked_by_hdmi)
> + mtk_dpi_power_off(dpi);
> }
>
> unsigned int mtk_dpi_encoder_index(struct device *dev)
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 08/43] drm/mediatek: mtk_dpi: Support AFIFO 1T1P output and conversion
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (6 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 07/43] drm/mediatek: mtk_dpi: Add support for DPI input clock from HDMI AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-03-02 11:29 ` Chun-Kuang Hu
2025-02-17 15:48 ` [PATCH v7 09/43] drm/mediatek: mtk_dpi: Explicitly manage TVD clock in power on/off AngeloGioacchino Del Regno
` (35 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
On some SoCs, like MT8195 and MT8188, the DPI's FIFO controller
(afifo) supports outputting either one or two pixels per round
regardless of the input being 1T1P or 1T2P.
Add a `output_1pixel` member to struct mtk_dpi_conf which, if
set, will enable outputting one pixel per clock.
In case the input is two pixel per clock (1T2P), the AFIFO HW
will automatically (and internally) convert it to 1T1P.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 9f83e82437dd..e12dc73ed79c 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -147,6 +147,8 @@ struct mtk_dpi_factor {
* @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
* @clocked_by_hdmi: HDMI IP outputs clock to dpi_pixel_clk input clock, needed
* for DPI registers access.
+ * @output_1pixel: Enable outputting one pixel per round; if the input is two pixel per
+ * round, the DPI hardware will internally transform it to 1T1P.
*/
struct mtk_dpi_conf {
const struct mtk_dpi_factor *dpi_factor;
@@ -168,6 +170,7 @@ struct mtk_dpi_conf {
u32 pixels_per_iter;
bool edge_cfg_in_mmsys;
bool clocked_by_hdmi;
+ bool output_1pixel;
};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -653,7 +656,13 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
if (dpi->conf->support_direct_pin) {
mtk_dpi_config_yc_map(dpi, dpi->yc_map);
mtk_dpi_config_2n_h_fre(dpi);
- mtk_dpi_dual_edge(dpi);
+
+ /* DPI can connect to either an external bridge or the internal HDMI encoder */
+ if (dpi->conf->output_1pixel)
+ mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN);
+ else
+ mtk_dpi_dual_edge(dpi);
+
mtk_dpi_config_disable_edge(dpi);
}
if (dpi->conf->input_2p_en_bit) {
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 08/43] drm/mediatek: mtk_dpi: Support AFIFO 1T1P output and conversion
2025-02-17 15:48 ` [PATCH v7 08/43] drm/mediatek: mtk_dpi: Support AFIFO 1T1P output and conversion AngeloGioacchino Del Regno
@ 2025-03-02 11:29 ` Chun-Kuang Hu
2025-03-02 14:01 ` Chun-Kuang Hu
0 siblings, 1 reply; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-03-02 11:29 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:49寫道：
>
> On some SoCs, like MT8195 and MT8188, the DPI's FIFO controller
> (afifo) supports outputting either one or two pixels per round
> regardless of the input being 1T1P or 1T2P.
>
> Add a `output_1pixel` member to struct mtk_dpi_conf which, if
> set, will enable outputting one pixel per clock.
>
> In case the input is two pixel per clock (1T2P), the AFIFO HW
> will automatically (and internally) convert it to 1T1P.
Applied to mediatek-drm-next [1], thanks.
[1] https://web.git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 9f83e82437dd..e12dc73ed79c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -147,6 +147,8 @@ struct mtk_dpi_factor {
> * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
> * @clocked_by_hdmi: HDMI IP outputs clock to dpi_pixel_clk input clock, needed
> * for DPI registers access.
> + * @output_1pixel: Enable outputting one pixel per round; if the input is two pixel per
> + * round, the DPI hardware will internally transform it to 1T1P.
> */
> struct mtk_dpi_conf {
> const struct mtk_dpi_factor *dpi_factor;
> @@ -168,6 +170,7 @@ struct mtk_dpi_conf {
> u32 pixels_per_iter;
> bool edge_cfg_in_mmsys;
> bool clocked_by_hdmi;
> + bool output_1pixel;
> };
>
> static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
> @@ -653,7 +656,13 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> if (dpi->conf->support_direct_pin) {
> mtk_dpi_config_yc_map(dpi, dpi->yc_map);
> mtk_dpi_config_2n_h_fre(dpi);
> - mtk_dpi_dual_edge(dpi);
> +
> + /* DPI can connect to either an external bridge or the internal HDMI encoder */
> + if (dpi->conf->output_1pixel)
> + mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN);
> + else
> + mtk_dpi_dual_edge(dpi);
> +
> mtk_dpi_config_disable_edge(dpi);
> }
> if (dpi->conf->input_2p_en_bit) {
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 08/43] drm/mediatek: mtk_dpi: Support AFIFO 1T1P output and conversion
2025-03-02 11:29 ` Chun-Kuang Hu
@ 2025-03-02 14:01 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-03-02 14:01 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: AngeloGioacchino Del Regno, p.zabel, airlied, simona,
maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt, conor+dt,
matthias.bgg, ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Chun-Kuang Hu <chunkuang.hu@kernel.org> 於 2025年3月2日 週日 下午7:29寫道：
>
> Hi, Angelo:
>
> AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
> 2025年2月17日 週一 下午11:49寫道：
> >
> > On some SoCs, like MT8195 and MT8188, the DPI's FIFO controller
> > (afifo) supports outputting either one or two pixels per round
> > regardless of the input being 1T1P or 1T2P.
> >
> > Add a `output_1pixel` member to struct mtk_dpi_conf which, if
> > set, will enable outputting one pixel per clock.
> >
> > In case the input is two pixel per clock (1T2P), the AFIFO HW
> > will automatically (and internally) convert it to 1T1P.
>
> Applied to mediatek-drm-next [1], thanks.
>
> [1] https://web.git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Fix build error then apply. Be care of patch quality.
Regards,
Chun-Kuang.
>
> Regards,
> Chun-Kuang.
>
> >
> > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_dpi.c | 11 ++++++++++-
> > 1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > index 9f83e82437dd..e12dc73ed79c 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > @@ -147,6 +147,8 @@ struct mtk_dpi_factor {
> > * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
> > * @clocked_by_hdmi: HDMI IP outputs clock to dpi_pixel_clk input clock, needed
> > * for DPI registers access.
> > + * @output_1pixel: Enable outputting one pixel per round; if the input is two pixel per
> > + * round, the DPI hardware will internally transform it to 1T1P.
> > */
> > struct mtk_dpi_conf {
> > const struct mtk_dpi_factor *dpi_factor;
> > @@ -168,6 +170,7 @@ struct mtk_dpi_conf {
> > u32 pixels_per_iter;
> > bool edge_cfg_in_mmsys;
> > bool clocked_by_hdmi;
> > + bool output_1pixel;
> > };
> >
> > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
> > @@ -653,7 +656,13 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> > if (dpi->conf->support_direct_pin) {
> > mtk_dpi_config_yc_map(dpi, dpi->yc_map);
> > mtk_dpi_config_2n_h_fre(dpi);
> > - mtk_dpi_dual_edge(dpi);
> > +
> > + /* DPI can connect to either an external bridge or the internal HDMI encoder */
> > + if (dpi->conf->output_1pixel)
> > + mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN);
> > + else
> > + mtk_dpi_dual_edge(dpi);
> > +
> > mtk_dpi_config_disable_edge(dpi);
> > }
> > if (dpi->conf->input_2p_en_bit) {
> > --
> > 2.48.1
> >
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 09/43] drm/mediatek: mtk_dpi: Explicitly manage TVD clock in power on/off
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (7 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 08/43] drm/mediatek: mtk_dpi: Support AFIFO 1T1P output and conversion AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-03-02 14:05 ` Chun-Kuang Hu
2025-02-17 15:48 ` [PATCH v7 10/43] drm/mediatek: Add support for MT8195 Digital Parallel Interface AngeloGioacchino Del Regno
` (34 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
In preparation for adding support for MT8195's HDMI reserved
DPI, add calls to clk_prepare_enable() / clk_disable_unprepare()
for the TVD clock: in this particular case, the aforementioned
clock is not (and cannot be) parented to neither pixel or engine
clocks hence it won't get enabled automatically by the clock
framework.
Please note that on all of the currently supported MediaTek
platforms, the TVD clock is always a parent of either pixel or
engine clocks, and this means that the common clock framework
is already enabling this clock before the children.
On such platforms, this commit will only increase the refcount
of the TVD clock without any functional change.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index e12dc73ed79c..ee952785866c 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -499,6 +499,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi)
mtk_dpi_disable(dpi);
clk_disable_unprepare(dpi->pixel_clk);
+ clk_disable_unprepare(dpi->tvd_clk);
clk_disable_unprepare(dpi->engine_clk);
}
@@ -515,6 +516,12 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
goto err_refcount;
}
+ ret = clk_prepare_enable(dpi->tvd_clk);
+ if (ret) {
+ dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret);
+ goto err_engine;
+ }
+
ret = clk_prepare_enable(dpi->pixel_clk);
if (ret) {
dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret);
@@ -524,6 +531,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
return 0;
err_pixel:
+ clk_disable_unprepare(dpi->tvd_clk);
+err_engine:
clk_disable_unprepare(dpi->engine_clk);
err_refcount:
dpi->refcount--;
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 09/43] drm/mediatek: mtk_dpi: Explicitly manage TVD clock in power on/off
2025-02-17 15:48 ` [PATCH v7 09/43] drm/mediatek: mtk_dpi: Explicitly manage TVD clock in power on/off AngeloGioacchino Del Regno
@ 2025-03-02 14:05 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-03-02 14:05 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:49寫道：
>
> In preparation for adding support for MT8195's HDMI reserved
> DPI, add calls to clk_prepare_enable() / clk_disable_unprepare()
> for the TVD clock: in this particular case, the aforementioned
> clock is not (and cannot be) parented to neither pixel or engine
> clocks hence it won't get enabled automatically by the clock
> framework.
>
> Please note that on all of the currently supported MediaTek
> platforms, the TVD clock is always a parent of either pixel or
> engine clocks, and this means that the common clock framework
> is already enabling this clock before the children.
> On such platforms, this commit will only increase the refcount
> of the TVD clock without any functional change.
Applied to mediatek-drm-next [1], thanks.
[1] https://web.git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index e12dc73ed79c..ee952785866c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -499,6 +499,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi)
>
> mtk_dpi_disable(dpi);
> clk_disable_unprepare(dpi->pixel_clk);
> + clk_disable_unprepare(dpi->tvd_clk);
> clk_disable_unprepare(dpi->engine_clk);
> }
>
> @@ -515,6 +516,12 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
> goto err_refcount;
> }
>
> + ret = clk_prepare_enable(dpi->tvd_clk);
> + if (ret) {
> + dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret);
> + goto err_engine;
> + }
> +
> ret = clk_prepare_enable(dpi->pixel_clk);
> if (ret) {
> dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret);
> @@ -524,6 +531,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
> return 0;
>
> err_pixel:
> + clk_disable_unprepare(dpi->tvd_clk);
> +err_engine:
> clk_disable_unprepare(dpi->engine_clk);
> err_refcount:
> dpi->refcount--;
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 10/43] drm/mediatek: Add support for MT8195 Digital Parallel Interface
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (8 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 09/43] drm/mediatek: mtk_dpi: Explicitly manage TVD clock in power on/off AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-03-02 14:14 ` Chun-Kuang Hu
2025-02-17 15:48 ` [PATCH v7 11/43] dt-bindings: display: mediatek: Add binding for HDMIv2 DDC AngeloGioacchino Del Regno
` (33 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
Add support for the DPI block found in the MT8195 and MT8188 SoCs.
Inside of the SoC, this block is directly connected to the HDMI IP.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 19 +++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 6 ++++++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
3 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index ee952785866c..d066fbd6ffb6 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -1139,6 +1139,24 @@ static const struct mtk_dpi_conf mt8192_conf = {
.csc_enable_bit = CSC_ENABLE,
};
+static const struct mtk_dpi_conf mt8195_conf = {
+ .max_clock_khz = 594000,
+ .output_fmts = mt8183_output_fmts,
+ .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
+ .pixels_per_iter = 1,
+ .is_ck_de_pol = true,
+ .swap_input_support = true,
+ .support_direct_pin = true,
+ .dimension_mask = HPW_MASK,
+ .hvsize_mask = HSIZE_MASK,
+ .channel_swap_shift = CH_SWAP,
+ .yuv422_en_bit = YUV422_EN,
+ .csc_enable_bit = CSC_ENABLE,
+ .input_2p_en_bit = DPI_INPUT_2P_EN,
+ .clocked_by_hdmi = true,
+ .output_1pixel = true,
+};
+
static const struct mtk_dpi_conf mt8195_dpintf_conf = {
.dpi_factor = dpi_factor_mt8195_dp_intf,
.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf),
@@ -1242,6 +1260,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
{ .compatible = "mediatek,mt8188-dp-intf", .data = &mt8195_dpintf_conf },
{ .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf },
{ .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf },
+ { .compatible = "mediatek,mt8195-dpi", .data = &mt8195_conf },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index a0b1d18bbbf7..3c24d9e9f241 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -40,6 +40,12 @@
#define FAKE_DE_LEVEN BIT(21)
#define FAKE_DE_RODD BIT(22)
#define FAKE_DE_REVEN BIT(23)
+
+/* DPI_CON: DPI instances */
+#define DPI_OUTPUT_1T1P_EN BIT(24)
+#define DPI_INPUT_2P_EN BIT(25)
+
+/* DPI_CON: DPINTF instances */
#define DPINTF_YUV422_EN BIT(24)
#define DPINTF_CSC_ENABLE BIT(26)
#define DPINTF_INPUT_2P_EN BIT(29)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index f22ad2882697..772c3d0f5d14 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -810,6 +810,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt8195-dp-intf",
.data = (void *)MTK_DP_INTF },
+ { .compatible = "mediatek,mt8195-dpi",
+ .data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt2701-dsi",
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8173-dsi",
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 10/43] drm/mediatek: Add support for MT8195 Digital Parallel Interface
2025-02-17 15:48 ` [PATCH v7 10/43] drm/mediatek: Add support for MT8195 Digital Parallel Interface AngeloGioacchino Del Regno
@ 2025-03-02 14:14 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-03-02 14:14 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:49寫道：
>
> Add support for the DPI block found in the MT8195 and MT8188 SoCs.
> Inside of the SoC, this block is directly connected to the HDMI IP.
After fix conflicts, applied to mediatek-drm-next [1], thanks.
[1] https://web.git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 19 +++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 6 ++++++
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
> 3 files changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index ee952785866c..d066fbd6ffb6 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -1139,6 +1139,24 @@ static const struct mtk_dpi_conf mt8192_conf = {
> .csc_enable_bit = CSC_ENABLE,
> };
>
> +static const struct mtk_dpi_conf mt8195_conf = {
> + .max_clock_khz = 594000,
> + .output_fmts = mt8183_output_fmts,
> + .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
> + .pixels_per_iter = 1,
> + .is_ck_de_pol = true,
> + .swap_input_support = true,
> + .support_direct_pin = true,
> + .dimension_mask = HPW_MASK,
> + .hvsize_mask = HSIZE_MASK,
> + .channel_swap_shift = CH_SWAP,
> + .yuv422_en_bit = YUV422_EN,
> + .csc_enable_bit = CSC_ENABLE,
> + .input_2p_en_bit = DPI_INPUT_2P_EN,
> + .clocked_by_hdmi = true,
> + .output_1pixel = true,
> +};
> +
> static const struct mtk_dpi_conf mt8195_dpintf_conf = {
> .dpi_factor = dpi_factor_mt8195_dp_intf,
> .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf),
> @@ -1242,6 +1260,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
> { .compatible = "mediatek,mt8188-dp-intf", .data = &mt8195_dpintf_conf },
> { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf },
> { .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf },
> + { .compatible = "mediatek,mt8195-dpi", .data = &mt8195_conf },
> { /* sentinel */ },
> };
> MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> index a0b1d18bbbf7..3c24d9e9f241 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> @@ -40,6 +40,12 @@
> #define FAKE_DE_LEVEN BIT(21)
> #define FAKE_DE_RODD BIT(22)
> #define FAKE_DE_REVEN BIT(23)
> +
> +/* DPI_CON: DPI instances */
> +#define DPI_OUTPUT_1T1P_EN BIT(24)
> +#define DPI_INPUT_2P_EN BIT(25)
> +
> +/* DPI_CON: DPINTF instances */
> #define DPINTF_YUV422_EN BIT(24)
> #define DPINTF_CSC_ENABLE BIT(26)
> #define DPINTF_INPUT_2P_EN BIT(29)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index f22ad2882697..772c3d0f5d14 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -810,6 +810,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt8195-dp-intf",
> .data = (void *)MTK_DP_INTF },
> + { .compatible = "mediatek,mt8195-dpi",
> + .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt2701-dsi",
> .data = (void *)MTK_DSI },
> { .compatible = "mediatek,mt8173-dsi",
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 11/43] dt-bindings: display: mediatek: Add binding for HDMIv2 DDC
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (9 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 10/43] drm/mediatek: Add support for MT8195 Digital Parallel Interface AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 12/43] dt-bindings: display: mediatek: Add binding for MT8195 HDMI-TX v2 AngeloGioacchino Del Regno
` (32 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
Add a binding for the Display Data Channel (DDC) IP in MediaTek
SoCs with version 2 HDMI TX IP.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../mediatek/mediatek,mt8195-hdmi-ddc.yaml | 41 +++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
new file mode 100644
index 000000000000..bde4dc556d4f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek HDMI MT8195 series HDMI Display Data Channel (DDC)
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ - CK Hu <ck.hu@mediatek.com>
+
+properties:
+ compatible:
+ oneOf:
+ - const: mediatek,mt8195-hdmi-ddc
+ - items:
+ - const: mediatek,mt8188-hdmi-ddc
+ - const: mediatek,mt8195-hdmi-ddc
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ hdmi {
+ hdmi_ddc: i2c {
+ compatible = "mediatek,mt8195-hdmi-ddc";
+ clocks = <&clk26m>;
+ };
+ };
+...
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 12/43] dt-bindings: display: mediatek: Add binding for MT8195 HDMI-TX v2
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (10 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 11/43] dt-bindings: display: mediatek: Add binding for HDMIv2 DDC AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-27 5:36 ` CK Hu (胡俊光)
2025-02-17 15:48 ` [PATCH v7 13/43] drm/mediatek: mtk_cec: Switch to register as module_platform_driver AngeloGioacchino Del Regno
` (31 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
Add a binding for the HDMI TX v2 Encoder found in MediaTek MT8195
and MT8188 SoCs.
This fully supports the HDMI Specification 2.0b, hence it provides
support for 3D-HDMI, Polarity inversion, up to 16 bits Deep Color,
color spaces including RGB444, YCBCR420/422/444 (ITU601/ITU709) and
xvYCC, with output resolutions up to 3840x2160p@60Hz.
Moreover, it also supports HDCP 1.4 and 2.3, Variable Refresh Rate
(VRR) and Consumer Electronics Control (CEC).
This IP also includes support for HDMI Audio, including IEC60958
and IEC61937 SPDIF, 8-channel PCM, DSD, and other lossless audio
according to HDMI 2.0.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../mediatek/mediatek,mt8195-hdmi.yaml | 151 ++++++++++++++++++
1 file changed, 151 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
new file mode 100644
index 000000000000..1b382f99d3ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
@@ -0,0 +1,151 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT8195 series HDMI-TX Encoder
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ - CK Hu <ck.hu@mediatek.com>
+
+description:
+ The MediaTek HDMI-TX v2 encoder can generate HDMI format data based on
+ the HDMI Specification 2.0b.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8188-hdmi-tx
+ - mediatek,mt8195-hdmi-tx
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: HDMI Peripheral Bus (APB) clock
+ - description: HDCP and HDMI_TOP clock
+ - description: HDCP, HDMI_TOP and HDMI Audio reference clock
+ - description: VPP HDMI Split clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: hdcp
+ - const: hdcp24m
+ - const: hdmi-split
+
+ i2c:
+ type: object
+ $ref: /schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
+ unevaluatedProperties: false
+ description: HDMI DDC I2C controller
+
+ phys:
+ maxItems: 1
+ description: PHY providing clocking TMDS and pixel to controller
+
+ phy-names:
+ items:
+ - const: hdmi
+
+ power-domains:
+ maxItems: 1
+
+ '#sound-dai-cells':
+ const: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Input port, usually connected to the output port of a DPI
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output port that must be connected either to the input port of
+ a HDMI connector node containing a ddc-i2c-bus, or to the input
+ port of an attached bridge chip, such as a SlimPort transmitter.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+ - phys
+ - phy-names
+ - ports
+
+allOf:
+ - $ref: /schemas/sound/dai-common.yaml#
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/mt8195-power.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ hdmi@1c300000 {
+ compatible = "mediatek,mt8195-hdmi-tx";
+ reg = <0 0x1c300000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_HDMI_APB>,
+ <&topckgen CLK_TOP_HDCP>,
+ <&topckgen CLK_TOP_HDCP_24M>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
+ clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split";
+ interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+ #sound-dai-cells = <1>;
+
+ hdmitx_ddc: i2c {
+ compatible = "mediatek,mt8195-hdmi-ddc";
+ clocks = <&clk26m>;
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_in: endpoint {
+ remote-endpoint = <&dpi1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+ };
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 12/43] dt-bindings: display: mediatek: Add binding for MT8195 HDMI-TX v2
2025-02-17 15:48 ` [PATCH v7 12/43] dt-bindings: display: mediatek: Add binding for MT8195 HDMI-TX v2 AngeloGioacchino Del Regno
@ 2025-02-27 5:36 ` CK Hu (胡俊光)
0 siblings, 0 replies; 74+ messages in thread
From: CK Hu (胡俊光) @ 2025-02-27 5:36 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, chunkuang.hu
Cc: robh, jie.qiu, tzimmermann, simona, mripard,
Jitao Shi (石记涛),
linux-mediatek, dri-devel, maarten.lankhorst, linux-kernel,
devicetree, kernel, dmitry.baryshkov, krzk+dt,
Lewis Liao (廖柏鈞),
p.zabel, conor+dt, TommyYL Chen (陳彥良),
Ives Chenjh (陳俊弘),
airlied, linux-arm-kernel, matthias.bgg,
Jason-JH Lin (林睿祥),
junzhi.zhao
On Mon, 2025-02-17 at 16:48 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
>
>
> Add a binding for the HDMI TX v2 Encoder found in MediaTek MT8195
> and MT8188 SoCs.
>
> This fully supports the HDMI Specification 2.0b, hence it provides
> support for 3D-HDMI, Polarity inversion, up to 16 bits Deep Color,
> color spaces including RGB444, YCBCR420/422/444 (ITU601/ITU709) and
> xvYCC, with output resolutions up to 3840x2160p@60Hz.
>
> Moreover, it also supports HDCP 1.4 and 2.3, Variable Refresh Rate
> (VRR) and Consumer Electronics Control (CEC).
>
> This IP also includes support for HDMI Audio, including IEC60958
> and IEC61937 SPDIF, 8-channel PCM, DSD, and other lossless audio
> according to HDMI 2.0.
>
> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../mediatek/mediatek,mt8195-hdmi.yaml | 151 ++++++++++++++++++
> 1 file changed, 151 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
> new file mode 100644
> index 000000000000..1b382f99d3ce
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
> @@ -0,0 +1,151 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml*__;Iw!!CTRNKA9wMg0ARbw!hjaw6rW0fGcNaeYWGbCHilyd6j6V1byRh1ZGipZfYhXOwPc0Y2RCI9yYLFNpqNFGiSagA0VWs3QqJuEBL-bSQVCiUYgz$
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!hjaw6rW0fGcNaeYWGbCHilyd6j6V1byRh1ZGipZfYhXOwPc0Y2RCI9yYLFNpqNFGiSagA0VWs3QqJuEBL-bSQX7ESZkS$
> +
> +title: MediaTek MT8195 series HDMI-TX Encoder
> +
> +maintainers:
> + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> + - CK Hu <ck.hu@mediatek.com>
> +
> +description:
> + The MediaTek HDMI-TX v2 encoder can generate HDMI format data based on
MediaTek MT8195 series HDMI-TX Encoder
After this modification,
Reviewed-by: CK Hu <ck.hu@mediatek.com>
> + the HDMI Specification 2.0b.
> +
> +properties:
> + compatible:
> + enum:
> + - mediatek,mt8188-hdmi-tx
> + - mediatek,mt8195-hdmi-tx
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: HDMI Peripheral Bus (APB) clock
> + - description: HDCP and HDMI_TOP clock
> + - description: HDCP, HDMI_TOP and HDMI Audio reference clock
> + - description: VPP HDMI Split clock
> +
> + clock-names:
> + items:
> + - const: bus
> + - const: hdcp
> + - const: hdcp24m
> + - const: hdmi-split
> +
> + i2c:
> + type: object
> + $ref: /schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
> + unevaluatedProperties: false
> + description: HDMI DDC I2C controller
> +
> + phys:
> + maxItems: 1
> + description: PHY providing clocking TMDS and pixel to controller
> +
> + phy-names:
> + items:
> + - const: hdmi
> +
> + power-domains:
> + maxItems: 1
> +
> + '#sound-dai-cells':
> + const: 1
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description:
> + Input port, usually connected to the output port of a DPI
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/properties/port
> + description:
> + Output port that must be connected either to the input port of
> + a HDMI connector node containing a ddc-i2c-bus, or to the input
> + port of an attached bridge chip, such as a SlimPort transmitter.
> +
> + required:
> + - port@0
> + - port@1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - power-domains
> + - phys
> + - phy-names
> + - ports
> +
> +allOf:
> + - $ref: /schemas/sound/dai-common.yaml#
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8195-clk.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/mt8195-power.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + hdmi@1c300000 {
> + compatible = "mediatek,mt8195-hdmi-tx";
> + reg = <0 0x1c300000 0 0x1000>;
> + clocks = <&topckgen CLK_TOP_HDMI_APB>,
> + <&topckgen CLK_TOP_HDCP>,
> + <&topckgen CLK_TOP_HDCP_24M>,
> + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
> + clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split";
> + interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>;
> + phys = <&hdmi_phy>;
> + phy-names = "hdmi";
> + power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hdmi_pins>;
> + #sound-dai-cells = <1>;
> +
> + hdmitx_ddc: i2c {
> + compatible = "mediatek,mt8195-hdmi-ddc";
> + clocks = <&clk26m>;
> + };
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + hdmi_in: endpoint {
> + remote-endpoint = <&dpi1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + hdmi_out: endpoint {
> + remote-endpoint = <&hdmi_connector_in>;
> + };
> + };
> + };
> + };
> + };
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 13/43] drm/mediatek: mtk_cec: Switch to register as module_platform_driver
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (11 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 12/43] dt-bindings: display: mediatek: Add binding for MT8195 HDMI-TX v2 AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 14/43] drm/mediatek: mtk_hdmi_ddc: " AngeloGioacchino Del Regno
` (30 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin, Alexandre Mergnat
In preparation for adding a driver for the new HDMIv2 IP, and
before splitting out the common bits from the HDMI driver, change
the mtk_cec driver from being registered from the mtk_hdmi driver
itself to be a module_platform_driver of its own.
Besides being a cleanup, this also allows build flexibility by
allowing to compile the CECv1 driver only when needed (for example,
this is not needed nor used in HDMIv2 configurations).
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/Makefile | 4 ++--
drivers/gpu/drm/mediatek/mtk_cec.c | 7 ++++++-
drivers/gpu/drm/mediatek/mtk_hdmi.c | 2 +-
drivers/gpu/drm/mediatek/mtk_hdmi.h | 1 -
4 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 32a2ed6c0cfe..bdd3a062f797 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -21,10 +21,10 @@ mediatek-drm-y := mtk_crtc.o \
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
-mediatek-drm-hdmi-objs := mtk_cec.o \
- mtk_hdmi.o \
+mediatek-drm-hdmi-objs := mtk_hdmi.o \
mtk_hdmi_ddc.o
+obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_cec.o
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
obj-$(CONFIG_DRM_MEDIATEK_DP) += mtk_dp.o
diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c
index b42c0d87eba3..c7be530ca041 100644
--- a/drivers/gpu/drm/mediatek/mtk_cec.c
+++ b/drivers/gpu/drm/mediatek/mtk_cec.c
@@ -12,7 +12,6 @@
#include <linux/platform_device.h>
#include "mtk_cec.h"
-#include "mtk_hdmi.h"
#include "mtk_drm_drv.h"
#define TR_CONFIG 0x00
@@ -102,6 +101,7 @@ void mtk_cec_set_hpd_event(struct device *dev,
cec->hpd_event = hpd_event;
spin_unlock_irqrestore(&cec->lock, flags);
}
+EXPORT_SYMBOL_NS_GPL(mtk_cec_set_hpd_event, "DRM_MTK_HDMI_V1");
bool mtk_cec_hpd_high(struct device *dev)
{
@@ -112,6 +112,7 @@ bool mtk_cec_hpd_high(struct device *dev)
return (status & (HDMI_PORD | HDMI_HTPLG)) == (HDMI_PORD | HDMI_HTPLG);
}
+EXPORT_SYMBOL_NS_GPL(mtk_cec_hpd_high, "DRM_MTK_HDMI_V1");
static void mtk_cec_htplg_irq_init(struct mtk_cec *cec)
{
@@ -247,3 +248,7 @@ struct platform_driver mtk_cec_driver = {
.of_match_table = mtk_cec_of_ids,
},
};
+module_platform_driver(mtk_cec_driver);
+
+MODULE_DESCRIPTION("MediaTek HDMI CEC Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index ca82bc829cb9..da725182f0db 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1805,7 +1805,6 @@ static struct platform_driver mtk_hdmi_driver = {
static struct platform_driver * const mtk_hdmi_drivers[] = {
&mtk_hdmi_ddc_driver,
- &mtk_cec_driver,
&mtk_hdmi_driver,
};
@@ -1827,3 +1826,4 @@ module_exit(mtk_hdmitx_exit);
MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
MODULE_DESCRIPTION("MediaTek HDMI Driver");
MODULE_LICENSE("GPL v2");
+MODULE_IMPORT_NS("DRM_MTK_HDMI_V1");
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
index 472bf141c92b..e40bc4651995 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
@@ -8,7 +8,6 @@
struct platform_driver;
-extern struct platform_driver mtk_cec_driver;
extern struct platform_driver mtk_hdmi_ddc_driver;
#endif /* _MTK_HDMI_CTRL_H */
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 14/43] drm/mediatek: mtk_hdmi_ddc: Switch to register as module_platform_driver
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (12 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 13/43] drm/mediatek: mtk_cec: Switch to register as module_platform_driver AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 15/43] drm/mediatek: mtk_hdmi: Convert to module_platform_driver macro AngeloGioacchino Del Regno
` (29 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin, Alexandre Mergnat
In preparation for adding a driver for the new HDMIv2 IP, and
before splitting out the common bits from the HDMI driver,
change the mtk_hdmi_ddc driver from being registered from the
HDMI driver itself to be a module_platform_driver of its own.
With this change, there are no more users of the mtk_hdmi.h header
so, while at it, also remove it.
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/Makefile | 6 ++----
drivers/gpu/drm/mediatek/mtk_hdmi.c | 2 --
drivers/gpu/drm/mediatek/mtk_hdmi.h | 13 -------------
drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c | 2 +-
4 files changed, 3 insertions(+), 20 deletions(-)
delete mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index bdd3a062f797..43afd0a26d14 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -21,10 +21,8 @@ mediatek-drm-y := mtk_crtc.o \
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
-mediatek-drm-hdmi-objs := mtk_hdmi.o \
- mtk_hdmi_ddc.o
-
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_cec.o
-obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
+obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_hdmi.o
+obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_hdmi_ddc.o
obj-$(CONFIG_DRM_MEDIATEK_DP) += mtk_dp.o
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index da725182f0db..e648fb5714e7 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -31,7 +31,6 @@
#include <drm/drm_probe_helper.h>
#include "mtk_cec.h"
-#include "mtk_hdmi.h"
#include "mtk_hdmi_regs.h"
#define NCTS_BYTES 7
@@ -1804,7 +1803,6 @@ static struct platform_driver mtk_hdmi_driver = {
};
static struct platform_driver * const mtk_hdmi_drivers[] = {
- &mtk_hdmi_ddc_driver,
&mtk_hdmi_driver,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
deleted file mode 100644
index e40bc4651995..000000000000
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2014 MediaTek Inc.
- * Author: Jie Qiu <jie.qiu@mediatek.com>
- */
-#ifndef _MTK_HDMI_CTRL_H
-#define _MTK_HDMI_CTRL_H
-
-struct platform_driver;
-
-extern struct platform_driver mtk_hdmi_ddc_driver;
-
-#endif /* _MTK_HDMI_CTRL_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
index 07db68067844..6358e1af69b4 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
@@ -20,7 +20,6 @@
#include <linux/of_platform.h>
#include "mtk_drm_drv.h"
-#include "mtk_hdmi.h"
#define SIF1_CLOK (288)
#define DDC_DDCMCTL0 (0x0)
@@ -337,6 +336,7 @@ struct platform_driver mtk_hdmi_ddc_driver = {
.of_match_table = mtk_hdmi_ddc_match,
},
};
+module_platform_driver(mtk_hdmi_ddc_driver);
MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
MODULE_DESCRIPTION("MediaTek HDMI DDC Driver");
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 15/43] drm/mediatek: mtk_hdmi: Convert to module_platform_driver macro
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (13 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 14/43] drm/mediatek: mtk_hdmi_ddc: " AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 16/43] drm/mediatek: mtk_hdmi: Compress of_device_id array entries AngeloGioacchino Del Regno
` (28 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin, Alexandre Mergnat
Now that all of the mtk_hdmi subdrivers are a platform driver on
their own it is possible to remove the custom init/exit functions
in this driver and just use the module_platform_driver() macro.
While at it, also compress struct of_device_id entries and remove
stray commas in mtk_hdmi_driver assignments.
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 20 +-------------------
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index e648fb5714e7..1e50b3918069 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1801,25 +1801,7 @@ static struct platform_driver mtk_hdmi_driver = {
.pm = &mtk_hdmi_pm_ops,
},
};
-
-static struct platform_driver * const mtk_hdmi_drivers[] = {
- &mtk_hdmi_driver,
-};
-
-static int __init mtk_hdmitx_init(void)
-{
- return platform_register_drivers(mtk_hdmi_drivers,
- ARRAY_SIZE(mtk_hdmi_drivers));
-}
-
-static void __exit mtk_hdmitx_exit(void)
-{
- platform_unregister_drivers(mtk_hdmi_drivers,
- ARRAY_SIZE(mtk_hdmi_drivers));
-}
-
-module_init(mtk_hdmitx_init);
-module_exit(mtk_hdmitx_exit);
+module_platform_driver(mtk_hdmi_driver);
MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
MODULE_DESCRIPTION("MediaTek HDMI Driver");
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 16/43] drm/mediatek: mtk_hdmi: Compress of_device_id array entries
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (14 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 15/43] drm/mediatek: mtk_hdmi: Convert to module_platform_driver macro AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-19 14:14 ` Chun-Kuang Hu
2025-02-17 15:48 ` [PATCH v7 17/43] drm/mediatek: mtk_hdmi: Unregister audio platform device on failure AngeloGioacchino Del Regno
` (27 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
Compress the entries found in the of_device_id array to improve
readability of this file and to make that consistent with other
kernel drivers.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 1e50b3918069..be71105ba81d 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1780,15 +1780,10 @@ static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
};
static const struct of_device_id mtk_hdmi_of_ids[] = {
- { .compatible = "mediatek,mt2701-hdmi",
- .data = &mtk_hdmi_conf_mt2701,
- },
- { .compatible = "mediatek,mt8167-hdmi",
- .data = &mtk_hdmi_conf_mt8167,
- },
- { .compatible = "mediatek,mt8173-hdmi",
- },
- {}
+ { .compatible = "mediatek,mt2701-hdmi", .data = &mtk_hdmi_conf_mt2701 },
+ { .compatible = "mediatek,mt8167-hdmi", .data = &mtk_hdmi_conf_mt8167 },
+ { .compatible = "mediatek,mt8173-hdmi" },
+ { /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_hdmi_of_ids);
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 16/43] drm/mediatek: mtk_hdmi: Compress of_device_id array entries
2025-02-17 15:48 ` [PATCH v7 16/43] drm/mediatek: mtk_hdmi: Compress of_device_id array entries AngeloGioacchino Del Regno
@ 2025-02-19 14:14 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-02-19 14:14 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:49寫道：
>
> Compress the entries found in the of_device_id array to improve
> readability of this file and to make that consistent with other
> kernel drivers.
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 13 ++++---------
> 1 file changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 1e50b3918069..be71105ba81d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1780,15 +1780,10 @@ static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
> };
>
> static const struct of_device_id mtk_hdmi_of_ids[] = {
> - { .compatible = "mediatek,mt2701-hdmi",
> - .data = &mtk_hdmi_conf_mt2701,
> - },
> - { .compatible = "mediatek,mt8167-hdmi",
> - .data = &mtk_hdmi_conf_mt8167,
> - },
> - { .compatible = "mediatek,mt8173-hdmi",
> - },
> - {}
> + { .compatible = "mediatek,mt2701-hdmi", .data = &mtk_hdmi_conf_mt2701 },
> + { .compatible = "mediatek,mt8167-hdmi", .data = &mtk_hdmi_conf_mt8167 },
> + { .compatible = "mediatek,mt8173-hdmi" },
> + { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, mtk_hdmi_of_ids);
>
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 17/43] drm/mediatek: mtk_hdmi: Unregister audio platform device on failure
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (15 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 16/43] drm/mediatek: mtk_hdmi: Compress of_device_id array entries AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-19 14:01 ` Chun-Kuang Hu
2025-02-17 15:48 ` [PATCH v7 18/43] drm/mediatek: hdmi: Use regmap instead of iomem for main registers AngeloGioacchino Del Regno
` (26 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
The probe function of this driver may fail after registering the
audio platform device: in that case, the state is not getting
cleaned up, leaving this device registered.
Adding up to the mix, should the probe function of this driver
return a probe deferral for N times, we're registering up to N
audio platform devices and, again, never freeing them up.
To fix this, add a pointer to the audio platform device in the
mtk_hdmi structure, and add a devm action to unregister it upon
driver removal or probe failure.
Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support")
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 25 +++++++++++++++++++------
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index be71105ba81d..b9f4f06edde6 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -172,6 +172,7 @@ struct mtk_hdmi {
unsigned int sys_offset;
void __iomem *regs;
enum hdmi_colorspace csp;
+ struct platform_device *audio_pdev;
struct hdmi_audio_param aud_param;
bool audio_enable;
bool powered;
@@ -1661,6 +1662,11 @@ static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
.hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb,
};
+static void mtk_hdmi_unregister_audio_driver(void *data)
+{
+ platform_device_unregister(data);
+}
+
static int mtk_hdmi_register_audio_driver(struct device *dev)
{
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
@@ -1671,13 +1677,20 @@ static int mtk_hdmi_register_audio_driver(struct device *dev)
.data = hdmi,
.no_capture_mute = 1,
};
- struct platform_device *pdev;
+ int ret;
- pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
- PLATFORM_DEVID_AUTO, &codec_data,
- sizeof(codec_data));
- if (IS_ERR(pdev))
- return PTR_ERR(pdev);
+ hdmi->audio_pdev = platform_device_register_data(dev,
+ HDMI_CODEC_DRV_NAME,
+ PLATFORM_DEVID_AUTO,
+ &codec_data,
+ sizeof(codec_data));
+ if (IS_ERR(hdmi->audio_pdev))
+ return PTR_ERR(hdmi->audio_pdev);
+
+ ret = devm_add_action_or_reset(dev, mtk_hdmi_unregister_audio_driver,
+ hdmi->audio_pdev);
+ if (ret)
+ return ret;
DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
return 0;
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 17/43] drm/mediatek: mtk_hdmi: Unregister audio platform device on failure
2025-02-17 15:48 ` [PATCH v7 17/43] drm/mediatek: mtk_hdmi: Unregister audio platform device on failure AngeloGioacchino Del Regno
@ 2025-02-19 14:01 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-02-19 14:01 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:49寫道：
>
> The probe function of this driver may fail after registering the
> audio platform device: in that case, the state is not getting
> cleaned up, leaving this device registered.
>
> Adding up to the mix, should the probe function of this driver
> return a probe deferral for N times, we're registering up to N
> audio platform devices and, again, never freeing them up.
>
> To fix this, add a pointer to the audio platform device in the
> mtk_hdmi structure, and add a devm action to unregister it upon
> driver removal or probe failure.
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support")
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 25 +++++++++++++++++++------
> 1 file changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index be71105ba81d..b9f4f06edde6 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -172,6 +172,7 @@ struct mtk_hdmi {
> unsigned int sys_offset;
> void __iomem *regs;
> enum hdmi_colorspace csp;
> + struct platform_device *audio_pdev;
> struct hdmi_audio_param aud_param;
> bool audio_enable;
> bool powered;
> @@ -1661,6 +1662,11 @@ static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
> .hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb,
> };
>
> +static void mtk_hdmi_unregister_audio_driver(void *data)
> +{
> + platform_device_unregister(data);
> +}
> +
> static int mtk_hdmi_register_audio_driver(struct device *dev)
> {
> struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> @@ -1671,13 +1677,20 @@ static int mtk_hdmi_register_audio_driver(struct device *dev)
> .data = hdmi,
> .no_capture_mute = 1,
> };
> - struct platform_device *pdev;
> + int ret;
>
> - pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
> - PLATFORM_DEVID_AUTO, &codec_data,
> - sizeof(codec_data));
> - if (IS_ERR(pdev))
> - return PTR_ERR(pdev);
> + hdmi->audio_pdev = platform_device_register_data(dev,
> + HDMI_CODEC_DRV_NAME,
> + PLATFORM_DEVID_AUTO,
> + &codec_data,
> + sizeof(codec_data));
> + if (IS_ERR(hdmi->audio_pdev))
> + return PTR_ERR(hdmi->audio_pdev);
> +
> + ret = devm_add_action_or_reset(dev, mtk_hdmi_unregister_audio_driver,
> + hdmi->audio_pdev);
> + if (ret)
> + return ret;
>
> DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
> return 0;
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 18/43] drm/mediatek: hdmi: Use regmap instead of iomem for main registers
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (16 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 17/43] drm/mediatek: mtk_hdmi: Unregister audio platform device on failure AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 19/43] drm/mediatek: mtk_hdmi: Fix typo for aud_sampe_size member AngeloGioacchino Del Regno
` (25 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin, Guillaume Ranquet
From: Guillaume Ranquet <granquet@baylibre.com>
In preparation for the addition of a new version of the HDMI IP
which will need to share its iospace between multiple subdrivers,
and in preparation for moving out the common bits between the two,
migrate this driver to fully use regmap.
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 173 +++++++++++-----------------
1 file changed, 65 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index b9f4f06edde6..29000cfcf761 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -170,7 +170,7 @@ struct mtk_hdmi {
u32 ibias_up;
struct regmap *sys_regmap;
unsigned int sys_offset;
- void __iomem *regs;
+ struct regmap *regs;
enum hdmi_colorspace csp;
struct platform_device *audio_pdev;
struct hdmi_audio_param aud_param;
@@ -187,50 +187,10 @@ static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
return container_of(b, struct mtk_hdmi, bridge);
}
-static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
-{
- return readl(hdmi->regs + offset);
-}
-
-static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
-{
- writel(val, hdmi->regs + offset);
-}
-
-static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
-{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp &= ~bits;
- writel(tmp, reg);
-}
-
-static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
-{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp |= bits;
- writel(tmp, reg);
-}
-
-static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
-{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp = (tmp & ~mask) | (val & mask);
- writel(tmp, reg);
-}
-
static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
{
- mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH,
- VIDEO_SOURCE_SEL);
+ regmap_update_bits(hdmi->regs, VIDEO_SOURCE_SEL,
+ VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH);
}
static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
@@ -265,12 +225,12 @@ static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
{
- mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
+ regmap_set_bits(hdmi->regs, GRL_AUDIO_CFG, AUDIO_ZERO);
}
static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
{
- mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
+ regmap_clear_bits(hdmi->regs, GRL_AUDIO_CFG, AUDIO_ZERO);
}
static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
@@ -279,25 +239,25 @@ static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
HDMI_RST, HDMI_RST);
regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
HDMI_RST, 0);
- mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
+ regmap_clear_bits(hdmi->regs, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
ANLG_ON, ANLG_ON);
}
static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
{
- mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0,
- CFG2_NOTICE_EN);
+ regmap_update_bits(hdmi->regs, GRL_CFG2, CFG2_NOTICE_EN,
+ enable_notice ? CFG2_NOTICE_EN : 0);
}
static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
{
- mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask);
+ regmap_write(hdmi->regs, GRL_INT_MASK, int_mask);
}
static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
{
- mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI);
+ regmap_update_bits(hdmi->regs, GRL_CFG1, CFG1_DVI, enable ? CFG1_DVI : 0);
}
static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
@@ -343,22 +303,22 @@ static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type);
return;
}
- mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
- mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type);
- mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver);
- mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len);
+ regmap_clear_bits(hdmi->regs, ctrl_reg, ctrl_frame_en);
+ regmap_write(hdmi->regs, GRL_INFOFRM_TYPE, frame_type);
+ regmap_write(hdmi->regs, GRL_INFOFRM_VER, frame_ver);
+ regmap_write(hdmi->regs, GRL_INFOFRM_LNG, frame_len);
- mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum);
+ regmap_write(hdmi->regs, GRL_IFM_PORT, checksum);
for (i = 0; i < frame_len; i++)
- mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]);
+ regmap_write(hdmi->regs, GRL_IFM_PORT, frame_data[i]);
- mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
+ regmap_set_bits(hdmi->regs, ctrl_reg, ctrl_frame_en);
}
static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
{
- mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF,
- AUDIO_PACKET_OFF);
+ regmap_update_bits(hdmi->regs, AUDIO_PACKET_OFF,
+ GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF);
}
static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
@@ -379,44 +339,44 @@ static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
{
- mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
+ regmap_clear_bits(hdmi->regs, GRL_CFG4, CTRL_AVMUTE);
usleep_range(2000, 4000);
- mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
+ regmap_set_bits(hdmi->regs, GRL_CFG4, CTRL_AVMUTE);
}
static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
{
- mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN,
- CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
+ regmap_update_bits(hdmi->regs, GRL_CFG4, CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET,
+ CFG4_AV_UNMUTE_EN);
usleep_range(2000, 4000);
- mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET,
- CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
+ regmap_update_bits(hdmi->regs, GRL_CFG4, CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET,
+ CFG4_AV_UNMUTE_SET);
}
static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
{
- mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT,
- CTS_CTRL_SOFT);
+ regmap_update_bits(hdmi->regs, GRL_CTS_CTRL, CTS_CTRL_SOFT,
+ on ? 0 : CTS_CTRL_SOFT);
}
static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
bool enable)
{
- mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0,
- NCTS_WRI_ANYTIME);
+ regmap_update_bits(hdmi->regs, GRL_CTS_CTRL, NCTS_WRI_ANYTIME,
+ enable ? NCTS_WRI_ANYTIME : 0);
}
static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
struct drm_display_mode *mode)
{
- mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE);
+ regmap_clear_bits(hdmi->regs, GRL_CFG4, CFG4_MHL_MODE);
if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
mode->clock == 74250 &&
mode->vdisplay == 1080)
- mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
+ regmap_clear_bits(hdmi->regs, GRL_CFG2, CFG2_MHL_DE_SEL);
else
- mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
+ regmap_set_bits(hdmi->regs, GRL_CFG2, CFG2_MHL_DE_SEL);
}
static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
@@ -444,7 +404,7 @@ static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
swap_bit = LFE_CC_SWAP;
break;
}
- mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff);
+ regmap_update_bits(hdmi->regs, GRL_CH_SWAP, 0xff, swap_bit);
}
static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
@@ -465,7 +425,7 @@ static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
break;
}
- mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK);
+ regmap_update_bits(hdmi->regs, GRL_AOUT_CFG, AOUT_BNUM_SEL_MASK, val);
}
static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
@@ -473,7 +433,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG0);
+ regmap_read(hdmi->regs, GRL_CFG0, &val);
val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
switch (i2s_fmt) {
@@ -497,7 +457,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
break;
}
- mtk_hdmi_write(hdmi, GRL_CFG0, val);
+ regmap_write(hdmi->regs, GRL_CFG0, val);
}
static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
@@ -506,14 +466,14 @@ static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
u8 val;
/* Disable high bitrate, set DST packet normal/double */
- mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
+ regmap_clear_bits(hdmi->regs, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
if (dst)
val = DST_NORMAL_DOUBLE | SACD_DST;
else
val = 0;
- mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask);
+ regmap_update_bits(hdmi->regs, GRL_AUDIO_CFG, mask, val);
}
static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
@@ -554,10 +514,10 @@ static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
i2s_uv = I2S_UV_CH_EN(0);
}
- mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff);
- mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
- mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
- mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv);
+ regmap_write(hdmi->regs, GRL_CH_SW0, ch_switch & 0xff);
+ regmap_write(hdmi->regs, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
+ regmap_write(hdmi->regs, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
+ regmap_write(hdmi->regs, GRL_I2S_UV, i2s_uv);
}
static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
@@ -565,7 +525,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG1);
+ regmap_read(hdmi->regs, GRL_CFG1, &val);
if (input_type == HDMI_AUD_INPUT_I2S &&
(val & CFG1_SPDIF) == CFG1_SPDIF) {
val &= ~CFG1_SPDIF;
@@ -573,7 +533,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
(val & CFG1_SPDIF) == 0) {
val |= CFG1_SPDIF;
}
- mtk_hdmi_write(hdmi, GRL_CFG1, val);
+ regmap_write(hdmi->regs, GRL_CFG1, val);
}
static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
@@ -582,13 +542,13 @@ static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
int i;
for (i = 0; i < 5; i++) {
- mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
- mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]);
- mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]);
+ regmap_write(hdmi->regs, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
+ regmap_write(hdmi->regs, GRL_L_STATUS_0 + i * 4, channel_status[i]);
+ regmap_write(hdmi->regs, GRL_R_STATUS_0 + i * 4, channel_status[i]);
}
for (; i < 24; i++) {
- mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0);
- mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0);
+ regmap_write(hdmi->regs, GRL_L_STATUS_0 + i * 4, 0);
+ regmap_write(hdmi->regs, GRL_R_STATUS_0 + i * 4, 0);
}
}
@@ -596,13 +556,13 @@ static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+ regmap_read(hdmi->regs, GRL_MIX_CTRL, &val);
if (val & MIX_CTRL_SRC_EN) {
val &= ~MIX_CTRL_SRC_EN;
- mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
+ regmap_write(hdmi->regs, GRL_MIX_CTRL, val);
usleep_range(255, 512);
val |= MIX_CTRL_SRC_EN;
- mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
+ regmap_write(hdmi->regs, GRL_MIX_CTRL, val);
}
}
@@ -610,10 +570,10 @@ static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+ regmap_read(hdmi->regs, GRL_MIX_CTRL, &val);
val &= ~MIX_CTRL_SRC_EN;
- mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
- mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
+ regmap_write(hdmi->regs, GRL_MIX_CTRL, val);
+ regmap_write(hdmi->regs, GRL_SHIFT_L1, 0x00);
}
static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
@@ -621,7 +581,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG5);
+ regmap_read(hdmi->regs, GRL_CFG5, &val);
val &= CFG5_CD_RATIO_MASK;
switch (mclk) {
@@ -644,7 +604,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
val |= CFG5_FS256;
break;
}
- mtk_hdmi_write(hdmi, GRL_CFG5, val);
+ regmap_write(hdmi->regs, GRL_CFG5, val);
}
struct hdmi_acr_n {
@@ -728,9 +688,9 @@ static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
unsigned char val[NCTS_BYTES];
int i;
- mtk_hdmi_write(hdmi, GRL_NCTS, 0);
- mtk_hdmi_write(hdmi, GRL_NCTS, 0);
- mtk_hdmi_write(hdmi, GRL_NCTS, 0);
+ regmap_write(hdmi->regs, GRL_NCTS, 0);
+ regmap_write(hdmi->regs, GRL_NCTS, 0);
+ regmap_write(hdmi->regs, GRL_NCTS, 0);
memset(val, 0, sizeof(val));
val[0] = (cts >> 24) & 0xff;
@@ -743,7 +703,7 @@ static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
val[6] = n & 0xff;
for (i = 0; i < NCTS_BYTES; i++)
- mtk_hdmi_write(hdmi, GRL_NCTS, val[i]);
+ regmap_write(hdmi->regs, GRL_NCTS, val[i]);
}
static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
@@ -758,8 +718,7 @@ static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
__func__, sample_rate, clock, n, cts);
- mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64,
- AUDIO_I2S_NCTS_SEL);
+ regmap_update_bits(hdmi->regs, DUMMY_304, AUDIO_I2S_NCTS_SEL, AUDIO_I2S_NCTS_SEL_64);
do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
}
@@ -879,7 +838,7 @@ static void mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
bool dst;
mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
- mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT);
+ regmap_set_bits(hdmi->regs, GRL_MIX_CTRL, MIX_CTRL_FLAT);
if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
@@ -911,7 +870,7 @@ static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
mtk_hdmi_hw_ncts_enable(hdmi, false);
mtk_hdmi_hw_aud_src_disable(hdmi);
- mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
+ regmap_clear_bits(hdmi->regs, GRL_CFG2, CFG2_ACLK_INV);
if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
switch (sample_rate) {
@@ -1425,7 +1384,6 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
struct device_node *cec_np, *remote, *i2c_np;
struct platform_device *cec_pdev;
struct regmap *regmap;
- struct resource *mem;
int ret;
ret = mtk_hdmi_get_all_clk(hdmi, np);
@@ -1471,8 +1429,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
}
hdmi->sys_regmap = regmap;
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- hdmi->regs = devm_ioremap_resource(dev, mem);
+ hdmi->regs = device_node_to_regmap(dev->of_node);
if (IS_ERR(hdmi->regs)) {
ret = PTR_ERR(hdmi->regs);
goto put_device;
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 19/43] drm/mediatek: mtk_hdmi: Fix typo for aud_sampe_size member
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (17 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 18/43] drm/mediatek: hdmi: Use regmap instead of iomem for main registers AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-19 14:06 ` Chun-Kuang Hu
2025-02-17 15:48 ` [PATCH v7 20/43] drm/mediatek: mtk_hdmi: Disgregate function mtk_hdmi_audio_set_param() AngeloGioacchino Del Regno
` (24 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
Rename member aud_sampe_size of struct hdmi_audio_param to
aud_sample_size to fix a typo and enhance readability.
This commit brings no functional changes.
Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support")
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 29000cfcf761..6257503ce639 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -136,7 +136,7 @@ enum hdmi_aud_channel_swap_type {
struct hdmi_audio_param {
enum hdmi_audio_coding_type aud_codec;
- enum hdmi_audio_sample_size aud_sampe_size;
+ enum hdmi_audio_sample_size aud_sample_size;
enum hdmi_aud_input_type aud_input_type;
enum hdmi_aud_i2s_fmt aud_i2s_fmt;
enum hdmi_aud_mclk aud_mclk;
@@ -1033,7 +1033,7 @@ static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
hdmi->csp = HDMI_COLORSPACE_RGB;
aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
- aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+ aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
@@ -1529,14 +1529,14 @@ static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
switch (daifmt->fmt) {
case HDMI_I2S:
hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
- hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+ hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
break;
case HDMI_SPDIF:
hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
- hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+ hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
break;
default:
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 19/43] drm/mediatek: mtk_hdmi: Fix typo for aud_sampe_size member
2025-02-17 15:48 ` [PATCH v7 19/43] drm/mediatek: mtk_hdmi: Fix typo for aud_sampe_size member AngeloGioacchino Del Regno
@ 2025-02-19 14:06 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-02-19 14:06 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:49寫道：
>
> Rename member aud_sampe_size of struct hdmi_audio_param to
> aud_sample_size to fix a typo and enhance readability.
>
> This commit brings no functional changes.
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support")
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 29000cfcf761..6257503ce639 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -136,7 +136,7 @@ enum hdmi_aud_channel_swap_type {
>
> struct hdmi_audio_param {
> enum hdmi_audio_coding_type aud_codec;
> - enum hdmi_audio_sample_size aud_sampe_size;
> + enum hdmi_audio_sample_size aud_sample_size;
> enum hdmi_aud_input_type aud_input_type;
> enum hdmi_aud_i2s_fmt aud_i2s_fmt;
> enum hdmi_aud_mclk aud_mclk;
> @@ -1033,7 +1033,7 @@ static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
>
> hdmi->csp = HDMI_COLORSPACE_RGB;
> aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> - aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> + aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
> aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
> aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
> @@ -1529,14 +1529,14 @@ static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
> switch (daifmt->fmt) {
> case HDMI_I2S:
> hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> - hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> + hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
> hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
> hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
> break;
> case HDMI_SPDIF:
> hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> - hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> + hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
> break;
> default:
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 20/43] drm/mediatek: mtk_hdmi: Disgregate function mtk_hdmi_audio_set_param()
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (18 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 19/43] drm/mediatek: mtk_hdmi: Fix typo for aud_sampe_size member AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 21/43] drm/mediatek: mtk_hdmi: Move audio params selection to new function AngeloGioacchino Del Regno
` (23 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
As a cleanup, and in preparation for splitting common bits of this
driver, disgregate the code in function mtk_hdmi_audio_set_param()
to the beginning and end of function mtk_hdmi_audio_hw_params().
In a later commit, the hw_params callback function will also be
disgregated so that the code will get two functions: one that
performs the generic hdmi_audio_param copy, and one that performs
IP specific setup, both of which will be called in the callback,
allowing all of the non IP version specific code to get moved in
a common file.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 26 +++++++++++---------------
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 6257503ce639..1f90cac112e2 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1054,20 +1054,6 @@ static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
hdmi->audio_enable = false;
}
-static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
- struct hdmi_audio_param *param)
-{
- if (!hdmi->audio_enable) {
- dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
- return -EINVAL;
- }
- dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
- param->aud_codec, param->aud_input_type,
- param->aud_input_chan_type, param->codec_params.sample_rate);
- memcpy(&hdmi->aud_param, param, sizeof(*param));
- return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
-}
-
static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
struct drm_display_mode *mode)
{
@@ -1487,6 +1473,11 @@ static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
struct hdmi_audio_param hdmi_params;
unsigned int chan = params->cea.channels;
+ if (!hdmi->audio_enable) {
+ dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
+ return -EINVAL;
+ }
+
dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
params->sample_rate, params->sample_width, chan);
@@ -1547,8 +1538,13 @@ static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
memcpy(&hdmi_params.codec_params, params,
sizeof(hdmi_params.codec_params));
+ memcpy(&hdmi->aud_param, &hdmi_params, sizeof(hdmi_params));
+
+ dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
+ hdmi_params.aud_codec, hdmi_params.aud_input_type,
+ hdmi_params.aud_input_chan_type, hdmi_params.codec_params.sample_rate);
- mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
+ mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
return 0;
}
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 21/43] drm/mediatek: mtk_hdmi: Move audio params selection to new function
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (19 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 20/43] drm/mediatek: mtk_hdmi: Disgregate function mtk_hdmi_audio_set_param() AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 22/43] drm/mediatek: mtk_hdmi: Move plugged_cb/codec_dev setting " AngeloGioacchino Del Regno
` (22 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
In preparation for splitting common bits of this driver, move the
audio params (codec, sample rate/size, input type, i2s format, etc)
selection to a new function called mtk_hdmi_audio_params().
While at it, also rename "hdmi_params" to "aud_params" both to match
the mtk_hdmi struct member name and to clarify that those parameters
are for HDMI Audio and not for HDMI Video configuration.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 63 ++++++++++++++++-------------
1 file changed, 35 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 1f90cac112e2..25ea3f3d982b 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1465,19 +1465,13 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
* HDMI audio codec callbacks
*/
-static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
- struct hdmi_codec_daifmt *daifmt,
- struct hdmi_codec_params *params)
+static int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi,
+ struct hdmi_codec_daifmt *daifmt,
+ struct hdmi_codec_params *params)
{
- struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
- struct hdmi_audio_param hdmi_params;
+ struct hdmi_audio_param aud_params = { 0 };
unsigned int chan = params->cea.channels;
- if (!hdmi->audio_enable) {
- dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
- return -EINVAL;
- }
-
dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
params->sample_rate, params->sample_width, chan);
@@ -1486,16 +1480,16 @@ static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
switch (chan) {
case 2:
- hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
+ aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
break;
case 4:
- hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
+ aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
break;
case 6:
- hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
+ aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
break;
case 8:
- hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
+ aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
break;
default:
dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
@@ -1519,31 +1513,44 @@ static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
switch (daifmt->fmt) {
case HDMI_I2S:
- hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
- hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
- hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
- hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
- hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
+ aud_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
+ aud_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+ aud_params.aud_input_type = HDMI_AUD_INPUT_I2S;
+ aud_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
+ aud_params.aud_mclk = HDMI_AUD_MCLK_128FS;
break;
case HDMI_SPDIF:
- hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
- hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
- hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
+ aud_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
+ aud_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+ aud_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
break;
default:
dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
daifmt->fmt);
return -EINVAL;
}
-
- memcpy(&hdmi_params.codec_params, params,
- sizeof(hdmi_params.codec_params));
- memcpy(&hdmi->aud_param, &hdmi_params, sizeof(hdmi_params));
+ memcpy(&aud_params.codec_params, params, sizeof(aud_params.codec_params));
+ memcpy(&hdmi->aud_param, &aud_params, sizeof(aud_params));
dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
- hdmi_params.aud_codec, hdmi_params.aud_input_type,
- hdmi_params.aud_input_chan_type, hdmi_params.codec_params.sample_rate);
+ aud_params.aud_codec, aud_params.aud_input_type,
+ aud_params.aud_input_chan_type, aud_params.codec_params.sample_rate);
+
+ return 0;
+}
+
+static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
+ struct hdmi_codec_daifmt *daifmt,
+ struct hdmi_codec_params *params)
+{
+ struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+
+ if (!hdmi->audio_enable) {
+ dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
+ return -EINVAL;
+ }
+ mtk_hdmi_audio_params(hdmi, daifmt, params);
mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
return 0;
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 22/43] drm/mediatek: mtk_hdmi: Move plugged_cb/codec_dev setting to new function
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (20 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 21/43] drm/mediatek: mtk_hdmi: Move audio params selection to new function AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 23/43] drm/mediatek: mtk_hdmi: Move N/CTS " AngeloGioacchino Del Regno
` (21 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
In preparation for splitting common bits of this driver, move the
mutex-protected cable plugged callback and codec device setting
to a new function called mtk_hdmi_audio_set_plugged_cb().
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 25ea3f3d982b..69db6b19017d 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1597,17 +1597,22 @@ static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf,
return 0;
}
-static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data,
- hdmi_codec_plugged_cb fn,
+static void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_codec_plugged_cb fn,
struct device *codec_dev)
{
- struct mtk_hdmi *hdmi = data;
-
mutex_lock(&hdmi->update_plugged_status_lock);
hdmi->plugged_cb = fn;
hdmi->codec_dev = codec_dev;
mutex_unlock(&hdmi->update_plugged_status_lock);
+}
+
+static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data,
+ hdmi_codec_plugged_cb fn,
+ struct device *codec_dev)
+{
+ struct mtk_hdmi *hdmi = data;
+ mtk_hdmi_audio_set_plugged_cb(hdmi, fn, codec_dev);
mtk_hdmi_update_plugged_status(hdmi);
return 0;
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 23/43] drm/mediatek: mtk_hdmi: Move N/CTS setting to new function
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (21 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 22/43] drm/mediatek: mtk_hdmi: Move plugged_cb/codec_dev setting " AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 24/43] drm/mediatek: mtk_hdmi: Move vendor/product strings to drm_bridge AngeloGioacchino Del Regno
` (20 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
In preparation for splitting common bits of this driver, moving
the hdmi_rec_n_table struct array, and the hdmi_recommended_n(),
hdmi_mode_clock_to_hz(), hdmi_expected_cts() functions, add one
function called mtk_hdmi_get_ncts() that sets both N and CTS in
a single call.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 69db6b19017d..e9f2f15e98fa 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -682,6 +682,13 @@ static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
128 * audio_sample_rate);
}
+static void mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock,
+ unsigned int *n, unsigned int *cts)
+{
+ *n = hdmi_recommended_n(sample_rate, clock);
+ *cts = hdmi_expected_cts(sample_rate, clock, *n);
+}
+
static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
unsigned int cts)
{
@@ -712,8 +719,7 @@ static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
{
unsigned int n, cts;
- n = hdmi_recommended_n(sample_rate, clock);
- cts = hdmi_expected_cts(sample_rate, clock, n);
+ mtk_hdmi_get_ncts(sample_rate, clock, &n, &cts);
dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
__func__, sample_rate, clock, n, cts);
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 24/43] drm/mediatek: mtk_hdmi: Move vendor/product strings to drm_bridge
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (22 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 23/43] drm/mediatek: mtk_hdmi: Move N/CTS " AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-19 14:23 ` Chun-Kuang Hu
2025-02-17 15:48 ` [PATCH v7 25/43] drm/mediatek: mtk_hdmi: Use dev_err_probe() in mtk_hdmi_dt_parse_pdata() AngeloGioacchino Del Regno
` (19 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
Move the vendor and product strings to the appropriate entries
of struct drm_bridge and use that in mtk_hdmi_setup_spd_infoframe
instead of having the same as function parameters.
While at it, also beautify the strings, setting them to read
"MediaTek On-Chip HDMI".
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index e9f2f15e98fa..4bf19574463d 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -952,15 +952,14 @@ static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
return 0;
}
-static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
- const char *vendor,
- const char *product)
+static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi)
{
+ struct drm_bridge *bridge = &hdmi->bridge;
struct hdmi_spd_infoframe frame;
u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE];
ssize_t err;
- err = hdmi_spd_infoframe_init(&frame, vendor, product);
+ err = hdmi_spd_infoframe_init(&frame, bridge->vendor, bridge->product);
if (err < 0) {
dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
err);
@@ -1328,7 +1327,7 @@ static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
{
mtk_hdmi_setup_audio_infoframe(hdmi);
mtk_hdmi_setup_avi_infoframe(hdmi, mode);
- mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
+ mtk_hdmi_setup_spd_infoframe(hdmi);
if (mode->flags & DRM_MODE_FLAG_3D_MASK)
mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
}
@@ -1707,6 +1706,8 @@ static int mtk_hdmi_probe(struct platform_device *pdev)
hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
| DRM_BRIDGE_OP_HPD;
hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
+ hdmi->bridge.vendor = "MediaTek";
+ hdmi->bridge.product = "On-Chip HDMI";
drm_bridge_add(&hdmi->bridge);
ret = mtk_hdmi_clk_enable_audio(hdmi);
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 24/43] drm/mediatek: mtk_hdmi: Move vendor/product strings to drm_bridge
2025-02-17 15:48 ` [PATCH v7 24/43] drm/mediatek: mtk_hdmi: Move vendor/product strings to drm_bridge AngeloGioacchino Del Regno
@ 2025-02-19 14:23 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-02-19 14:23 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:49寫道：
>
> Move the vendor and product strings to the appropriate entries
> of struct drm_bridge and use that in mtk_hdmi_setup_spd_infoframe
> instead of having the same as function parameters.
>
> While at it, also beautify the strings, setting them to read
> "MediaTek On-Chip HDMI".
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index e9f2f15e98fa..4bf19574463d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -952,15 +952,14 @@ static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
> return 0;
> }
>
> -static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
> - const char *vendor,
> - const char *product)
> +static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi)
> {
> + struct drm_bridge *bridge = &hdmi->bridge;
> struct hdmi_spd_infoframe frame;
> u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE];
> ssize_t err;
>
> - err = hdmi_spd_infoframe_init(&frame, vendor, product);
> + err = hdmi_spd_infoframe_init(&frame, bridge->vendor, bridge->product);
> if (err < 0) {
> dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
> err);
> @@ -1328,7 +1327,7 @@ static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
> {
> mtk_hdmi_setup_audio_infoframe(hdmi);
> mtk_hdmi_setup_avi_infoframe(hdmi, mode);
> - mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
> + mtk_hdmi_setup_spd_infoframe(hdmi);
> if (mode->flags & DRM_MODE_FLAG_3D_MASK)
> mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
> }
> @@ -1707,6 +1706,8 @@ static int mtk_hdmi_probe(struct platform_device *pdev)
> hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
> | DRM_BRIDGE_OP_HPD;
> hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
> + hdmi->bridge.vendor = "MediaTek";
> + hdmi->bridge.product = "On-Chip HDMI";
> drm_bridge_add(&hdmi->bridge);
>
> ret = mtk_hdmi_clk_enable_audio(hdmi);
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 25/43] drm/mediatek: mtk_hdmi: Use dev_err_probe() in mtk_hdmi_dt_parse_pdata()
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (23 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 24/43] drm/mediatek: mtk_hdmi: Move vendor/product strings to drm_bridge AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-27 5:42 ` CK Hu (胡俊光)
2025-02-17 15:48 ` [PATCH v7 26/43] drm/mediatek: mtk_hdmi: Move CEC device parsing in new function AngeloGioacchino Del Regno
` (18 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
Change error prints to use dev_err_probe() instead of dev_err()
where possible in function mtk_hdmi_dt_parse_pdata(), used only
during device probe.
While at it, also beautify some prints.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 31 ++++++++++-------------------
1 file changed, 10 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 4bf19574463d..61e521430b48 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1372,25 +1372,19 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
- struct device_node *cec_np, *remote, *i2c_np;
+ struct device_node *remote, *i2c_np;
struct platform_device *cec_pdev;
struct regmap *regmap;
int ret;
ret = mtk_hdmi_get_all_clk(hdmi, np);
- if (ret) {
- if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get clocks: %d\n", ret);
-
- return ret;
- }
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to get clocks\n");
/* The CEC module handles HDMI hotplug detection */
cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
- if (!cec_np) {
- dev_err(dev, "Failed to find CEC node\n");
- return -EINVAL;
- }
+ if (!cec_np)
+ return dev_err_probe(dev, -EINVAL, "Failed to find CEC node\n");
cec_pdev = of_find_device_by_node(cec_np);
if (!cec_pdev) {
@@ -1413,9 +1407,8 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
if (IS_ERR(regmap))
ret = PTR_ERR(regmap);
if (ret) {
- dev_err(dev,
- "Failed to get system configuration registers: %d\n",
- ret);
+ dev_err_probe(dev, ret,
+ "Failed to get system configuration registers\n");
goto put_device;
}
hdmi->sys_regmap = regmap;
@@ -1443,20 +1436,16 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
}
i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
+ of_node_put(remote);
if (!i2c_np) {
- dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n",
- remote);
- of_node_put(remote);
- ret = -EINVAL;
+ ret = dev_err_probe(dev, -EINVAL, "No ddc-i2c-bus in connector\n");
goto put_device;
}
- of_node_put(remote);
hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
of_node_put(i2c_np);
if (!hdmi->ddc_adpt) {
- dev_err(dev, "Failed to get ddc i2c adapter by node\n");
- ret = -EINVAL;
+ ret = dev_err_probe(dev, -EINVAL, "Failed to get ddc i2c adapter by node\n");
goto put_device;
}
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 25/43] drm/mediatek: mtk_hdmi: Use dev_err_probe() in mtk_hdmi_dt_parse_pdata()
2025-02-17 15:48 ` [PATCH v7 25/43] drm/mediatek: mtk_hdmi: Use dev_err_probe() in mtk_hdmi_dt_parse_pdata() AngeloGioacchino Del Regno
@ 2025-02-27 5:42 ` CK Hu (胡俊光)
0 siblings, 0 replies; 74+ messages in thread
From: CK Hu (胡俊光) @ 2025-02-27 5:42 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, chunkuang.hu
Cc: robh, jie.qiu, tzimmermann, simona, mripard,
Jitao Shi (石记涛),
linux-mediatek, dri-devel, maarten.lankhorst, linux-kernel,
devicetree, kernel, dmitry.baryshkov, krzk+dt,
Lewis Liao (廖柏鈞),
p.zabel, conor+dt, TommyYL Chen (陳彥良),
Ives Chenjh (陳俊弘),
airlied, linux-arm-kernel, matthias.bgg,
Jason-JH Lin (林睿祥),
junzhi.zhao
Hi, Angelo:
On Mon, 2025-02-17 at 16:48 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
>
>
> Change error prints to use dev_err_probe() instead of dev_err()
> where possible in function mtk_hdmi_dt_parse_pdata(), used only
> during device probe.
> While at it, also beautify some prints.
I would apply bug-fix, cleanup, and refinement patches first and then apply v2 related patches.
So bug-fix, cleanup, and refinement patches could be backported to old version branch without any v2 related patches.
When I apply this patch, conflicts happen.
Please rebase this series onto mediatek-drm-next, and apply this patch before v2 related patches.
Regards,
CK
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 31 ++++++++++-------------------
> 1 file changed, 10 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 4bf19574463d..61e521430b48 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1372,25 +1372,19 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
> {
> struct device *dev = &pdev->dev;
> struct device_node *np = dev->of_node;
> - struct device_node *cec_np, *remote, *i2c_np;
> + struct device_node *remote, *i2c_np;
> struct platform_device *cec_pdev;
> struct regmap *regmap;
> int ret;
>
> ret = mtk_hdmi_get_all_clk(hdmi, np);
> - if (ret) {
> - if (ret != -EPROBE_DEFER)
> - dev_err(dev, "Failed to get clocks: %d\n", ret);
> -
> - return ret;
> - }
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to get clocks\n");
>
> /* The CEC module handles HDMI hotplug detection */
> cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
> - if (!cec_np) {
> - dev_err(dev, "Failed to find CEC node\n");
> - return -EINVAL;
> - }
> + if (!cec_np)
> + return dev_err_probe(dev, -EINVAL, "Failed to find CEC node\n");
>
> cec_pdev = of_find_device_by_node(cec_np);
> if (!cec_pdev) {
> @@ -1413,9 +1407,8 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
> if (IS_ERR(regmap))
> ret = PTR_ERR(regmap);
> if (ret) {
> - dev_err(dev,
> - "Failed to get system configuration registers: %d\n",
> - ret);
> + dev_err_probe(dev, ret,
> + "Failed to get system configuration registers\n");
> goto put_device;
> }
> hdmi->sys_regmap = regmap;
> @@ -1443,20 +1436,16 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
> }
>
> i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
> + of_node_put(remote);
> if (!i2c_np) {
> - dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n",
> - remote);
> - of_node_put(remote);
> - ret = -EINVAL;
> + ret = dev_err_probe(dev, -EINVAL, "No ddc-i2c-bus in connector\n");
> goto put_device;
> }
> - of_node_put(remote);
>
> hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
> of_node_put(i2c_np);
> if (!hdmi->ddc_adpt) {
> - dev_err(dev, "Failed to get ddc i2c adapter by node\n");
> - ret = -EINVAL;
> + ret = dev_err_probe(dev, -EINVAL, "Failed to get ddc i2c adapter by node\n");
> goto put_device;
> }
>
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 26/43] drm/mediatek: mtk_hdmi: Move CEC device parsing in new function
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (24 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 25/43] drm/mediatek: mtk_hdmi: Use dev_err_probe() in mtk_hdmi_dt_parse_pdata() AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 27/43] drm/mediatek: mtk_hdmi: Remove unused members of struct mtk_hdmi AngeloGioacchino Del Regno
` (17 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
Move the CEC device parsing logic to a new function called
mtk_hdmi_get_cec_dev(), and move the parsing action to the end
of mtk_hdmi_dt_parse_pdata(), allowing to remove gotos in this
function, reducing code size and improving readability.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 82 ++++++++++++++---------------
1 file changed, 39 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 61e521430b48..eb3b1009c305 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1367,20 +1367,12 @@ static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
.edid_read = mtk_hdmi_bridge_edid_read,
};
-static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
- struct platform_device *pdev)
+static int mtk_hdmi_get_cec_dev(struct mtk_hdmi *hdmi, struct device *dev, struct device_node *np)
{
- struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
- struct device_node *remote, *i2c_np;
struct platform_device *cec_pdev;
- struct regmap *regmap;
+ struct device_node *cec_np;
int ret;
- ret = mtk_hdmi_get_all_clk(hdmi, np);
- if (ret)
- return dev_err_probe(dev, ret, "Failed to get clocks\n");
-
/* The CEC module handles HDMI hotplug detection */
cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
if (!cec_np)
@@ -1394,65 +1386,69 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
return -EPROBE_DEFER;
}
of_node_put(cec_np);
- hdmi->cec_dev = &cec_pdev->dev;
/*
* The mediatek,syscon-hdmi property contains a phandle link to the
* MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
* registers it contains.
*/
- regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
- ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
- &hdmi->sys_offset);
- if (IS_ERR(regmap))
- ret = PTR_ERR(regmap);
- if (ret) {
- dev_err_probe(dev, ret,
- "Failed to get system configuration registers\n");
- goto put_device;
- }
- hdmi->sys_regmap = regmap;
+ hdmi->sys_regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
+ if (IS_ERR(hdmi->sys_regmap))
+ return PTR_ERR(hdmi->sys_regmap);
+
+ ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1, &hdmi->sys_offset);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to get system configuration registers\n");
+
+ hdmi->cec_dev = &cec_pdev->dev;
+ return 0;
+}
+
+static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
+ struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *remote, *i2c_np;
+ int ret;
+
+ ret = mtk_hdmi_get_all_clk(hdmi, np);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to get clocks\n");
hdmi->regs = device_node_to_regmap(dev->of_node);
- if (IS_ERR(hdmi->regs)) {
- ret = PTR_ERR(hdmi->regs);
- goto put_device;
- }
+ if (IS_ERR(hdmi->regs))
+ return PTR_ERR(hdmi->regs);
remote = of_graph_get_remote_node(np, 1, 0);
- if (!remote) {
- ret = -EINVAL;
- goto put_device;
- }
+ if (!remote)
+ return -EINVAL;
if (!of_device_is_compatible(remote, "hdmi-connector")) {
hdmi->next_bridge = of_drm_find_bridge(remote);
if (!hdmi->next_bridge) {
dev_err(dev, "Waiting for external bridge\n");
of_node_put(remote);
- ret = -EPROBE_DEFER;
- goto put_device;
+ return -EPROBE_DEFER;
}
}
i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
of_node_put(remote);
- if (!i2c_np) {
- ret = dev_err_probe(dev, -EINVAL, "No ddc-i2c-bus in connector\n");
- goto put_device;
- }
+ if (!i2c_np)
+ return dev_err_probe(dev, -EINVAL, "No ddc-i2c-bus in connector\n");
hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
of_node_put(i2c_np);
- if (!hdmi->ddc_adpt) {
- ret = dev_err_probe(dev, -EINVAL, "Failed to get ddc i2c adapter by node\n");
- goto put_device;
- }
+ if (!hdmi->ddc_adpt)
+ return dev_err_probe(dev, -EINVAL, "Failed to get ddc i2c adapter by node\n");
+
+ ret = mtk_hdmi_get_cec_dev(hdmi, dev, np);
+ if (ret)
+ return ret;
return 0;
-put_device:
- put_device(hdmi->cec_dev);
- return ret;
}
/*
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 27/43] drm/mediatek: mtk_hdmi: Remove unused members of struct mtk_hdmi
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (25 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 26/43] drm/mediatek: mtk_hdmi: Move CEC device parsing in new function AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-20 14:02 ` Chun-Kuang Hu
2025-02-17 15:48 ` [PATCH v7 28/43] drm/mediatek: mtk_hdmi: Move output init to mtk_hdmi_register_audio_driver() AngeloGioacchino Del Regno
` (16 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
The hdmi_colorspace csp member of struct mtk_hdmi is initialized
once but then it's never used at all.
Remove said member and the only assignment to it as a cleanup.
Also remove the ibias, ibias_up, min_clock, max_clock, min_hdisplay
and max_vdisplay members, as those were really completely unused.
This commit brings no functional changes.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index eb3b1009c305..6e4900f99b51 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -162,16 +162,9 @@ struct mtk_hdmi {
struct clk *clk[MTK_HDMI_CLK_COUNT];
struct drm_display_mode mode;
bool dvi_mode;
- u32 min_clock;
- u32 max_clock;
- u32 max_hdisplay;
- u32 max_vdisplay;
- u32 ibias;
- u32 ibias_up;
struct regmap *sys_regmap;
unsigned int sys_offset;
struct regmap *regs;
- enum hdmi_colorspace csp;
struct platform_device *audio_pdev;
struct hdmi_audio_param aud_param;
bool audio_enable;
@@ -1036,7 +1029,6 @@ static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
{
struct hdmi_audio_param *aud_param = &hdmi->aud_param;
- hdmi->csp = HDMI_COLORSPACE_RGB;
aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 27/43] drm/mediatek: mtk_hdmi: Remove unused members of struct mtk_hdmi
2025-02-17 15:48 ` [PATCH v7 27/43] drm/mediatek: mtk_hdmi: Remove unused members of struct mtk_hdmi AngeloGioacchino Del Regno
@ 2025-02-20 14:02 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-02-20 14:02 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:50寫道：
>
> The hdmi_colorspace csp member of struct mtk_hdmi is initialized
> once but then it's never used at all.
> Remove said member and the only assignment to it as a cleanup.
>
> Also remove the ibias, ibias_up, min_clock, max_clock, min_hdisplay
> and max_vdisplay members, as those were really completely unused.
>
> This commit brings no functional changes.
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 8 --------
> 1 file changed, 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index eb3b1009c305..6e4900f99b51 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -162,16 +162,9 @@ struct mtk_hdmi {
> struct clk *clk[MTK_HDMI_CLK_COUNT];
> struct drm_display_mode mode;
> bool dvi_mode;
> - u32 min_clock;
> - u32 max_clock;
> - u32 max_hdisplay;
> - u32 max_vdisplay;
> - u32 ibias;
> - u32 ibias_up;
> struct regmap *sys_regmap;
> unsigned int sys_offset;
> struct regmap *regs;
> - enum hdmi_colorspace csp;
> struct platform_device *audio_pdev;
> struct hdmi_audio_param aud_param;
> bool audio_enable;
> @@ -1036,7 +1029,6 @@ static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
> {
> struct hdmi_audio_param *aud_param = &hdmi->aud_param;
>
> - hdmi->csp = HDMI_COLORSPACE_RGB;
> aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 28/43] drm/mediatek: mtk_hdmi: Move output init to mtk_hdmi_register_audio_driver()
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (26 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 27/43] drm/mediatek: mtk_hdmi: Remove unused members of struct mtk_hdmi AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 29/43] drm/mediatek: mtk_hdmi: Use devm managed version of drm_bridge_add AngeloGioacchino Del Regno
` (15 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
In preparation for moving the common bits of this driver, merge the
contents of mtk_hdmi_output_init in mtk_hdmi_register_audio_driver
function to aggregate all of the initial audio setup together in
the same function and to make it clear that all of the setup that
is performed in mtk_hdmi_output_init is specifically related only
to audio and not video.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 27 ++++++++-------------------
1 file changed, 8 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 6e4900f99b51..e79ebed21eab 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1025,20 +1025,6 @@ static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
return 0;
}
-static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
-{
- struct hdmi_audio_param *aud_param = &hdmi->aud_param;
-
- aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
- aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
- aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
- aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
- aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
- aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
-
- return 0;
-}
-
static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
{
mtk_hdmi_hw_send_aud_packet(hdmi, true);
@@ -1617,6 +1603,7 @@ static void mtk_hdmi_unregister_audio_driver(void *data)
static int mtk_hdmi_register_audio_driver(struct device *dev)
{
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+ struct hdmi_audio_param *aud_param = &hdmi->aud_param;
struct hdmi_codec_pdata codec_data = {
.ops = &mtk_hdmi_audio_codec_ops,
.max_i2s_channels = 2,
@@ -1626,6 +1613,13 @@ static int mtk_hdmi_register_audio_driver(struct device *dev)
};
int ret;
+ aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
+ aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+ aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
+ aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
+ aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
+ aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
+
hdmi->audio_pdev = platform_device_register_data(dev,
HDMI_CODEC_DRV_NAME,
PLATFORM_DEVID_AUTO,
@@ -1668,11 +1662,6 @@ static int mtk_hdmi_probe(struct platform_device *pdev)
mutex_init(&hdmi->update_plugged_status_lock);
platform_set_drvdata(pdev, hdmi);
- ret = mtk_hdmi_output_init(hdmi);
- if (ret)
- return dev_err_probe(dev, ret,
- "Failed to initialize hdmi output\n");
-
ret = mtk_hdmi_register_audio_driver(dev);
if (ret)
return dev_err_probe(dev, ret,
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 29/43] drm/mediatek: mtk_hdmi: Use devm managed version of drm_bridge_add
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (27 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 28/43] drm/mediatek: mtk_hdmi: Move output init to mtk_hdmi_register_audio_driver() AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-20 14:10 ` Chun-Kuang Hu
2025-02-17 15:48 ` [PATCH v7 30/43] drm/mediatek: mtk_hdmi: Remove ifdef for CONFIG_PM_SLEEP AngeloGioacchino Del Regno
` (14 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
Simplify the probe/remove functions by using devm_drm_bridge_add()
as now there is no more need to manually remove the bridge.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index e79ebed21eab..f539472307e2 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1674,14 +1674,15 @@ static int mtk_hdmi_probe(struct platform_device *pdev)
hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
hdmi->bridge.vendor = "MediaTek";
hdmi->bridge.product = "On-Chip HDMI";
- drm_bridge_add(&hdmi->bridge);
+
+ ret = devm_drm_bridge_add(dev, &hdmi->bridge);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to add bridge\n");
ret = mtk_hdmi_clk_enable_audio(hdmi);
- if (ret) {
- drm_bridge_remove(&hdmi->bridge);
+ if (ret)
return dev_err_probe(dev, ret,
"Failed to enable audio clocks\n");
- }
return 0;
}
@@ -1690,7 +1691,6 @@ static void mtk_hdmi_remove(struct platform_device *pdev)
{
struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
- drm_bridge_remove(&hdmi->bridge);
mtk_hdmi_clk_disable_audio(hdmi);
}
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 29/43] drm/mediatek: mtk_hdmi: Use devm managed version of drm_bridge_add
2025-02-17 15:48 ` [PATCH v7 29/43] drm/mediatek: mtk_hdmi: Use devm managed version of drm_bridge_add AngeloGioacchino Del Regno
@ 2025-02-20 14:10 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-02-20 14:10 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:50寫道：
>
> Simplify the probe/remove functions by using devm_drm_bridge_add()
> as now there is no more need to manually remove the bridge.
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index e79ebed21eab..f539472307e2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1674,14 +1674,15 @@ static int mtk_hdmi_probe(struct platform_device *pdev)
> hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
> hdmi->bridge.vendor = "MediaTek";
> hdmi->bridge.product = "On-Chip HDMI";
> - drm_bridge_add(&hdmi->bridge);
> +
> + ret = devm_drm_bridge_add(dev, &hdmi->bridge);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to add bridge\n");
>
> ret = mtk_hdmi_clk_enable_audio(hdmi);
> - if (ret) {
> - drm_bridge_remove(&hdmi->bridge);
> + if (ret)
> return dev_err_probe(dev, ret,
> "Failed to enable audio clocks\n");
> - }
>
> return 0;
> }
> @@ -1690,7 +1691,6 @@ static void mtk_hdmi_remove(struct platform_device *pdev)
> {
> struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
>
> - drm_bridge_remove(&hdmi->bridge);
> mtk_hdmi_clk_disable_audio(hdmi);
> }
>
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 30/43] drm/mediatek: mtk_hdmi: Remove ifdef for CONFIG_PM_SLEEP
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (28 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 29/43] drm/mediatek: mtk_hdmi: Use devm managed version of drm_bridge_add AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-20 14:17 ` Chun-Kuang Hu
2025-02-17 15:48 ` [PATCH v7 31/43] drm/mediatek: mtk_hdmi: Remove goto in mtk_hdmi_clk_enable_audio() AngeloGioacchino Del Regno
` (13 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
Since the SIMPLE_DEV_PM_OPS macro and the pm pointer are anyway
defined when CONFIG_PM_SLEEP is not set, remove the ifdef for it
and indicate that the mtk_hdmi_{remove,suspend} functions may be
unused (as they are, in case PM support is not built-in).
While at it, to improve readability, also compress the
SIMPLE_DEV_PM_OPS declaration as it even fits in less
than 80 columns.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index f539472307e2..bf8cf7fc8c07 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1694,8 +1694,7 @@ static void mtk_hdmi_remove(struct platform_device *pdev)
mtk_hdmi_clk_disable_audio(hdmi);
}
-#ifdef CONFIG_PM_SLEEP
-static int mtk_hdmi_suspend(struct device *dev)
+static __maybe_unused int mtk_hdmi_suspend(struct device *dev)
{
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
@@ -1704,7 +1703,7 @@ static int mtk_hdmi_suspend(struct device *dev)
return 0;
}
-static int mtk_hdmi_resume(struct device *dev)
+static __maybe_unused int mtk_hdmi_resume(struct device *dev)
{
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
int ret = 0;
@@ -1717,9 +1716,8 @@ static int mtk_hdmi_resume(struct device *dev)
return 0;
}
-#endif
-static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
- mtk_hdmi_suspend, mtk_hdmi_resume);
+
+static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resume);
static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
.tz_disabled = true,
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 30/43] drm/mediatek: mtk_hdmi: Remove ifdef for CONFIG_PM_SLEEP
2025-02-17 15:48 ` [PATCH v7 30/43] drm/mediatek: mtk_hdmi: Remove ifdef for CONFIG_PM_SLEEP AngeloGioacchino Del Regno
@ 2025-02-20 14:17 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-02-20 14:17 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:50寫道：
>
> Since the SIMPLE_DEV_PM_OPS macro and the pm pointer are anyway
> defined when CONFIG_PM_SLEEP is not set, remove the ifdef for it
> and indicate that the mtk_hdmi_{remove,suspend} functions may be
> unused (as they are, in case PM support is not built-in).
>
> While at it, to improve readability, also compress the
> SIMPLE_DEV_PM_OPS declaration as it even fits in less
> than 80 columns.
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index f539472307e2..bf8cf7fc8c07 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1694,8 +1694,7 @@ static void mtk_hdmi_remove(struct platform_device *pdev)
> mtk_hdmi_clk_disable_audio(hdmi);
> }
>
> -#ifdef CONFIG_PM_SLEEP
> -static int mtk_hdmi_suspend(struct device *dev)
> +static __maybe_unused int mtk_hdmi_suspend(struct device *dev)
> {
> struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
>
> @@ -1704,7 +1703,7 @@ static int mtk_hdmi_suspend(struct device *dev)
> return 0;
> }
>
> -static int mtk_hdmi_resume(struct device *dev)
> +static __maybe_unused int mtk_hdmi_resume(struct device *dev)
> {
> struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> int ret = 0;
> @@ -1717,9 +1716,8 @@ static int mtk_hdmi_resume(struct device *dev)
>
> return 0;
> }
> -#endif
> -static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
> - mtk_hdmi_suspend, mtk_hdmi_resume);
> +
> +static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resume);
>
> static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
> .tz_disabled = true,
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 31/43] drm/mediatek: mtk_hdmi: Remove goto in mtk_hdmi_clk_enable_audio()
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (29 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 30/43] drm/mediatek: mtk_hdmi: Remove ifdef for CONFIG_PM_SLEEP AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-20 14:22 ` Chun-Kuang Hu
2025-02-17 15:48 ` [PATCH v7 32/43] drm/mediatek: mtk_hdmi: Remove driver bound to HDMI print AngeloGioacchino Del Regno
` (12 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
If the clk_prepare_enable() call for the SPDIF clock fails, just
disable and unprepare the clock in the error check branch and
return immediately instead of jumping to the end with a goto,
slightly reducing code size.
This commit brings no functional changes.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index bf8cf7fc8c07..2e98a8ed6cbe 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1095,13 +1095,12 @@ static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
return ret;
ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
- if (ret)
- goto err;
+ if (ret) {
+ clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
+ return ret;
+ }
return 0;
-err:
- clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
- return ret;
}
static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 31/43] drm/mediatek: mtk_hdmi: Remove goto in mtk_hdmi_clk_enable_audio()
2025-02-17 15:48 ` [PATCH v7 31/43] drm/mediatek: mtk_hdmi: Remove goto in mtk_hdmi_clk_enable_audio() AngeloGioacchino Del Regno
@ 2025-02-20 14:22 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-02-20 14:22 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:50寫道：
>
> If the clk_prepare_enable() call for the SPDIF clock fails, just
> disable and unprepare the clock in the error check branch and
> return immediately instead of jumping to the end with a goto,
> slightly reducing code size.
>
> This commit brings no functional changes.
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index bf8cf7fc8c07..2e98a8ed6cbe 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1095,13 +1095,12 @@ static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
> return ret;
>
> ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
> - if (ret)
> - goto err;
> + if (ret) {
> + clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
> + return ret;
> + }
>
> return 0;
> -err:
> - clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
> - return ret;
> }
>
> static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 32/43] drm/mediatek: mtk_hdmi: Remove driver bound to HDMI print
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (30 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 31/43] drm/mediatek: mtk_hdmi: Remove goto in mtk_hdmi_clk_enable_audio() AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-20 14:26 ` Chun-Kuang Hu
2025-02-17 15:48 ` [PATCH v7 33/43] drm/mediatek: mtk_hdmi: Cleanup function mtk_hdmi_resume() AngeloGioacchino Del Regno
` (11 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
Remove the "driver bound to HDMI" print to avoid useless spam in
the kernel log, as registered and bound drivers can be debugged
through debugfs.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 2e98a8ed6cbe..50f9ab48cbf9 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1632,7 +1632,6 @@ static int mtk_hdmi_register_audio_driver(struct device *dev)
if (ret)
return ret;
- DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
return 0;
}
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 32/43] drm/mediatek: mtk_hdmi: Remove driver bound to HDMI print
2025-02-17 15:48 ` [PATCH v7 32/43] drm/mediatek: mtk_hdmi: Remove driver bound to HDMI print AngeloGioacchino Del Regno
@ 2025-02-20 14:26 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-02-20 14:26 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:50寫道：
>
> Remove the "driver bound to HDMI" print to avoid useless spam in
> the kernel log, as registered and bound drivers can be debugged
> through debugfs.
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 2e98a8ed6cbe..50f9ab48cbf9 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1632,7 +1632,6 @@ static int mtk_hdmi_register_audio_driver(struct device *dev)
> if (ret)
> return ret;
>
> - DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
> return 0;
> }
>
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 33/43] drm/mediatek: mtk_hdmi: Cleanup function mtk_hdmi_resume()
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (31 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 32/43] drm/mediatek: mtk_hdmi: Remove driver bound to HDMI print AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-20 14:32 ` Chun-Kuang Hu
2025-02-17 15:48 ` [PATCH v7 34/43] drm/mediatek: mtk_hdmi: Improve mtk_hdmi_get_all_clk() flexibility AngeloGioacchino Del Regno
` (10 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
Remove the error print in case of mtk_hdmi_clk_enable_audio()
failures: since the APIs will already print on their own, having
one in there is redundant.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 9 +--------
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 50f9ab48cbf9..2614561e2634 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1704,15 +1704,8 @@ static __maybe_unused int mtk_hdmi_suspend(struct device *dev)
static __maybe_unused int mtk_hdmi_resume(struct device *dev)
{
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
- int ret = 0;
- ret = mtk_hdmi_clk_enable_audio(hdmi);
- if (ret) {
- dev_err(dev, "hdmi resume failed!\n");
- return ret;
- }
-
- return 0;
+ return mtk_hdmi_clk_enable_audio(hdmi);
}
static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resume);
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 33/43] drm/mediatek: mtk_hdmi: Cleanup function mtk_hdmi_resume()
2025-02-17 15:48 ` [PATCH v7 33/43] drm/mediatek: mtk_hdmi: Cleanup function mtk_hdmi_resume() AngeloGioacchino Del Regno
@ 2025-02-20 14:32 ` Chun-Kuang Hu
0 siblings, 0 replies; 74+ messages in thread
From: Chun-Kuang Hu @ 2025-02-20 14:32 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, p.zabel, airlied, simona, maarten.lankhorst,
mripard, tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
ck.hu, jitao.shi, jie.qiu, junzhi.zhao, dri-devel,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
kernel, dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Hi, Angelo:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於
2025年2月17日 週一 下午11:50寫道：
>
> Remove the error print in case of mtk_hdmi_clk_enable_audio()
> failures: since the APIs will already print on their own, having
> one in there is redundant.
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 9 +--------
> 1 file changed, 1 insertion(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 50f9ab48cbf9..2614561e2634 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1704,15 +1704,8 @@ static __maybe_unused int mtk_hdmi_suspend(struct device *dev)
> static __maybe_unused int mtk_hdmi_resume(struct device *dev)
> {
> struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> - int ret = 0;
>
> - ret = mtk_hdmi_clk_enable_audio(hdmi);
> - if (ret) {
> - dev_err(dev, "hdmi resume failed!\n");
> - return ret;
> - }
> -
> - return 0;
> + return mtk_hdmi_clk_enable_audio(hdmi);
> }
>
> static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resume);
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 34/43] drm/mediatek: mtk_hdmi: Improve mtk_hdmi_get_all_clk() flexibility
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (32 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 33/43] drm/mediatek: mtk_hdmi: Cleanup function mtk_hdmi_resume() AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 35/43] drm/mediatek: mtk_hdmi: Add HDMI IP version configuration to pdata AngeloGioacchino Del Regno
` (9 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
In preparation for splitting common bits of this driver and for
introducing a new version of the MediaTek HDMI Encoder IP, improve
the flexibility of function mtk_hdmi_get_all_clk() by adding a
pointer to the clock names array and size of it to its parameters.
Also change the array of struct clock pointers in the mtk_hdmi
structure to be dynamically allocated, and allocate it in probe.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 26 ++++++++++++++++----------
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 2614561e2634..66a08eedef44 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -159,7 +159,7 @@ struct mtk_hdmi {
struct phy *phy;
struct device *cec_dev;
struct i2c_adapter *ddc_adpt;
- struct clk *clk[MTK_HDMI_CLK_COUNT];
+ struct clk **clk;
struct drm_display_mode mode;
bool dvi_mode;
struct regmap *sys_regmap;
@@ -1072,17 +1072,18 @@ static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
[MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
};
-static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
- struct device_node *np)
+static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, struct device_node *np,
+ const char * const *clock_names, size_t num_clocks)
{
int i;
- for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
- hdmi->clk[i] = of_clk_get_by_name(np,
- mtk_hdmi_clk_names[i]);
+ for (i = 0; i < num_clocks; i++) {
+ hdmi->clk[i] = of_clk_get_by_name(np, clock_names[i]);
+
if (IS_ERR(hdmi->clk[i]))
return PTR_ERR(hdmi->clk[i]);
}
+
return 0;
}
@@ -1382,15 +1383,15 @@ static int mtk_hdmi_get_cec_dev(struct mtk_hdmi *hdmi, struct device *dev, struc
return 0;
}
-static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
- struct platform_device *pdev)
+static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct platform_device *pdev,
+ const char * const *clk_names, size_t num_clocks)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct device_node *remote, *i2c_np;
int ret;
- ret = mtk_hdmi_get_all_clk(hdmi, np);
+ ret = mtk_hdmi_get_all_clk(hdmi, np, clk_names, num_clocks);
if (ret)
return dev_err_probe(dev, ret, "Failed to get clocks\n");
@@ -1639,6 +1640,7 @@ static int mtk_hdmi_probe(struct platform_device *pdev)
{
struct mtk_hdmi *hdmi;
struct device *dev = &pdev->dev;
+ const int num_clocks = MTK_HDMI_CLK_COUNT;
int ret;
hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
@@ -1648,7 +1650,11 @@ static int mtk_hdmi_probe(struct platform_device *pdev)
hdmi->dev = dev;
hdmi->conf = of_device_get_match_data(dev);
- ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
+ hdmi->clk = devm_kcalloc(dev, num_clocks, sizeof(*hdmi->clk), GFP_KERNEL);
+ if (!hdmi->clk)
+ return -ENOMEM;
+
+ ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev, mtk_hdmi_clk_names, num_clocks);
if (ret)
return ret;
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 35/43] drm/mediatek: mtk_hdmi: Add HDMI IP version configuration to pdata
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (33 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 34/43] drm/mediatek: mtk_hdmi: Improve mtk_hdmi_get_all_clk() flexibility AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 36/43] drm/mediatek: mtk_hdmi: Split driver and add common probe function AngeloGioacchino Del Regno
` (8 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
In preparation for adding a driver for the HDMIv2 IP and before
moving the common bits out of this driver, add a new structure
`mtk_hdmi_ver_conf`, holding pointers to HDMI IP version specific
drm_bridge_funcs, hdmi_codec_ops and clock array used for probe,
and nest it into the mtk_hdmi_conf platform data structure.
While at it, also convert all of the direct users of
mtk_hdmi_bridge_funcs, mtk_hdmi_audio_codec_ops, mtk_hdmi_clk_names
to use pointers from the ver_conf platform data.
In order to do so, it was also necessary to fill a new version 1
specific const `mtk_hdmi_v1_ver_conf` and assign it to all of the
currently supported compatibles for this driver.
This commit brings no functional change.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 36 ++++++++++++++++++++++++-----
1 file changed, 30 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 66a08eedef44..aaed901ef053 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -144,7 +144,15 @@ struct hdmi_audio_param {
struct hdmi_codec_params codec_params;
};
+struct mtk_hdmi_ver_conf {
+ const struct drm_bridge_funcs *bridge_funcs;
+ const struct hdmi_codec_ops *codec_ops;
+ const char * const *mtk_hdmi_clock_names;
+ int num_clocks;
+};
+
struct mtk_hdmi_conf {
+ const struct mtk_hdmi_ver_conf *ver_conf;
bool tz_disabled;
bool cea_modes_only;
unsigned long max_mode_clock;
@@ -1605,7 +1613,7 @@ static int mtk_hdmi_register_audio_driver(struct device *dev)
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
struct hdmi_audio_param *aud_param = &hdmi->aud_param;
struct hdmi_codec_pdata codec_data = {
- .ops = &mtk_hdmi_audio_codec_ops,
+ .ops = hdmi->conf->ver_conf->codec_ops,
.max_i2s_channels = 2,
.i2s = 1,
.data = hdmi,
@@ -1638,6 +1646,7 @@ static int mtk_hdmi_register_audio_driver(struct device *dev)
static int mtk_hdmi_probe(struct platform_device *pdev)
{
+ const struct mtk_hdmi_ver_conf *ver_conf;
struct mtk_hdmi *hdmi;
struct device *dev = &pdev->dev;
const int num_clocks = MTK_HDMI_CLK_COUNT;
@@ -1649,12 +1658,14 @@ static int mtk_hdmi_probe(struct platform_device *pdev)
hdmi->dev = dev;
hdmi->conf = of_device_get_match_data(dev);
+ ver_conf = hdmi->conf->ver_conf;
- hdmi->clk = devm_kcalloc(dev, num_clocks, sizeof(*hdmi->clk), GFP_KERNEL);
+ hdmi->clk = devm_kcalloc(dev, ver_conf->num_clocks, sizeof(*hdmi->clk), GFP_KERNEL);
if (!hdmi->clk)
return -ENOMEM;
- ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev, mtk_hdmi_clk_names, num_clocks);
+ ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev, ver_conf->mtk_hdmi_clock_names,
+ ver_conf->num_clocks);
if (ret)
return ret;
@@ -1671,7 +1682,7 @@ static int mtk_hdmi_probe(struct platform_device *pdev)
return dev_err_probe(dev, ret,
"Failed to register audio driver\n");
- hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
+ hdmi->bridge.funcs = ver_conf->bridge_funcs;
hdmi->bridge.of_node = pdev->dev.of_node;
hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
| DRM_BRIDGE_OP_HPD;
@@ -1716,19 +1727,32 @@ static __maybe_unused int mtk_hdmi_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resume);
+static const struct mtk_hdmi_ver_conf mtk_hdmi_v1_ver_conf = {
+ .bridge_funcs = &mtk_hdmi_bridge_funcs,
+ .codec_ops = &mtk_hdmi_audio_codec_ops,
+ .mtk_hdmi_clock_names = mtk_hdmi_clk_names,
+ .num_clocks = ARRAY_SIZE(mtk_hdmi_clk_names)
+};
+
static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
.tz_disabled = true,
+ .ver_conf = &mtk_hdmi_v1_ver_conf
};
static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
- .max_mode_clock = 148500,
.cea_modes_only = true,
+ .max_mode_clock = 148500,
+ .ver_conf = &mtk_hdmi_v1_ver_conf
+};
+
+static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8173 = {
+ .ver_conf = &mtk_hdmi_v1_ver_conf
};
static const struct of_device_id mtk_hdmi_of_ids[] = {
{ .compatible = "mediatek,mt2701-hdmi", .data = &mtk_hdmi_conf_mt2701 },
{ .compatible = "mediatek,mt8167-hdmi", .data = &mtk_hdmi_conf_mt8167 },
- { .compatible = "mediatek,mt8173-hdmi" },
+ { .compatible = "mediatek,mt8173-hdmi", .data = &mtk_hdmi_conf_mt8173 },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_hdmi_of_ids);
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 36/43] drm/mediatek: mtk_hdmi: Split driver and add common probe function
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (34 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 35/43] drm/mediatek: mtk_hdmi: Add HDMI IP version configuration to pdata AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-27 5:56 ` CK Hu (胡俊光)
2025-02-17 15:48 ` [PATCH v7 37/43] drm/mediatek: mtk_hdmi_common: Make CEC support optional AngeloGioacchino Del Regno
` (7 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
In preparation for adding a new driver for the HDMI TX v2 IP,
split out the functions that will be common between the already
present mtk_hdmi (v1) driver and the new one.
Since the probe flow for both drivers is 90% similar, add a common
probe function that will be called from each driver's .probe()
callback, avoiding lots of code duplication.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/Kconfig | 11 +-
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_hdmi.c | 542 +--------------------
drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 426 ++++++++++++++++
drivers/gpu/drm/mediatek/mtk_hdmi_common.h | 188 +++++++
5 files changed, 633 insertions(+), 535 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.h
diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
index e47debd60619..994b48b82d44 100644
--- a/drivers/gpu/drm/mediatek/Kconfig
+++ b/drivers/gpu/drm/mediatek/Kconfig
@@ -30,9 +30,18 @@ config DRM_MEDIATEK_DP
help
DRM/KMS Display Port driver for MediaTek SoCs.
+config DRM_MEDIATEK_HDMI_COMMON
+ tristate
+ depends on DRM_MEDIATEK
+ select DRM_DISPLAY_HDMI_HELPER
+ select DRM_DISPLAY_HELPER
+ select SND_SOC_HDMI_CODEC if SND_SOC
+ help
+ MediaTek SoC HDMI common library
+
config DRM_MEDIATEK_HDMI
tristate "DRM HDMI Support for Mediatek SoCs"
depends on DRM_MEDIATEK
- select SND_SOC_HDMI_CODEC if SND_SOC
+ select DRM_MEDIATEK_HDMI_COMMON
help
DRM/KMS HDMI driver for Mediatek SoCs
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 43afd0a26d14..78cf2d4fc85f 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -21,6 +21,7 @@ mediatek-drm-y := mtk_crtc.o \
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
+obj-$(CONFIG_DRM_MEDIATEK_HDMI_COMMON) += mtk_hdmi_common.o
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_cec.o
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_hdmi.o
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_hdmi_ddc.o
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index aaed901ef053..8c2e8dd56aa3 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -31,6 +31,7 @@
#include <drm/drm_probe_helper.h>
#include "mtk_cec.h"
+#include "mtk_hdmi_common.h"
#include "mtk_hdmi_regs.h"
#define NCTS_BYTES 7
@@ -43,151 +44,6 @@ enum mtk_hdmi_clk_id {
MTK_HDMI_CLK_COUNT
};
-enum hdmi_aud_input_type {
- HDMI_AUD_INPUT_I2S = 0,
- HDMI_AUD_INPUT_SPDIF,
-};
-
-enum hdmi_aud_i2s_fmt {
- HDMI_I2S_MODE_RJT_24BIT = 0,
- HDMI_I2S_MODE_RJT_16BIT,
- HDMI_I2S_MODE_LJT_24BIT,
- HDMI_I2S_MODE_LJT_16BIT,
- HDMI_I2S_MODE_I2S_24BIT,
- HDMI_I2S_MODE_I2S_16BIT
-};
-
-enum hdmi_aud_mclk {
- HDMI_AUD_MCLK_128FS,
- HDMI_AUD_MCLK_192FS,
- HDMI_AUD_MCLK_256FS,
- HDMI_AUD_MCLK_384FS,
- HDMI_AUD_MCLK_512FS,
- HDMI_AUD_MCLK_768FS,
- HDMI_AUD_MCLK_1152FS,
-};
-
-enum hdmi_aud_channel_type {
- HDMI_AUD_CHAN_TYPE_1_0 = 0,
- HDMI_AUD_CHAN_TYPE_1_1,
- HDMI_AUD_CHAN_TYPE_2_0,
- HDMI_AUD_CHAN_TYPE_2_1,
- HDMI_AUD_CHAN_TYPE_3_0,
- HDMI_AUD_CHAN_TYPE_3_1,
- HDMI_AUD_CHAN_TYPE_4_0,
- HDMI_AUD_CHAN_TYPE_4_1,
- HDMI_AUD_CHAN_TYPE_5_0,
- HDMI_AUD_CHAN_TYPE_5_1,
- HDMI_AUD_CHAN_TYPE_6_0,
- HDMI_AUD_CHAN_TYPE_6_1,
- HDMI_AUD_CHAN_TYPE_7_0,
- HDMI_AUD_CHAN_TYPE_7_1,
- HDMI_AUD_CHAN_TYPE_3_0_LRS,
- HDMI_AUD_CHAN_TYPE_3_1_LRS,
- HDMI_AUD_CHAN_TYPE_4_0_CLRS,
- HDMI_AUD_CHAN_TYPE_4_1_CLRS,
- HDMI_AUD_CHAN_TYPE_6_1_CS,
- HDMI_AUD_CHAN_TYPE_6_1_CH,
- HDMI_AUD_CHAN_TYPE_6_1_OH,
- HDMI_AUD_CHAN_TYPE_6_1_CHR,
- HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
- HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
- HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
- HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
- HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
- HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
- HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
- HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
- HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
- HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
- HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
- HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
- HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
- HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
- HDMI_AUD_CHAN_TYPE_6_0_CS,
- HDMI_AUD_CHAN_TYPE_6_0_CH,
- HDMI_AUD_CHAN_TYPE_6_0_OH,
- HDMI_AUD_CHAN_TYPE_6_0_CHR,
- HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
- HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
- HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
- HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
- HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
- HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
- HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
- HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
- HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
- HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
- HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
- HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
- HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
- HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
- HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
- HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
-};
-
-enum hdmi_aud_channel_swap_type {
- HDMI_AUD_SWAP_LR,
- HDMI_AUD_SWAP_LFE_CC,
- HDMI_AUD_SWAP_LSRS,
- HDMI_AUD_SWAP_RLS_RRS,
- HDMI_AUD_SWAP_LR_STATUS,
-};
-
-struct hdmi_audio_param {
- enum hdmi_audio_coding_type aud_codec;
- enum hdmi_audio_sample_size aud_sample_size;
- enum hdmi_aud_input_type aud_input_type;
- enum hdmi_aud_i2s_fmt aud_i2s_fmt;
- enum hdmi_aud_mclk aud_mclk;
- enum hdmi_aud_channel_type aud_input_chan_type;
- struct hdmi_codec_params codec_params;
-};
-
-struct mtk_hdmi_ver_conf {
- const struct drm_bridge_funcs *bridge_funcs;
- const struct hdmi_codec_ops *codec_ops;
- const char * const *mtk_hdmi_clock_names;
- int num_clocks;
-};
-
-struct mtk_hdmi_conf {
- const struct mtk_hdmi_ver_conf *ver_conf;
- bool tz_disabled;
- bool cea_modes_only;
- unsigned long max_mode_clock;
-};
-
-struct mtk_hdmi {
- struct drm_bridge bridge;
- struct drm_bridge *next_bridge;
- struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
- struct device *dev;
- const struct mtk_hdmi_conf *conf;
- struct phy *phy;
- struct device *cec_dev;
- struct i2c_adapter *ddc_adpt;
- struct clk **clk;
- struct drm_display_mode mode;
- bool dvi_mode;
- struct regmap *sys_regmap;
- unsigned int sys_offset;
- struct regmap *regs;
- struct platform_device *audio_pdev;
- struct hdmi_audio_param aud_param;
- bool audio_enable;
- bool powered;
- bool enabled;
- hdmi_codec_plugged_cb plugged_cb;
- struct device *codec_dev;
- struct mutex update_plugged_status_lock;
-};
-
-static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
-{
- return container_of(b, struct mtk_hdmi, bridge);
-}
-
static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
{
regmap_update_bits(hdmi->regs, VIDEO_SOURCE_SEL,
@@ -608,88 +464,6 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
regmap_write(hdmi->regs, GRL_CFG5, val);
}
-struct hdmi_acr_n {
- unsigned int clock;
- unsigned int n[3];
-};
-
-/* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
-static const struct hdmi_acr_n hdmi_rec_n_table[] = {
- /* Clock, N: 32kHz 44.1kHz 48kHz */
- { 25175, { 4576, 7007, 6864 } },
- { 74176, { 11648, 17836, 11648 } },
- { 148352, { 11648, 8918, 5824 } },
- { 296703, { 5824, 4459, 5824 } },
- { 297000, { 3072, 4704, 5120 } },
- { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */
-};
-
-/**
- * hdmi_recommended_n() - Return N value recommended by HDMI specification
- * @freq: audio sample rate in Hz
- * @clock: rounded TMDS clock in kHz
- */
-static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
-{
- const struct hdmi_acr_n *recommended;
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
- if (clock == hdmi_rec_n_table[i].clock)
- break;
- }
- recommended = hdmi_rec_n_table + i;
-
- switch (freq) {
- case 32000:
- return recommended->n[0];
- case 44100:
- return recommended->n[1];
- case 48000:
- return recommended->n[2];
- case 88200:
- return recommended->n[1] * 2;
- case 96000:
- return recommended->n[2] * 2;
- case 176400:
- return recommended->n[1] * 4;
- case 192000:
- return recommended->n[2] * 4;
- default:
- return (128 * freq) / 1000;
- }
-}
-
-static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
-{
- switch (clock) {
- case 25175:
- return 25174825; /* 25.2/1.001 MHz */
- case 74176:
- return 74175824; /* 74.25/1.001 MHz */
- case 148352:
- return 148351648; /* 148.5/1.001 MHz */
- case 296703:
- return 296703297; /* 297/1.001 MHz */
- default:
- return clock * 1000;
- }
-}
-
-static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
- unsigned int tmds_clock, unsigned int n)
-{
- return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
- 128 * audio_sample_rate);
-}
-
-static void mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock,
- unsigned int *n, unsigned int *cts)
-{
- *n = hdmi_recommended_n(sample_rate, clock);
- *cts = hdmi_expected_cts(sample_rate, clock, *n);
-}
-
static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
unsigned int cts)
{
@@ -1080,21 +854,6 @@ static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
[MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
};
-static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, struct device_node *np,
- const char * const *clock_names, size_t num_clocks)
-{
- int i;
-
- for (i = 0; i < num_clocks; i++) {
- hdmi->clk[i] = of_clk_get_by_name(np, clock_names[i]);
-
- if (IS_ERR(hdmi->clk[i]))
- return PTR_ERR(hdmi->clk[i]);
- }
-
- return 0;
-}
-
static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
{
int ret;
@@ -1237,13 +996,6 @@ static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge,
return 0;
}
-static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- return true;
-}
-
static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
@@ -1275,28 +1027,6 @@ static void mtk_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge,
hdmi->powered = false;
}
-static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
- const struct drm_display_mode *mode,
- const struct drm_display_mode *adjusted_mode)
-{
- struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
-
- dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
- adjusted_mode->name, adjusted_mode->hdisplay);
- dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
- adjusted_mode->hsync_start, adjusted_mode->hsync_end,
- adjusted_mode->htotal);
- dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
- adjusted_mode->hskew, adjusted_mode->vdisplay);
- dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
- adjusted_mode->vsync_start, adjusted_mode->vsync_end,
- adjusted_mode->vtotal);
- dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
- adjusted_mode->vscan, adjusted_mode->flags);
-
- drm_mode_copy(&hdmi->mode, adjusted_mode);
-}
-
static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
struct drm_bridge_state *old_state)
{
@@ -1353,168 +1083,10 @@ static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
.edid_read = mtk_hdmi_bridge_edid_read,
};
-static int mtk_hdmi_get_cec_dev(struct mtk_hdmi *hdmi, struct device *dev, struct device_node *np)
-{
- struct platform_device *cec_pdev;
- struct device_node *cec_np;
- int ret;
-
- /* The CEC module handles HDMI hotplug detection */
- cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
- if (!cec_np)
- return dev_err_probe(dev, -EINVAL, "Failed to find CEC node\n");
-
- cec_pdev = of_find_device_by_node(cec_np);
- if (!cec_pdev) {
- dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
- cec_np);
- of_node_put(cec_np);
- return -EPROBE_DEFER;
- }
- of_node_put(cec_np);
-
- /*
- * The mediatek,syscon-hdmi property contains a phandle link to the
- * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
- * registers it contains.
- */
- hdmi->sys_regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
- if (IS_ERR(hdmi->sys_regmap))
- return PTR_ERR(hdmi->sys_regmap);
-
- ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1, &hdmi->sys_offset);
- if (ret)
- return dev_err_probe(dev, ret,
- "Failed to get system configuration registers\n");
-
- hdmi->cec_dev = &cec_pdev->dev;
- return 0;
-}
-
-static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct platform_device *pdev,
- const char * const *clk_names, size_t num_clocks)
-{
- struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
- struct device_node *remote, *i2c_np;
- int ret;
-
- ret = mtk_hdmi_get_all_clk(hdmi, np, clk_names, num_clocks);
- if (ret)
- return dev_err_probe(dev, ret, "Failed to get clocks\n");
-
- hdmi->regs = device_node_to_regmap(dev->of_node);
- if (IS_ERR(hdmi->regs))
- return PTR_ERR(hdmi->regs);
-
- remote = of_graph_get_remote_node(np, 1, 0);
- if (!remote)
- return -EINVAL;
-
- if (!of_device_is_compatible(remote, "hdmi-connector")) {
- hdmi->next_bridge = of_drm_find_bridge(remote);
- if (!hdmi->next_bridge) {
- dev_err(dev, "Waiting for external bridge\n");
- of_node_put(remote);
- return -EPROBE_DEFER;
- }
- }
-
- i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
- of_node_put(remote);
- if (!i2c_np)
- return dev_err_probe(dev, -EINVAL, "No ddc-i2c-bus in connector\n");
-
- hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
- of_node_put(i2c_np);
- if (!hdmi->ddc_adpt)
- return dev_err_probe(dev, -EINVAL, "Failed to get ddc i2c adapter by node\n");
-
- ret = mtk_hdmi_get_cec_dev(hdmi, dev, np);
- if (ret)
- return ret;
-
- return 0;
-}
-
/*
* HDMI audio codec callbacks
*/
-static int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi,
- struct hdmi_codec_daifmt *daifmt,
- struct hdmi_codec_params *params)
-{
- struct hdmi_audio_param aud_params = { 0 };
- unsigned int chan = params->cea.channels;
-
- dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
- params->sample_rate, params->sample_width, chan);
-
- if (!hdmi->bridge.encoder)
- return -ENODEV;
-
- switch (chan) {
- case 2:
- aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
- break;
- case 4:
- aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
- break;
- case 6:
- aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
- break;
- case 8:
- aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
- break;
- default:
- dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
- return -EINVAL;
- }
-
- switch (params->sample_rate) {
- case 32000:
- case 44100:
- case 48000:
- case 88200:
- case 96000:
- case 176400:
- case 192000:
- break;
- default:
- dev_err(hdmi->dev, "rate[%d] not supported!\n",
- params->sample_rate);
- return -EINVAL;
- }
-
- switch (daifmt->fmt) {
- case HDMI_I2S:
- aud_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
- aud_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
- aud_params.aud_input_type = HDMI_AUD_INPUT_I2S;
- aud_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
- aud_params.aud_mclk = HDMI_AUD_MCLK_128FS;
- break;
- case HDMI_SPDIF:
- aud_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
- aud_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
- aud_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
- break;
- default:
- dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
- daifmt->fmt);
- return -EINVAL;
- }
- memcpy(&aud_params.codec_params, params, sizeof(aud_params.codec_params));
- memcpy(&hdmi->aud_param, &aud_params, sizeof(aud_params));
-
- dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
- aud_params.aud_codec, aud_params.aud_input_type,
- aud_params.aud_input_chan_type, aud_params.codec_params.sample_rate);
-
- return 0;
-}
-
static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
struct hdmi_codec_daifmt *daifmt,
struct hdmi_codec_params *params)
@@ -1562,26 +1134,6 @@ mtk_hdmi_audio_mute(struct device *dev, void *data,
return 0;
}
-static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
-{
- struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
-
- if (hdmi->enabled)
- memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len));
- else
- memset(buf, 0, len);
- return 0;
-}
-
-static void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_codec_plugged_cb fn,
- struct device *codec_dev)
-{
- mutex_lock(&hdmi->update_plugged_status_lock);
- hdmi->plugged_cb = fn;
- hdmi->codec_dev = codec_dev;
- mutex_unlock(&hdmi->update_plugged_status_lock);
-}
-
static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data,
hdmi_codec_plugged_cb fn,
struct device *codec_dev)
@@ -1603,100 +1155,21 @@ static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
.hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb,
};
-static void mtk_hdmi_unregister_audio_driver(void *data)
-{
- platform_device_unregister(data);
-}
-
-static int mtk_hdmi_register_audio_driver(struct device *dev)
-{
- struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
- struct hdmi_audio_param *aud_param = &hdmi->aud_param;
- struct hdmi_codec_pdata codec_data = {
- .ops = hdmi->conf->ver_conf->codec_ops,
- .max_i2s_channels = 2,
- .i2s = 1,
- .data = hdmi,
- .no_capture_mute = 1,
- };
- int ret;
-
- aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
- aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
- aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
- aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
- aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
- aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
-
- hdmi->audio_pdev = platform_device_register_data(dev,
- HDMI_CODEC_DRV_NAME,
- PLATFORM_DEVID_AUTO,
- &codec_data,
- sizeof(codec_data));
- if (IS_ERR(hdmi->audio_pdev))
- return PTR_ERR(hdmi->audio_pdev);
-
- ret = devm_add_action_or_reset(dev, mtk_hdmi_unregister_audio_driver,
- hdmi->audio_pdev);
- if (ret)
- return ret;
-
- return 0;
-}
-
static int mtk_hdmi_probe(struct platform_device *pdev)
{
- const struct mtk_hdmi_ver_conf *ver_conf;
struct mtk_hdmi *hdmi;
- struct device *dev = &pdev->dev;
- const int num_clocks = MTK_HDMI_CLK_COUNT;
int ret;
- hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
- if (!hdmi)
- return -ENOMEM;
+ hdmi = mtk_hdmi_common_probe(pdev);
+ if (IS_ERR(hdmi))
+ return PTR_ERR(hdmi);
- hdmi->dev = dev;
- hdmi->conf = of_device_get_match_data(dev);
- ver_conf = hdmi->conf->ver_conf;
-
- hdmi->clk = devm_kcalloc(dev, ver_conf->num_clocks, sizeof(*hdmi->clk), GFP_KERNEL);
- if (!hdmi->clk)
- return -ENOMEM;
-
- ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev, ver_conf->mtk_hdmi_clock_names,
- ver_conf->num_clocks);
- if (ret)
- return ret;
-
- hdmi->phy = devm_phy_get(dev, "hdmi");
- if (IS_ERR(hdmi->phy))
- return dev_err_probe(dev, PTR_ERR(hdmi->phy),
- "Failed to get HDMI PHY\n");
-
- mutex_init(&hdmi->update_plugged_status_lock);
- platform_set_drvdata(pdev, hdmi);
-
- ret = mtk_hdmi_register_audio_driver(dev);
- if (ret)
- return dev_err_probe(dev, ret,
- "Failed to register audio driver\n");
-
- hdmi->bridge.funcs = ver_conf->bridge_funcs;
- hdmi->bridge.of_node = pdev->dev.of_node;
- hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
- | DRM_BRIDGE_OP_HPD;
- hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
- hdmi->bridge.vendor = "MediaTek";
- hdmi->bridge.product = "On-Chip HDMI";
-
- ret = devm_drm_bridge_add(dev, &hdmi->bridge);
- if (ret)
- return dev_err_probe(dev, ret, "Failed to add bridge\n");
+ if (!hdmi->cec_dev)
+ return dev_err_probe(hdmi->dev, -ENODEV, "CEC is required by HDMIv1\n");
ret = mtk_hdmi_clk_enable_audio(hdmi);
if (ret)
- return dev_err_probe(dev, ret,
+ return dev_err_probe(hdmi->dev, ret,
"Failed to enable audio clocks\n");
return 0;
@@ -1772,3 +1245,4 @@ MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
MODULE_DESCRIPTION("MediaTek HDMI Driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS("DRM_MTK_HDMI_V1");
+MODULE_IMPORT_NS("DRM_MTK_HDMI");
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
new file mode 100644
index 000000000000..3dfde63198e5
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
@@ -0,0 +1,426 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Copyright (c) 2024 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <drm/drm_modes.h>
+#include <linux/device.h>
+#include <linux/hdmi.h>
+#include <linux/i2c.h>
+#include <linux/math.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/syscon.h>
+#include <sound/hdmi-codec.h>
+
+#include "mtk_hdmi_common.h"
+
+struct hdmi_acr_n {
+ unsigned int clock;
+ unsigned int n[3];
+};
+
+/* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
+static const struct hdmi_acr_n hdmi_rec_n_table[] = {
+ /* Clock, N: 32kHz 44.1kHz 48kHz */
+ { 25175, { 4576, 7007, 6864 } },
+ { 74176, { 11648, 17836, 11648 } },
+ { 148352, { 11648, 8918, 5824 } },
+ { 296703, { 5824, 4459, 5824 } },
+ { 297000, { 3072, 4704, 5120 } },
+ { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */
+};
+
+/**
+ * hdmi_recommended_n() - Return N value recommended by HDMI specification
+ * @freq: audio sample rate in Hz
+ * @clock: rounded TMDS clock in kHz
+ */
+static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
+{
+ const struct hdmi_acr_n *recommended;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
+ if (clock == hdmi_rec_n_table[i].clock)
+ break;
+ }
+ recommended = hdmi_rec_n_table + i;
+
+ switch (freq) {
+ case 32000:
+ return recommended->n[0];
+ case 44100:
+ return recommended->n[1];
+ case 48000:
+ return recommended->n[2];
+ case 88200:
+ return recommended->n[1] * 2;
+ case 96000:
+ return recommended->n[2] * 2;
+ case 176400:
+ return recommended->n[1] * 4;
+ case 192000:
+ return recommended->n[2] * 4;
+ default:
+ return (128 * freq) / 1000;
+ }
+}
+
+static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
+{
+ switch (clock) {
+ case 25175:
+ return 25174825; /* 25.2/1.001 MHz */
+ case 74176:
+ return 74175824; /* 74.25/1.001 MHz */
+ case 148352:
+ return 148351648; /* 148.5/1.001 MHz */
+ case 296703:
+ return 296703297; /* 297/1.001 MHz */
+ default:
+ return clock * 1000;
+ }
+}
+
+static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
+ unsigned int tmds_clock, unsigned int n)
+{
+ return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
+ 128 * audio_sample_rate);
+}
+
+void mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock,
+ unsigned int *n, unsigned int *cts)
+{
+ *n = hdmi_recommended_n(sample_rate, clock);
+ *cts = hdmi_expected_cts(sample_rate, clock, *n);
+}
+EXPORT_SYMBOL_NS_GPL(mtk_hdmi_get_ncts, "DRM_MTK_HDMI");
+
+int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi,
+ struct hdmi_codec_daifmt *daifmt,
+ struct hdmi_codec_params *params)
+{
+ struct hdmi_audio_param aud_params = { 0 };
+ unsigned int chan = params->cea.channels;
+
+ dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
+ params->sample_rate, params->sample_width, chan);
+
+ if (!hdmi->bridge.encoder)
+ return -ENODEV;
+
+ switch (chan) {
+ case 2:
+ aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
+ break;
+ case 4:
+ aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
+ break;
+ case 6:
+ aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
+ break;
+ case 8:
+ aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
+ break;
+ default:
+ dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
+ return -EINVAL;
+ }
+
+ switch (params->sample_rate) {
+ case 32000:
+ case 44100:
+ case 48000:
+ case 88200:
+ case 96000:
+ case 176400:
+ case 192000:
+ break;
+ default:
+ dev_err(hdmi->dev, "rate[%d] not supported!\n",
+ params->sample_rate);
+ return -EINVAL;
+ }
+
+ switch (daifmt->fmt) {
+ case HDMI_I2S:
+ aud_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
+ aud_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+ aud_params.aud_input_type = HDMI_AUD_INPUT_I2S;
+ aud_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
+ aud_params.aud_mclk = HDMI_AUD_MCLK_128FS;
+ break;
+ case HDMI_SPDIF:
+ aud_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
+ aud_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+ aud_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
+ break;
+ default:
+ dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
+ daifmt->fmt);
+ return -EINVAL;
+ }
+ memcpy(&aud_params.codec_params, params, sizeof(aud_params.codec_params));
+ memcpy(&hdmi->aud_param, &aud_params, sizeof(aud_params));
+
+ dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
+ aud_params.aud_codec, aud_params.aud_input_type,
+ aud_params.aud_input_chan_type, aud_params.codec_params.sample_rate);
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(mtk_hdmi_audio_params, "DRM_MTK_HDMI");
+
+int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
+{
+ struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+
+ if (hdmi->enabled)
+ memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len));
+ else
+ memset(buf, 0, len);
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(mtk_hdmi_audio_get_eld, "DRM_MTK_HDMI");
+
+void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_codec_plugged_cb fn,
+ struct device *codec_dev)
+{
+ mutex_lock(&hdmi->update_plugged_status_lock);
+ hdmi->plugged_cb = fn;
+ hdmi->codec_dev = codec_dev;
+ mutex_unlock(&hdmi->update_plugged_status_lock);
+}
+EXPORT_SYMBOL_NS_GPL(mtk_hdmi_audio_set_plugged_cb, "DRM_MTK_HDMI");
+
+static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, struct device_node *np,
+ const char * const *clock_names, size_t num_clocks)
+{
+ int i;
+
+ for (i = 0; i < num_clocks; i++) {
+ hdmi->clk[i] = of_clk_get_by_name(np, clock_names[i]);
+
+ if (IS_ERR(hdmi->clk[i]))
+ return PTR_ERR(hdmi->clk[i]);
+ }
+
+ return 0;
+}
+
+bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true;
+}
+EXPORT_SYMBOL_NS_GPL(mtk_hdmi_bridge_mode_fixup, "DRM_MTK_HDMI");
+
+void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
+{
+ struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+
+ dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
+ adjusted_mode->name, adjusted_mode->hdisplay);
+ dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
+ adjusted_mode->hsync_start, adjusted_mode->hsync_end,
+ adjusted_mode->htotal);
+ dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
+ adjusted_mode->hskew, adjusted_mode->vdisplay);
+ dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
+ adjusted_mode->vsync_start, adjusted_mode->vsync_end,
+ adjusted_mode->vtotal);
+ dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
+ adjusted_mode->vscan, adjusted_mode->flags);
+
+ drm_mode_copy(&hdmi->mode, adjusted_mode);
+}
+EXPORT_SYMBOL_NS_GPL(mtk_hdmi_bridge_mode_set, "DRM_MTK_HDMI");
+
+static int mtk_hdmi_get_cec_dev(struct mtk_hdmi *hdmi, struct device *dev, struct device_node *np)
+{
+ struct platform_device *cec_pdev;
+ struct device_node *cec_np;
+ int ret;
+
+ /* The CEC module handles HDMI hotplug detection */
+ cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
+ if (!cec_np)
+ return dev_err_probe(dev, -EINVAL, "Failed to find CEC node\n");
+
+ cec_pdev = of_find_device_by_node(cec_np);
+ if (!cec_pdev) {
+ dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
+ cec_np);
+ of_node_put(cec_np);
+ return -EPROBE_DEFER;
+ }
+ of_node_put(cec_np);
+
+ /*
+ * The mediatek,syscon-hdmi property contains a phandle link to the
+ * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
+ * registers it contains.
+ */
+ hdmi->sys_regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
+ if (IS_ERR(hdmi->sys_regmap))
+ return PTR_ERR(hdmi->sys_regmap);
+
+ ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1, &hdmi->sys_offset);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to get system configuration registers\n");
+
+ hdmi->cec_dev = &cec_pdev->dev;
+ return 0;
+}
+
+static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct platform_device *pdev,
+ const char * const *clk_names, size_t num_clocks)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *remote, *i2c_np;
+ int ret;
+
+ ret = mtk_hdmi_get_all_clk(hdmi, np, clk_names, num_clocks);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to get clocks\n");
+
+ hdmi->regs = device_node_to_regmap(dev->of_node);
+ if (IS_ERR(hdmi->regs))
+ return PTR_ERR(hdmi->regs);
+
+ remote = of_graph_get_remote_node(np, 1, 0);
+ if (!remote)
+ return -EINVAL;
+
+ if (!of_device_is_compatible(remote, "hdmi-connector")) {
+ hdmi->next_bridge = of_drm_find_bridge(remote);
+ if (!hdmi->next_bridge) {
+ dev_err(dev, "Waiting for external bridge\n");
+ of_node_put(remote);
+ return -EPROBE_DEFER;
+ }
+ }
+
+ i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
+ of_node_put(remote);
+ if (!i2c_np)
+ return dev_err_probe(dev, -EINVAL, "No ddc-i2c-bus in connector\n");
+
+ hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
+ of_node_put(i2c_np);
+ if (!hdmi->ddc_adpt)
+ return dev_err_probe(dev, -EINVAL, "Failed to get ddc i2c adapter by node\n");
+
+ ret = mtk_hdmi_get_cec_dev(hdmi, dev, np);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void mtk_hdmi_unregister_audio_driver(void *data)
+{
+ platform_device_unregister(data);
+}
+
+static int mtk_hdmi_register_audio_driver(struct device *dev)
+{
+ struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+ struct hdmi_audio_param *aud_param = &hdmi->aud_param;
+ struct hdmi_codec_pdata codec_data = {
+ .ops = hdmi->conf->ver_conf->codec_ops,
+ .max_i2s_channels = 2,
+ .i2s = 1,
+ .data = hdmi,
+ .no_capture_mute = 1,
+ };
+ int ret;
+
+ aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
+ aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+ aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
+ aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
+ aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
+ aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
+
+ hdmi->audio_pdev = platform_device_register_data(dev,
+ HDMI_CODEC_DRV_NAME,
+ PLATFORM_DEVID_AUTO,
+ &codec_data,
+ sizeof(codec_data));
+ if (IS_ERR(hdmi->audio_pdev))
+ return PTR_ERR(hdmi->audio_pdev);
+
+ ret = devm_add_action_or_reset(dev, mtk_hdmi_unregister_audio_driver,
+ hdmi->audio_pdev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev)
+{
+ const struct mtk_hdmi_ver_conf *ver_conf;
+ struct device *dev = &pdev->dev;
+ struct mtk_hdmi *hdmi;
+ int ret;
+
+ hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
+ if (!hdmi)
+ return ERR_PTR(-ENOMEM);
+
+ hdmi->dev = dev;
+ hdmi->conf = of_device_get_match_data(dev);
+ ver_conf = hdmi->conf->ver_conf;
+
+ hdmi->clk = devm_kcalloc(dev, ver_conf->num_clocks, sizeof(*hdmi->clk), GFP_KERNEL);
+ if (!hdmi->clk)
+ return ERR_PTR(-ENOMEM);
+
+ ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev, ver_conf->mtk_hdmi_clock_names,
+ ver_conf->num_clocks);
+ if (ret)
+ return ERR_PTR(ret);
+
+ hdmi->phy = devm_phy_get(dev, "hdmi");
+ if (IS_ERR(hdmi->phy))
+ return dev_err_cast_probe(dev, hdmi->phy, "Failed to get HDMI PHY\n");
+
+ mutex_init(&hdmi->update_plugged_status_lock);
+ platform_set_drvdata(pdev, hdmi);
+
+ ret = mtk_hdmi_register_audio_driver(dev);
+ if (ret)
+ return dev_err_ptr_probe(dev, ret, "Cannot register HDMI Audio driver\n");
+
+ hdmi->bridge.funcs = ver_conf->bridge_funcs;
+ hdmi->bridge.of_node = pdev->dev.of_node;
+ hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
+ | DRM_BRIDGE_OP_HPD;
+ hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
+ hdmi->bridge.vendor = "MediaTek";
+ hdmi->bridge.product = "On-Chip HDMI";
+
+ ret = devm_drm_bridge_add(dev, &hdmi->bridge);
+ if (ret)
+ return dev_err_ptr_probe(dev, ret, "Failed to add bridge\n");
+
+ return hdmi;
+}
+EXPORT_SYMBOL_NS_GPL(mtk_hdmi_common_probe, "DRM_MTK_HDMI");
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_DESCRIPTION("MediaTek HDMI Common Library");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
new file mode 100644
index 000000000000..d3de8afff40f
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
@@ -0,0 +1,188 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2024 Collabora Ltd.
+ */
+
+#ifndef _MTK_HDMI_COMMON_H
+#define _MTK_HDMI_COMMON_H
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_print.h>
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/hdmi.h>
+#include <linux/i2c.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mutex.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+
+#include <sound/hdmi-codec.h>
+
+enum hdmi_aud_input_type {
+ HDMI_AUD_INPUT_I2S = 0,
+ HDMI_AUD_INPUT_SPDIF,
+};
+
+enum hdmi_aud_i2s_fmt {
+ HDMI_I2S_MODE_RJT_24BIT = 0,
+ HDMI_I2S_MODE_RJT_16BIT,
+ HDMI_I2S_MODE_LJT_24BIT,
+ HDMI_I2S_MODE_LJT_16BIT,
+ HDMI_I2S_MODE_I2S_24BIT,
+ HDMI_I2S_MODE_I2S_16BIT
+};
+
+enum hdmi_aud_mclk {
+ HDMI_AUD_MCLK_128FS,
+ HDMI_AUD_MCLK_192FS,
+ HDMI_AUD_MCLK_256FS,
+ HDMI_AUD_MCLK_384FS,
+ HDMI_AUD_MCLK_512FS,
+ HDMI_AUD_MCLK_768FS,
+ HDMI_AUD_MCLK_1152FS,
+};
+
+enum hdmi_aud_channel_type {
+ HDMI_AUD_CHAN_TYPE_1_0 = 0,
+ HDMI_AUD_CHAN_TYPE_1_1,
+ HDMI_AUD_CHAN_TYPE_2_0,
+ HDMI_AUD_CHAN_TYPE_2_1,
+ HDMI_AUD_CHAN_TYPE_3_0,
+ HDMI_AUD_CHAN_TYPE_3_1,
+ HDMI_AUD_CHAN_TYPE_4_0,
+ HDMI_AUD_CHAN_TYPE_4_1,
+ HDMI_AUD_CHAN_TYPE_5_0,
+ HDMI_AUD_CHAN_TYPE_5_1,
+ HDMI_AUD_CHAN_TYPE_6_0,
+ HDMI_AUD_CHAN_TYPE_6_1,
+ HDMI_AUD_CHAN_TYPE_7_0,
+ HDMI_AUD_CHAN_TYPE_7_1,
+ HDMI_AUD_CHAN_TYPE_3_0_LRS,
+ HDMI_AUD_CHAN_TYPE_3_1_LRS,
+ HDMI_AUD_CHAN_TYPE_4_0_CLRS,
+ HDMI_AUD_CHAN_TYPE_4_1_CLRS,
+ HDMI_AUD_CHAN_TYPE_6_1_CS,
+ HDMI_AUD_CHAN_TYPE_6_1_CH,
+ HDMI_AUD_CHAN_TYPE_6_1_OH,
+ HDMI_AUD_CHAN_TYPE_6_1_CHR,
+ HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
+ HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
+ HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
+ HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
+ HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
+ HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
+ HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
+ HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
+ HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
+ HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
+ HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
+ HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
+ HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
+ HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
+ HDMI_AUD_CHAN_TYPE_6_0_CS,
+ HDMI_AUD_CHAN_TYPE_6_0_CH,
+ HDMI_AUD_CHAN_TYPE_6_0_OH,
+ HDMI_AUD_CHAN_TYPE_6_0_CHR,
+ HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
+ HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
+ HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
+ HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
+ HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
+ HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
+ HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
+ HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
+ HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
+ HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
+ HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
+ HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
+ HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
+ HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
+ HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
+ HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
+};
+
+enum hdmi_aud_channel_swap_type {
+ HDMI_AUD_SWAP_LR,
+ HDMI_AUD_SWAP_LFE_CC,
+ HDMI_AUD_SWAP_LSRS,
+ HDMI_AUD_SWAP_RLS_RRS,
+ HDMI_AUD_SWAP_LR_STATUS,
+};
+
+struct hdmi_audio_param {
+ enum hdmi_audio_coding_type aud_codec;
+ enum hdmi_audio_sample_size aud_sample_size;
+ enum hdmi_aud_input_type aud_input_type;
+ enum hdmi_aud_i2s_fmt aud_i2s_fmt;
+ enum hdmi_aud_mclk aud_mclk;
+ enum hdmi_aud_channel_type aud_input_chan_type;
+ struct hdmi_codec_params codec_params;
+};
+
+struct mtk_hdmi_ver_conf {
+ const struct drm_bridge_funcs *bridge_funcs;
+ const struct hdmi_codec_ops *codec_ops;
+ const char * const *mtk_hdmi_clock_names;
+ int num_clocks;
+};
+
+struct mtk_hdmi_conf {
+ const struct mtk_hdmi_ver_conf *ver_conf;
+ bool tz_disabled;
+ bool cea_modes_only;
+ unsigned long max_mode_clock;
+};
+
+struct mtk_hdmi {
+ struct drm_bridge bridge;
+ struct drm_bridge *next_bridge;
+ struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
+ struct device *dev;
+ const struct mtk_hdmi_conf *conf;
+ struct phy *phy;
+ struct device *cec_dev;
+ struct i2c_adapter *ddc_adpt;
+ struct clk **clk;
+ struct drm_display_mode mode;
+ bool dvi_mode;
+ struct regmap *sys_regmap;
+ unsigned int sys_offset;
+ struct regmap *regs;
+ struct platform_device *audio_pdev;
+ struct hdmi_audio_param aud_param;
+ bool audio_enable;
+ bool powered;
+ bool enabled;
+ hdmi_codec_plugged_cb plugged_cb;
+ struct device *codec_dev;
+ struct mutex update_plugged_status_lock;
+};
+
+static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
+{
+ return container_of(b, struct mtk_hdmi, bridge);
+}
+
+
+int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len);
+void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_codec_plugged_cb fn,
+ struct device *codec_dev);
+int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi, struct hdmi_codec_daifmt *daifmt,
+ struct hdmi_codec_params *params);
+void mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock,
+ unsigned int *n, unsigned int *cts);
+bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode);
+void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode);
+struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev);
+#endif /* _MTK_HDMI_COMMON_H */
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 36/43] drm/mediatek: mtk_hdmi: Split driver and add common probe function
2025-02-17 15:48 ` [PATCH v7 36/43] drm/mediatek: mtk_hdmi: Split driver and add common probe function AngeloGioacchino Del Regno
@ 2025-02-27 5:56 ` CK Hu (胡俊光)
0 siblings, 0 replies; 74+ messages in thread
From: CK Hu (胡俊光) @ 2025-02-27 5:56 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, chunkuang.hu
Cc: robh, jie.qiu, tzimmermann, simona, mripard,
Jitao Shi (石记涛),
linux-mediatek, dri-devel, maarten.lankhorst, linux-kernel,
devicetree, kernel, dmitry.baryshkov, krzk+dt,
Lewis Liao (廖柏鈞),
p.zabel, conor+dt, TommyYL Chen (陳彥良),
Ives Chenjh (陳俊弘),
airlied, linux-arm-kernel, matthias.bgg,
Jason-JH Lin (林睿祥),
junzhi.zhao
On Mon, 2025-02-17 at 16:48 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
>
>
> In preparation for adding a new driver for the HDMI TX v2 IP,
> split out the functions that will be common between the already
> present mtk_hdmi (v1) driver and the new one.
>
> Since the probe flow for both drivers is 90% similar, add a common
> probe function that will be called from each driver's .probe()
> callback, avoiding lots of code duplication.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/Kconfig | 11 +-
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 542 +--------------------
> drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 426 ++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_hdmi_common.h | 188 +++++++
> 5 files changed, 633 insertions(+), 535 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.h
>
> diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
> index e47debd60619..994b48b82d44 100644
> --- a/drivers/gpu/drm/mediatek/Kconfig
> +++ b/drivers/gpu/drm/mediatek/Kconfig
> @@ -30,9 +30,18 @@ config DRM_MEDIATEK_DP
> help
> DRM/KMS Display Port driver for MediaTek SoCs.
>
> +config DRM_MEDIATEK_HDMI_COMMON
> + tristate
> + depends on DRM_MEDIATEK
> + select DRM_DISPLAY_HDMI_HELPER
> + select DRM_DISPLAY_HELPER
> + select SND_SOC_HDMI_CODEC if SND_SOC
> + help
> + MediaTek SoC HDMI common library
> +
> config DRM_MEDIATEK_HDMI
> tristate "DRM HDMI Support for Mediatek SoCs"
> depends on DRM_MEDIATEK
> - select SND_SOC_HDMI_CODEC if SND_SOC
> + select DRM_MEDIATEK_HDMI_COMMON
> help
> DRM/KMS HDMI driver for Mediatek SoCs
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 43afd0a26d14..78cf2d4fc85f 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -21,6 +21,7 @@ mediatek-drm-y := mtk_crtc.o \
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> +obj-$(CONFIG_DRM_MEDIATEK_HDMI_COMMON) += mtk_hdmi_common.o
The whole patch looks good to me.
But make common part to a module looks a little bit more modularized.
Let things to be simple, I would like the whole MediaTek hdmi driver be a single module.
For MediaTek drm driver, it is already broken to mediatek-drm, hdmi, dp modules.
Maybe someday dsi or dpi would be broken to modules.
So I would like hdmi to be a single module which include v1, v2 and common part.
If someday we need to optimize code size, then send patch to break hdmi module.
Regards,
CK
> obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_cec.o
> obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_hdmi.o
> obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_hdmi_ddc.o
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 37/43] drm/mediatek: mtk_hdmi_common: Make CEC support optional
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (35 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 36/43] drm/mediatek: mtk_hdmi: Split driver and add common probe function AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 38/43] drm/mediatek: mtk_hdmi_common: Assign DDC adapter pointer to bridge AngeloGioacchino Del Regno
` (6 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
In preparation for adding a new driver for HDMIv2, for which CEC
is not strictly required, change the of_get_compatible_child()
failure error to -ENOTSUPP to be able to differentiate between
error conditions in mtk_hdmi_dt_parse_pdata().
In that case, if -ENOTSUPP is returned, this driver will print
an informative message saying that CEC support is unavailable,
as the devicetree node for that was not found, but after that,
function mtk_hdmi_dt_parse_pdata() will not return error to
the caller.
This will not change functionality of the mtk_hdmi (v1) driver
as that is still checking whether CEC is present and, if not,
will fail probing with an error saying that CEC is required
by HDMIv1.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
index 3dfde63198e5..5ea45608921c 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
@@ -254,12 +254,11 @@ static int mtk_hdmi_get_cec_dev(struct mtk_hdmi *hdmi, struct device *dev, struc
/* The CEC module handles HDMI hotplug detection */
cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
if (!cec_np)
- return dev_err_probe(dev, -EINVAL, "Failed to find CEC node\n");
+ return dev_err_probe(dev, -ENOTSUPP, "Failed to find CEC node\n");
cec_pdev = of_find_device_by_node(cec_np);
if (!cec_pdev) {
- dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
- cec_np);
+ dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", cec_np);
of_node_put(cec_np);
return -EPROBE_DEFER;
}
@@ -323,7 +322,9 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct platform_device
return dev_err_probe(dev, -EINVAL, "Failed to get ddc i2c adapter by node\n");
ret = mtk_hdmi_get_cec_dev(hdmi, dev, np);
- if (ret)
+ if (ret == -ENOTSUPP)
+ dev_info(dev, "CEC support unavailable: node not found\n");
+ else if (ret)
return ret;
return 0;
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 38/43] drm/mediatek: mtk_hdmi_common: Assign DDC adapter pointer to bridge
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (36 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 37/43] drm/mediatek: mtk_hdmi_common: Make CEC support optional AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 39/43] drm/mediatek: mtk_hdmi_common: Add OP_HDMI if helper funcs assigned AngeloGioacchino Del Regno
` (5 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
In preparation for adding the new HDMI TX v2 IP driver, assign the
pointer to the DDC adapter to struct drm_bridge during probe.
This commit brings no functional changes.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
index 5ea45608921c..2c91f65f26fa 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
@@ -411,6 +411,7 @@ struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev)
hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
| DRM_BRIDGE_OP_HPD;
hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
+ hdmi->bridge.ddc = hdmi->ddc_adpt;
hdmi->bridge.vendor = "MediaTek";
hdmi->bridge.product = "On-Chip HDMI";
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 39/43] drm/mediatek: mtk_hdmi_common: Add OP_HDMI if helper funcs assigned
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (37 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 38/43] drm/mediatek: mtk_hdmi_common: Assign DDC adapter pointer to bridge AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 40/43] drm/mediatek: mtk_hdmi_common: Add var to enable interlaced modes AngeloGioacchino Del Regno
` (4 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
In preparation for adding the HDMI TX v2 driver, and to allow
a future modernization of the HDMI v1 one, perform changes
that enable the usage of the HDMI Helpers provided by DRM.
Check if the HDMI driver provides the function pointers to
hdmi_{clear,write}_infoframe used by the HDMI Helper API and,
if present, add DRM_BRIDGE_OP_HDMI to the drm_bridge ops,
enabling the drm API to register the bridge as HDMI and to use
the HDMI Helper functions.
If the hdmi_{write,clear}_infoframe pointers are not assigned,
vendor and product strings and HDMI helpers will not be used,
hence this commit brings no functional changes to drivers that
have not been refactored to use the new helpers.
This also means that, in the current state, there is effectively
no functional change to mtk_hdmi and its other components.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
index 2c91f65f26fa..d58752b772e8 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
@@ -410,6 +410,11 @@ struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev)
hdmi->bridge.of_node = pdev->dev.of_node;
hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
| DRM_BRIDGE_OP_HPD;
+
+ if (ver_conf->bridge_funcs->hdmi_write_infoframe &&
+ ver_conf->bridge_funcs->hdmi_clear_infoframe)
+ hdmi->bridge.ops |= DRM_BRIDGE_OP_HDMI;
+
hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
hdmi->bridge.ddc = hdmi->ddc_adpt;
hdmi->bridge.vendor = "MediaTek";
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 40/43] drm/mediatek: mtk_hdmi_common: Add var to enable interlaced modes
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (38 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 39/43] drm/mediatek: mtk_hdmi_common: Add OP_HDMI if helper funcs assigned AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-17 15:48 ` [PATCH v7 41/43] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188 AngeloGioacchino Del Regno
` (3 subsequent siblings)
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
Add an interlace_allowed bool member to struct mtk_hdmi_ver_conf
which will be used to signal whether interlaced modes are supported
by the bridge (in our case, the HDMI IP), and enable it for HDMIv2.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 1 +
drivers/gpu/drm/mediatek/mtk_hdmi_common.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
index d58752b772e8..9d1b29ddfb8d 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
@@ -419,6 +419,7 @@ struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev)
hdmi->bridge.ddc = hdmi->ddc_adpt;
hdmi->bridge.vendor = "MediaTek";
hdmi->bridge.product = "On-Chip HDMI";
+ hdmi->bridge.interlace_allowed = ver_conf->interlace_allowed;
ret = devm_drm_bridge_add(dev, &hdmi->bridge);
if (ret)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
index d3de8afff40f..38d1bdf4c77e 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
@@ -131,6 +131,7 @@ struct mtk_hdmi_ver_conf {
const struct hdmi_codec_ops *codec_ops;
const char * const *mtk_hdmi_clock_names;
int num_clocks;
+ bool interlace_allowed;
};
struct mtk_hdmi_conf {
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v7 41/43] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (39 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 40/43] drm/mediatek: mtk_hdmi_common: Add var to enable interlaced modes AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-27 8:17 ` CK Hu (胡俊光)
2025-02-17 15:48 ` [PATCH v7 42/43] drm/mediatek: mtk_hdmi_v2: Add debugfs ops and implement ABIST AngeloGioacchino Del Regno
` (2 subsequent siblings)
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
found in MediaTek's MT8195, MT8188 SoC and their variants, and
including support for display modes up to 4k60 and for HDMI
Audio, as per the HDMI 2.0 spec.
HDCP and CEC functionalities are also supported by this hardware,
but are not included in this commit and that also poses a slight
difference between the V2 and V1 controllers in how they handle
Hotplug Detection (HPD).
While the v1 controller was using the CEC controller to check
HDMI cable connection and disconnection, in this driver the v2
one does not.
This is due to the fact that on parts with v2 designs, like the
MT8195 SoC, there is one CEC controller shared between the HDMI
Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
adding support to use the CEC HW to wake up the HDMI controllers
it is necessary to have support for one TX, one RX *and* for both
at the same time.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/Kconfig | 7 +
drivers/gpu/drm/mediatek/Makefile | 2 +
drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 4 +
drivers/gpu/drm/mediatek/mtk_hdmi_common.h | 9 +
drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c | 385 ++++++
drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h | 263 ++++
drivers/gpu/drm/mediatek/mtk_hdmi_v2.c | 1352 +++++++++++++++++++
7 files changed, 2022 insertions(+)
create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
index 994b48b82d44..c89ae4ed2c96 100644
--- a/drivers/gpu/drm/mediatek/Kconfig
+++ b/drivers/gpu/drm/mediatek/Kconfig
@@ -45,3 +45,10 @@ config DRM_MEDIATEK_HDMI
select DRM_MEDIATEK_HDMI_COMMON
help
DRM/KMS HDMI driver for Mediatek SoCs
+
+config DRM_MEDIATEK_HDMI_V2
+ tristate "DRM HDMI v2 IP support for MediaTek SoCs"
+ depends on DRM_MEDIATEK
+ select DRM_MEDIATEK_HDMI_COMMON
+ help
+ DRM/KMS HDMI driver for MediaTek SoCs with HDMIv2 IP
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 78cf2d4fc85f..e0ac49b07d50 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -25,5 +25,7 @@ obj-$(CONFIG_DRM_MEDIATEK_HDMI_COMMON) += mtk_hdmi_common.o
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_cec.o
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_hdmi.o
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_hdmi_ddc.o
+obj-$(CONFIG_DRM_MEDIATEK_HDMI_V2) += mtk_hdmi_v2.o
+obj-$(CONFIG_DRM_MEDIATEK_HDMI_V2) += mtk_hdmi_ddc_v2.o
obj-$(CONFIG_DRM_MEDIATEK_DP) += mtk_dp.o
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
index 9d1b29ddfb8d..784bc05c9541 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
@@ -294,6 +294,10 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct platform_device
if (ret)
return dev_err_probe(dev, ret, "Failed to get clocks\n");
+ hdmi->irq = platform_get_irq(pdev, 0);
+ if (!hdmi->irq)
+ return hdmi->irq;
+
hdmi->regs = device_node_to_regmap(dev->of_node);
if (IS_ERR(hdmi->regs))
return PTR_ERR(hdmi->regs);
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
index 38d1bdf4c77e..de5e064585f8 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
@@ -126,6 +126,12 @@ struct hdmi_audio_param {
struct hdmi_codec_params codec_params;
};
+enum hdmi_hpd_state {
+ HDMI_PLUG_OUT = 0,
+ HDMI_PLUG_IN_AND_SINK_POWER_ON,
+ HDMI_PLUG_IN_ONLY,
+};
+
struct mtk_hdmi_ver_conf {
const struct drm_bridge_funcs *bridge_funcs;
const struct hdmi_codec_ops *codec_ops;
@@ -139,6 +145,7 @@ struct mtk_hdmi_conf {
bool tz_disabled;
bool cea_modes_only;
unsigned long max_mode_clock;
+ u32 reg_hdmi_tx_cfg;
};
struct mtk_hdmi {
@@ -161,6 +168,8 @@ struct mtk_hdmi {
bool audio_enable;
bool powered;
bool enabled;
+ unsigned int irq;
+ enum hdmi_hpd_state hpd;
hdmi_codec_plugged_cb plugged_cb;
struct device *codec_dev;
struct mutex update_plugged_status_lock;
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
new file mode 100644
index 000000000000..16b630dc1fdb
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
@@ -0,0 +1,385 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek HDMI v2 Display Data Channel Driver
+ *
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2021 BayLibre, SAS
+ * Copyright (c) 2024 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+
+#include <drm/drm_edid.h>
+
+#include "mtk_hdmi_common.h"
+#include "mtk_hdmi_regs_v2.h"
+
+#define DDC2_DLY_CNT 572 /* BIM=208M/(v*4) = 90Khz */
+#define DDC2_DLY_CNT_EDID 832 /* BIM=208M/(v*4) = 62.5Khz */
+#define SI2C_ADDR_READ 0xf4
+#define SCDC_I2C_SLAVE_ADDRESS 0x54
+
+struct mtk_hdmi_ddc {
+ struct device *dev;
+ void __iomem *regs;
+ struct clk *clk;
+ struct i2c_adapter adap;
+};
+
+static int mtk_ddc_check_and_rise_low_bus(struct mtk_hdmi_ddc *ddc)
+{
+ u32 val;
+
+ regmap_read(ddc->regs, HDCP2X_DDCM_STATUS, &val);
+ if (val & DDC_I2C_BUS_LOW) {
+ regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
+ FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLOCK_SCL));
+ usleep_range(250, 300);
+ }
+
+ if (val & DDC_I2C_NO_ACK) {
+ u32 ddc_ctrl, hpd_ddc_ctrl, hpd_ddc_status;
+
+ regmap_read(ddc->regs, DDC_CTRL, &ddc_ctrl);
+ regmap_read(ddc->regs, HPD_DDC_CTRL, &hpd_ddc_ctrl);
+ regmap_read(ddc->regs, HPD_DDC_STATUS, &hpd_ddc_status);
+ }
+
+ if (val & DDC_I2C_NO_ACK)
+ return -EIO;
+
+ return 0;
+}
+
+static int mtk_ddc_wr_one(struct mtk_hdmi_ddc *ddc, u16 addr_id,
+ u16 offset_id, u8 wr_data)
+{
+ u32 val;
+ int ret;
+
+ /* If down, rise bus for write operation */
+ mtk_ddc_check_and_rise_low_bus(ddc);
+
+ regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,
+ FIELD_PREP(HPD_DDC_DELAY_CNT, DDC2_DLY_CNT));
+
+ regmap_write(ddc->regs, SI2C_CTRL,
+ FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
+ FIELD_PREP(SI2C_WDATA, wr_data) |
+ SI2C_WR);
+
+ regmap_write(ddc->regs, DDC_CTRL,
+ FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_WRITE) |
+ FIELD_PREP(DDC_CTRL_DIN_CNT, 1) |
+ FIELD_PREP(DDC_CTRL_OFFSET, offset_id) |
+ FIELD_PREP(DDC_CTRL_ADDR, addr_id));
+ usleep_range(1000, 1250);
+
+ ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,
+ !(val & DDC_I2C_IN_PROG), 500, 1000);
+ if (ret) {
+ dev_err(ddc->dev, "DDC I2C write timeout\n");
+ return ret;
+ }
+
+ /* The I2C bus might be down after WR operation: rise it again */
+ ret = mtk_ddc_check_and_rise_low_bus(ddc);
+ if (ret) {
+ dev_err(ddc->dev, "Error during write operation: No ACK\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mtk_ddcm_read_hdmi(struct mtk_hdmi_ddc *ddc, u16 uc_dev,
+ u8 addr, u8 *puc_value, u16 data_cnt)
+{
+ u16 dly_cnt, i, loop_counter, temp_length, uc_idx;
+ u32 rem, uc_read_count, val;
+ int ret;
+
+ mtk_ddc_check_and_rise_low_bus(ddc);
+
+ regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
+ FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLEAR_FIFO));
+
+ if (data_cnt >= 16) {
+ temp_length = 16;
+ loop_counter = data_cnt;
+
+ rem = do_div(loop_counter, temp_length);
+ if (rem)
+ loop_counter++;
+ } else {
+ temp_length = data_cnt;
+ loop_counter = 1;
+ }
+
+ if (uc_dev >= DDC_ADDR)
+ dly_cnt = DDC2_DLY_CNT_EDID;
+ else
+ dly_cnt = DDC2_DLY_CNT;
+
+ regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,
+ FIELD_PREP(HPD_DDC_DELAY_CNT, dly_cnt));
+
+ for (i = 0; i < loop_counter; i++) {
+ rem = data_cnt % 16;
+
+ if (i > 0 && i == (loop_counter - 1) && rem)
+ temp_length = rem;
+
+ /* 0x51 - 0x53: Flow control */
+ if (uc_dev > DDC_ADDR && uc_dev <= 0x53) {
+ regmap_update_bits(ddc->regs, SCDC_CTRL, SCDC_DDC_SEGMENT,
+ FIELD_PREP(SCDC_DDC_SEGMENT, uc_dev - DDC_ADDR));
+
+ regmap_write(ddc->regs, DDC_CTRL,
+ FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ENH_READ_NOACK) |
+ FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) |
+ FIELD_PREP(DDC_CTRL_OFFSET, addr + i * temp_length) |
+ FIELD_PREP(DDC_CTRL_ADDR, DDC_ADDR));
+ } else {
+ u16 offset;
+
+ if (addr != 0x43)
+ offset = i * 16;
+ else
+ offset = 0;
+
+ regmap_write(ddc->regs, DDC_CTRL,
+ FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_READ_NOACK) |
+ FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) |
+ FIELD_PREP(DDC_CTRL_OFFSET, addr + offset) |
+ FIELD_PREP(DDC_CTRL_ADDR, uc_dev));
+ }
+ usleep_range(5000, 5500);
+
+ ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,
+ !(val & DDC_I2C_IN_PROG), 1000,
+ 500 * (temp_length + 5));
+ if (ret) {
+ dev_err(ddc->dev, "Timeout waiting for DDC I2C\n");
+ return ret;
+ }
+
+ ret = mtk_ddc_check_and_rise_low_bus(ddc);
+ if (ret) {
+ dev_err(ddc->dev, "Error during read operation: No ACK\n");
+ return ret;
+ }
+
+ for (uc_idx = 0; uc_idx < temp_length; uc_idx++) {
+ unsigned int read_idx = i * 16 + uc_idx;
+
+ regmap_write(ddc->regs, SI2C_CTRL,
+ FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
+ SI2C_RD);
+
+ regmap_read(ddc->regs, HPD_DDC_STATUS, &val);
+ puc_value[read_idx] = FIELD_GET(DDC_DATA_OUT, val);
+
+ regmap_write(ddc->regs, SI2C_CTRL,
+ FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
+ SI2C_CONFIRM_READ);
+
+ /*
+ * If HDMI IP gets reset during EDID read, DDC read
+ * operation will fail and its delay counter will be
+ * reset to 400.
+ */
+ regmap_read(ddc->regs, HPD_DDC_CTRL, &val);
+ if (FIELD_GET(HPD_DDC_DELAY_CNT, val) < DDC2_DLY_CNT)
+ return 0;
+
+ uc_read_count = read_idx + 1;
+ }
+ }
+ if (uc_read_count > U8_MAX)
+ dev_warn(ddc->dev, "Invalid read data count %u\n", uc_read_count);
+
+ return uc_read_count;
+}
+
+static int mtk_hdmi_fg_ddc_data_read(struct mtk_hdmi_ddc *ddc, u16 b_dev,
+ u8 data_addr, u16 data_cnt, u8 *pr_data)
+{
+ int read_data_cnt;
+ u16 req_data_cnt;
+
+ if (!data_cnt) {
+ dev_err(ddc->dev, "Invalid DDCM read request\n");
+ return -EINVAL;
+ }
+
+ req_data_cnt = U8_MAX - data_addr + 1;
+ if (req_data_cnt > data_cnt)
+ req_data_cnt = data_cnt;
+
+ regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);
+
+ read_data_cnt = mtk_ddcm_read_hdmi(ddc, b_dev, data_addr, pr_data, req_data_cnt);
+
+ if (read_data_cnt < 0)
+ return read_data_cnt;
+ else if (read_data_cnt != req_data_cnt)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int mtk_hdmi_ddc_fg_data_write(struct mtk_hdmi_ddc *ddc, u16 b_dev,
+ u8 data_addr, u16 data_cnt, u8 *pr_data)
+{
+ int i = 0, ret;
+
+ regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);
+ do {
+ ret = mtk_ddc_wr_one(ddc, b_dev, data_addr + i, pr_data[i]);
+ if (ret)
+ return ret;
+ } while (++i < data_cnt);
+
+ return 0;
+}
+
+static int mtk_hdmi_ddc_v2_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
+{
+ struct mtk_hdmi_ddc *ddc;
+ u8 offset = 0;
+ int i, ret;
+
+ ddc = adapter->algo_data;
+
+ for (i = 0; i < num; i++) {
+ struct i2c_msg *msg = &msgs[i];
+
+ if (!msg->buf) {
+ dev_err(ddc->dev, "No message buffer\n");
+ return -EINVAL;
+ }
+
+ if (msg->flags & I2C_M_RD) {
+ /*
+ * The underlying DDC hardware always issues a write request
+ * that assigns the read offset as part of the read operation,
+ * therefore, use the `offset` value assigned in the previous
+ * write request from drm_edid
+ */
+ ret = mtk_hdmi_fg_ddc_data_read(ddc, msg->addr, offset,
+ msg->len, &msg->buf[0]);
+ if (ret)
+ return ret;
+ } else {
+ /*
+ * The HW needs the data offset, found in buf[0], in the
+ * DDC_CTRL register, and each byte of data, starting at
+ * buf[1], goes in the SI2C_WDATA register.
+ */
+ ret = mtk_hdmi_ddc_fg_data_write(ddc, msg->addr, msg->buf[0],
+ msg->len - 1, &msg->buf[1]);
+ if (ret)
+ return ret;
+
+ /*
+ * Store the offset value requested by drm_edid or by
+ * scdc to use in subsequent read requests.
+ */
+ if ((msg->addr == DDC_ADDR || msg->addr == SCDC_I2C_SLAVE_ADDRESS) &&
+ msg->len == 1) {
+ offset = msg->buf[0];
+ }
+ }
+ }
+
+ return i;
+}
+
+static u32 mtk_hdmi_ddc_v2_func(struct i2c_adapter *adapter)
+{
+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm mtk_hdmi_ddc_v2_algorithm = {
+ .master_xfer = mtk_hdmi_ddc_v2_xfer,
+ .functionality = mtk_hdmi_ddc_v2_func,
+};
+
+static int mtk_hdmi_ddc_v2_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_hdmi_ddc *ddc;
+ int ret;
+
+ ddc = devm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL);
+ if (!ddc)
+ return -ENOMEM;
+
+ ddc->dev = dev;
+ ddc->regs = device_node_to_regmap(dev->parent->of_node);
+ if (IS_ERR_OR_NULL(ddc->regs))
+ return dev_err_probe(dev,
+ IS_ERR(ddc->regs) ? PTR_ERR(ddc->regs) : -EINVAL,
+ "Cannot get regmap\n");
+
+ ddc->clk = devm_clk_get_enabled(dev, NULL);
+ if (IS_ERR(ddc->clk))
+ return dev_err_probe(dev, PTR_ERR(ddc->clk), "Cannot get DDC clock\n");
+
+ strscpy(ddc->adap.name, "mediatek-hdmi-ddc-v2", sizeof(ddc->adap.name));
+ ddc->adap.owner = THIS_MODULE;
+ ddc->adap.algo = &mtk_hdmi_ddc_v2_algorithm;
+ ddc->adap.retries = 3;
+ ddc->adap.dev.of_node = dev->of_node;
+ ddc->adap.algo_data = ddc;
+ ddc->adap.dev.parent = &pdev->dev;
+
+ ret = devm_pm_runtime_enable(&pdev->dev);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "Cannot enable Runtime PM\n");
+
+ pm_runtime_get_sync(dev);
+
+ ret = devm_i2c_add_adapter(dev, &ddc->adap);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Cannot add DDC I2C adapter\n");
+
+ platform_set_drvdata(pdev, ddc);
+ return 0;
+}
+
+static const struct of_device_id mtk_hdmi_ddc_v2_match[] = {
+ { .compatible = "mediatek,mt8195-hdmi-ddc" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mtk_hdmi_ddc_v2_match);
+
+struct platform_driver mtk_hdmi_ddc_v2_driver = {
+ .probe = mtk_hdmi_ddc_v2_probe,
+ .driver = {
+ .name = "mediatek-hdmi-ddc-v2",
+ .of_match_table = mtk_hdmi_ddc_v2_match,
+ },
+};
+module_platform_driver(mtk_hdmi_ddc_v2_driver);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_AUTHOR("Can Zeng <can.zeng@mediatek.com>");
+MODULE_DESCRIPTION("MediaTek HDMIv2 DDC Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h b/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
new file mode 100644
index 000000000000..521b35c7e14d
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
@@ -0,0 +1,263 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2021 BayLibre, SAS
+ * Copyright (c) 2024 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#ifndef _MTK_HDMI_REGS_H
+#define _MTK_HDMI_REGS_H
+
+/* HDMI_TOP Config */
+#define TOP_CFG00 0x000
+#define HDMI2_ON BIT(2)
+#define HDMI_MODE_HDMI BIT(3)
+#define SCR_ON BIT(4)
+#define TMDS_PACK_MODE GENMASK(9, 8)
+#define TMDS_PACK_MODE_8BPP 0
+#define TMDS_PACK_MODE_10BPP 1
+#define TMDS_PACK_MODE_12BPP 2
+#define TMDS_PACK_MODE_16BPP 3
+#define DEEPCOLOR_PKT_EN BIT(12)
+#define HDMI_ABIST_VIDEO_FORMAT GENMASK(21, 16)
+#define HDMI_ABIST_ENABLE BIT(31)
+#define TOP_CFG01 0x004
+#define CP_SET_MUTE_EN BIT(0)
+#define CP_CLR_MUTE_EN BIT(1)
+#define NULL_PKT_EN BIT(2)
+#define NULL_PKT_VSYNC_HIGH_EN BIT(3)
+
+/* HDMI_TOP Audio: Channel Mapping */
+#define TOP_AUD_MAP 0x00c
+#define SD0_MAP GENMASK(2, 0)
+#define SD1_MAP GENMASK(6, 4)
+#define SD2_MAP GENMASK(10, 8)
+#define SD3_MAP GENMASK(14, 12)
+#define SD4_MAP GENMASK(18, 16)
+#define SD5_MAP GENMASK(22, 20)
+#define SD6_MAP GENMASK(26, 24)
+#define SD7_MAP GENMASK(30, 28)
+
+/* Auxiliary Video Information (AVI) Infoframe */
+#define TOP_AVI_HEADER 0x024
+#define TOP_AVI_PKT00 0x028
+#define TOP_AVI_PKT01 0x02C
+#define TOP_AVI_PKT02 0x030
+#define TOP_AVI_PKT03 0x034
+#define TOP_AVI_PKT04 0x038
+#define TOP_AVI_PKT05 0x03C
+
+/* Audio Interface Infoframe */
+#define TOP_AIF_HEADER 0x040
+#define TOP_AIF_PKT00 0x044
+#define TOP_AIF_PKT01 0x048
+#define TOP_AIF_PKT02 0x04c
+#define TOP_AIF_PKT03 0x050
+
+/* Audio SPDIF Infoframe */
+#define TOP_SPDIF_HEADER 0x054
+#define TOP_SPDIF_PKT00 0x058
+#define TOP_SPDIF_PKT01 0x05c
+#define TOP_SPDIF_PKT02 0x060
+#define TOP_SPDIF_PKT03 0x064
+#define TOP_SPDIF_PKT04 0x068
+#define TOP_SPDIF_PKT05 0x06c
+#define TOP_SPDIF_PKT06 0x070
+#define TOP_SPDIF_PKT07 0x074
+
+/* Infoframes Configuration */
+#define TOP_INFO_EN 0x01c
+#define AVI_EN BIT(0)
+#define SPD_EN BIT(1)
+#define AUD_EN BIT(2)
+#define CP_EN BIT(5)
+#define VSIF_EN BIT(11)
+#define AVI_EN_WR BIT(16)
+#define SPD_EN_WR BIT(17)
+#define AUD_EN_WR BIT(18)
+#define CP_EN_WR BIT(21)
+#define VSIF_EN_WR BIT(27)
+#define TOP_INFO_RPT 0x020
+#define AVI_RPT_EN BIT(0)
+#define SPD_RPT_EN BIT(1)
+#define AUD_RPT_EN BIT(2)
+#define CP_RPT_EN BIT(5)
+#define VSIF_RPT_EN BIT(11)
+
+/* Vendor Specific Infoframe */
+#define TOP_VSIF_HEADER 0x174
+#define TOP_VSIF_PKT00 0x178
+#define TOP_VSIF_PKT01 0x17c
+#define TOP_VSIF_PKT02 0x180
+#define TOP_VSIF_PKT03 0x184
+#define TOP_VSIF_PKT04 0x188
+#define TOP_VSIF_PKT05 0x18c
+#define TOP_VSIF_PKT06 0x190
+#define TOP_VSIF_PKT07 0x194
+
+/* HDMI_TOP Misc */
+#define TOP_MISC_CTLR 0x1a4
+#define DEEP_COLOR_ADD BIT(4)
+
+/* Hardware interrupts */
+#define TOP_INT_STA00 0x1a8
+#define TOP_INT_ENABLE00 0x1b0
+#define HTPLG_R_INT BIT(0)
+#define HTPLG_F_INT BIT(1)
+#define PORD_R_INT BIT(2)
+#define PORD_F_INT BIT(3)
+#define HDMI_VSYNC_INT BIT(4)
+#define HDMI_AUDIO_INT BIT(5)
+#define HDCP2X_RX_REAUTH_REQ_DDCM_INT BIT(25)
+#define TOP_INT_ENABLE01 0x1b4
+#define TOP_INT_CLR00 0x1b8
+#define TOP_INT_CLR01 0x1bc
+
+
+/* Video Mute */
+#define TOP_VMUTE_CFG1 0x1c8
+#define REG_VMUTE_EN BIT(16)
+
+/* HDMI Audio IP */
+#define AIP_CTRL 0x400
+#define CTS_SW_SEL BIT(0)
+#define CTS_REQ_EN BIT(1)
+#define MCLK_EN BIT(2)
+#define NO_MCLK_CTSGEN_SEL BIT(3)
+#define AUD_IN_EN BIT(8)
+#define AUD_SEL_OWRT BIT(9)
+#define SPDIF_EN BIT(13)
+#define HBRA_ON BIT(14)
+#define DSD_EN BIT(15)
+#define I2S_EN GENMASK(19, 16)
+#define HBR_FROM_SPDIF BIT(20)
+#define CTS_CAL_N4 BIT(23)
+#define SPDIF_INTERNAL_MODULE BIT(24)
+#define AIP_N_VAL 0x404
+#define AIP_CTS_SVAL 0x408
+#define AIP_SPDIF_CTRL 0x40c
+#define WR_1UI_LOCK BIT(0)
+#define FS_OVERRIDE_WRITE BIT(1)
+#define WR_2UI_LOCK BIT(2)
+#define MAX_1UI_WRITE GENMASK(15, 8)
+#define MAX_2UI_SPDIF_WRITE GENMASK(23, 16)
+#define MAX_2UI_I2S_HI_WRITE GENMASK(23, 20)
+#define MAX_2UI_I2S_LFE_CC_SWAP BIT(1)
+#define MAX_2UI_I2S_LO_WRITE GENMASK(19, 16)
+#define AUD_ERR_THRESH GENMASK(29, 24)
+#define I2S2DSD_EN BIT(30)
+#define AIP_I2S_CTRL 0x410
+#define FIFO0_MAP GENMASK(1, 0)
+#define FIFO1_MAP GENMASK(3, 2)
+#define FIFO2_MAP GENMASK(5, 4)
+#define FIFO3_MAP GENMASK(7, 6)
+#define I2S_1ST_BIT_NOSHIFT BIT(8)
+#define I2S_DATA_DIR_LSB BIT(9)
+#define JUSTIFY_RIGHT BIT(10)
+#define WS_HIGH BIT(11)
+#define VBIT_COMPRESSED BIT(12)
+#define CBIT_ORDER_SAME BIT(13)
+#define SCK_EDGE_RISE BIT(14)
+#define AIP_I2S_CHST0 0x414
+#define AIP_I2S_CHST1 0x418
+#define AIP_TXCTRL 0x424
+#define RST4AUDIO BIT(0)
+#define RST4AUDIO_FIFO BIT(1)
+#define RST4AUDIO_ACR BIT(2)
+#define AUD_LAYOUT_1 BIT(4)
+#define AUD_MUTE_FIFO_EN BIT(5)
+#define AUD_PACKET_DROP BIT(6)
+#define DSD_MUTE_EN BIT(7)
+#define AIP_TPI_CTRL 0x428
+#define TPI_AUDIO_LOOKUP_EN BIT(2)
+
+/* Video downsampling configuration */
+#define VID_DOWNSAMPLE_CONFIG 0x8d0
+#define C444_C422_CONFIG_ENABLE BIT(0)
+#define C422_C420_CONFIG_ENABLE BIT(4)
+#define C422_C420_CONFIG_BYPASS BIT(5)
+#define C422_C420_CONFIG_OUT_CB_OR_CR BIT(6)
+#define VID_OUT_FORMAT 0x8fc
+#define OUTPUT_FORMAT_DEMUX_420_ENABLE BIT(10)
+
+/* HDCP registers */
+#define HDCP_TOP_CTRL 0xc00
+#define HDCP2X_CTRL_0 0xc20
+#define HDCP2X_EN BIT(0)
+#define HDCP2X_ENCRYPT_EN BIT(7)
+#define HDCP2X_HPD_OVR BIT(10)
+#define HDCP2X_HPD_SW BIT(11)
+#define HDCP2X_POL_CTRL 0xc54
+#define HDCP2X_DIS_POLL_EN BIT(16)
+#define HDCP1X_CTRL 0xcd0
+#define HDCP1X_ENC_EN BIT(6)
+
+/* HDMI DDC registers */
+#define HPD_DDC_CTRL 0xc08
+#define HPD_DDC_DELAY_CNT GENMASK(31, 16)
+#define HPD_DDC_HPD_DBNC_EN BIT(2)
+#define HPD_DDC_PORD_DBNC_EN BIT(3)
+#define DDC_CTRL 0xc10
+#define DDC_CTRL_ADDR GENMASK(7, 1)
+#define DDC_CTRL_OFFSET GENMASK(15, 8)
+#define DDC_CTRL_DIN_CNT GENMASK(25, 16)
+#define DDC_CTRL_CMD GENMASK(31, 28)
+#define SCDC_CTRL 0xc18
+#define SCDC_DDC_SEGMENT GENMASK(15, 8)
+#define HPD_DDC_STATUS 0xc60
+#define HPD_STATE GENMASK(1, 0)
+#define HPD_STATE_CONNECTED 2
+#define HPD_PIN_STA BIT(4)
+#define PORD_PIN_STA BIT(5)
+#define DDC_I2C_IN_PROG BIT(13)
+#define DDC_DATA_OUT GENMASK(23, 16)
+#define SI2C_CTRL 0xcac
+#define SI2C_WR BIT(0)
+#define SI2C_RD BIT(1)
+#define SI2C_CONFIRM_READ BIT(2)
+#define SI2C_WDATA GENMASK(15, 8)
+#define SI2C_ADDR GENMASK(23, 16)
+
+/* HDCP DDC registers */
+#define HDCP2X_DDCM_STATUS 0xc68
+#define DDC_I2C_NO_ACK BIT(10)
+#define DDC_I2C_BUS_LOW BIT(11)
+
+/* HDMI TX registers */
+#define HDMITX_CONFIG_MT8188 0xea0
+#define HDMITX_CONFIG_MT8195 0x900
+#define HDMI_YUV420_MODE BIT(10)
+#define HDMITX_SW_HPD BIT(29)
+#define HDMITX_SW_RSTB BIT(31)
+
+/**
+ * enum mtk_hdmi_ddc_v2_cmds - DDC_CMD register commands
+ * @DDC_CMD_READ_NOACK: Current address read with no ACK on last byte
+ * @DDC_CMD_READ: Current address read with ACK on last byte
+ * @DDC_CMD_SEQ_READ_NOACK: Sequential read with no ACK on last byte
+ * @DDC_CMD_SEQ_READ: Sequential read with ACK on last byte
+ * @DDC_CMD_ENH_READ_NOACK: Enhanced read with no ACK on last byte
+ * @DDC_CMD_ENH_READ: Enhanced read with ACK on last byte
+ * @DDC_CMD_SEQ_WRITE_NOACK: Sequential write ignoring ACK on last byte
+ * @DDC_CMD_SEQ_WRITE: Sequential write requiring ACK on last byte
+ * @DDC_CMD_RSVD: Reserved for future use
+ * @DDC_CMD_CLEAR_FIFO: Clear DDC I2C FIFO
+ * @DDC_CMD_CLOCK_SCL: Start clocking DDC I2C SCL
+ * @DDC_CMD_ABORT_XFER: Abort DDC I2C transaction
+ */
+enum mtk_hdmi_ddc_v2_cmds {
+ DDC_CMD_READ_NOACK = 0x0,
+ DDC_CMD_READ,
+ DDC_CMD_SEQ_READ_NOACK,
+ DDC_CMD_SEQ_READ,
+ DDC_CMD_ENH_READ_NOACK,
+ DDC_CMD_ENH_READ,
+ DDC_CMD_SEQ_WRITE_NOACK,
+ DDC_CMD_SEQ_WRITE = 0x07,
+ DDC_CMD_CLEAR_FIFO = 0x09,
+ DDC_CMD_CLOCK_SCL = 0x0a,
+ DDC_CMD_ABORT_XFER = 0x0f
+};
+
+#endif /* _MTK_HDMI_REGS_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
new file mode 100644
index 000000000000..4cf82b924124
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
@@ -0,0 +1,1352 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek HDMI v2 IP driver
+ *
+ * Copyright (c) 2022 MediaTek Inc.
+ * Copyright (c) 2022 BayLibre, SAS
+ * Copyright (c) 2024 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/suspend.h>
+#include <linux/units.h>
+#include <linux/phy/phy.h>
+
+#include <drm/display/drm_hdmi_helper.h>
+#include <drm/display/drm_hdmi_state_helper.h>
+#include <drm/display/drm_scdc_helper.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_print.h>
+#include <drm/drm_probe_helper.h>
+
+#include "mtk_hdmi_common.h"
+#include "mtk_hdmi_regs_v2.h"
+
+#define MTK_HDMI_V2_CLOCK_MIN 27000
+#define MTK_HDMI_V2_CLOCK_MAX 594000
+
+#define HPD_PORD_HWIRQS (HTPLG_R_INT | HTPLG_F_INT | PORD_F_INT | PORD_R_INT)
+
+enum mtk_hdmi_v2_clk_id {
+ MTK_HDMI_V2_CLK_HDCP_SEL,
+ MTK_HDMI_V2_CLK_HDCP_24M_SEL,
+ MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI,
+ MTK_HDMI_V2_CLK_HDMI_APB_SEL,
+ MTK_HDMI_V2_CLK_COUNT,
+};
+
+const char *const mtk_hdmi_v2_clk_names[MTK_HDMI_V2_CLK_COUNT] = {
+ [MTK_HDMI_V2_CLK_HDMI_APB_SEL] = "bus",
+ [MTK_HDMI_V2_CLK_HDCP_SEL] = "hdcp",
+ [MTK_HDMI_V2_CLK_HDCP_24M_SEL] = "hdcp24m",
+ [MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI] = "hdmi-split",
+};
+
+static inline void mtk_hdmi_v2_hwirq_disable(struct mtk_hdmi *hdmi)
+{
+ regmap_write(hdmi->regs, TOP_INT_ENABLE00, 0);
+ regmap_write(hdmi->regs, TOP_INT_ENABLE01, 0);
+}
+
+static inline void mtk_hdmi_v2_enable_hpd_pord_irq(struct mtk_hdmi *hdmi, bool enable)
+{
+ if (enable)
+ regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS);
+ else
+ regmap_clear_bits(hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS);
+}
+
+static inline void mtk_hdmi_v2_set_sw_hpd(struct mtk_hdmi *hdmi, bool enable)
+{
+ if (enable) {
+ regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD);
+ regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR);
+ regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW);
+ } else {
+ regmap_clear_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR);
+ regmap_clear_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW);
+ regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD);
+ }
+}
+
+static inline void mtk_hdmi_v2_enable_scrambling(struct mtk_hdmi *hdmi, bool enable)
+{
+ struct drm_scdc *scdc = &hdmi->curr_conn->display_info.hdmi.scdc;
+
+ if (enable)
+ regmap_set_bits(hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON);
+ else
+ regmap_clear_bits(hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON);
+
+ if (scdc->supported) {
+ if (scdc->scrambling.supported)
+ drm_scdc_set_scrambling(hdmi->curr_conn, enable);
+ drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, enable);
+ }
+}
+
+static void mtk_hdmi_v2_hw_vid_mute(struct mtk_hdmi *hdmi, bool enable)
+{
+ /* If enabled, sends a black image */
+ if (enable)
+ regmap_set_bits(hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN);
+ else
+ regmap_clear_bits(hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN);
+}
+
+static void mtk_hdmi_v2_hw_aud_mute(struct mtk_hdmi *hdmi, bool enable)
+{
+ u32 aip, val;
+
+ if (!enable) {
+ regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_MUTE_FIFO_EN);
+ return;
+ }
+
+ regmap_read(hdmi->regs, AIP_CTRL, &aip);
+
+ val = AUD_MUTE_FIFO_EN;
+ if (aip & DSD_EN)
+ val |= DSD_MUTE_EN;
+
+ regmap_update_bits(hdmi->regs, AIP_TXCTRL, val, val);
+}
+
+static void mtk_hdmi_v2_hw_reset(struct mtk_hdmi *hdmi)
+{
+ regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB);
+ udelay(5);
+ regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB);
+}
+
+static inline u32 mtk_hdmi_v2_format_hw_packet(const u8 *buffer, u8 len)
+{
+ unsigned short i;
+ u32 val = 0;
+
+ for (i = 0; i < len; i++)
+ val |= buffer[i] << (i * 8);
+
+ return val;
+}
+
+static void mtk_hdmi_v2_hw_write_audio_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer)
+{
+ regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR);
+ regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);
+
+ regmap_write(hdmi->regs, TOP_AIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3));
+ regmap_write(hdmi->regs, TOP_AIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 3));
+ regmap_write(hdmi->regs, TOP_AIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 2));
+ regmap_write(hdmi->regs, TOP_AIF_PKT02, 0);
+ regmap_write(hdmi->regs, TOP_AIF_PKT03, 0);
+
+ regmap_set_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);
+ regmap_set_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR);
+}
+
+static void mtk_hdmi_v2_hw_write_avi_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer)
+{
+ regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);
+ regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);
+
+ regmap_write(hdmi->regs, TOP_AVI_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3));
+ regmap_write(hdmi->regs, TOP_AVI_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4));
+ regmap_write(hdmi->regs, TOP_AVI_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 3));
+ regmap_write(hdmi->regs, TOP_AVI_PKT02, mtk_hdmi_v2_format_hw_packet(&buffer[10], 4));
+ regmap_write(hdmi->regs, TOP_AVI_PKT03, mtk_hdmi_v2_format_hw_packet(&buffer[14], 3));
+ regmap_write(hdmi->regs, TOP_AVI_PKT04, 0);
+ regmap_write(hdmi->regs, TOP_AVI_PKT05, 0);
+
+ regmap_set_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);
+ regmap_set_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);
+}
+
+static void mtk_hdmi_v2_hw_write_spd_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer)
+{
+ regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);
+ regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);
+
+ regmap_write(hdmi->regs, TOP_SPDIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3));
+ regmap_write(hdmi->regs, TOP_SPDIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4));
+ regmap_write(hdmi->regs, TOP_SPDIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 3));
+ regmap_write(hdmi->regs, TOP_SPDIF_PKT02, mtk_hdmi_v2_format_hw_packet(&buffer[10], 4));
+ regmap_write(hdmi->regs, TOP_SPDIF_PKT03, mtk_hdmi_v2_format_hw_packet(&buffer[14], 3));
+ regmap_write(hdmi->regs, TOP_SPDIF_PKT04, mtk_hdmi_v2_format_hw_packet(&buffer[17], 4));
+ regmap_write(hdmi->regs, TOP_SPDIF_PKT05, mtk_hdmi_v2_format_hw_packet(&buffer[21], 3));
+ regmap_write(hdmi->regs, TOP_SPDIF_PKT06, mtk_hdmi_v2_format_hw_packet(&buffer[24], 4));
+ regmap_write(hdmi->regs, TOP_SPDIF_PKT07, buffer[28]);
+
+ regmap_set_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);
+ regmap_set_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);
+}
+
+static void mtk_hdmi_v2_hw_write_vendor_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer)
+{
+ regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);
+ regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);
+
+ regmap_write(hdmi->regs, TOP_VSIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3));
+ regmap_write(hdmi->regs, TOP_VSIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4));
+ regmap_write(hdmi->regs, TOP_VSIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 2));
+ regmap_write(hdmi->regs, TOP_VSIF_PKT02, 0);
+ regmap_write(hdmi->regs, TOP_VSIF_PKT03, 0);
+ regmap_write(hdmi->regs, TOP_VSIF_PKT04, 0);
+ regmap_write(hdmi->regs, TOP_VSIF_PKT05, 0);
+ regmap_write(hdmi->regs, TOP_VSIF_PKT06, 0);
+ regmap_write(hdmi->regs, TOP_VSIF_PKT07, 0);
+
+ regmap_set_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);
+ regmap_set_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);
+}
+
+static void mtk_hdmi_yuv420_downsampling(struct mtk_hdmi *hdmi, bool enable)
+{
+ u32 val;
+
+ regmap_read(hdmi->regs, VID_DOWNSAMPLE_CONFIG, &val);
+
+ if (enable) {
+ regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMI_YUV420_MODE);
+
+ val |= C444_C422_CONFIG_ENABLE | C422_C420_CONFIG_ENABLE;
+ val |= C422_C420_CONFIG_OUT_CB_OR_CR;
+ val &= ~C422_C420_CONFIG_BYPASS;
+ regmap_write(hdmi->regs, VID_DOWNSAMPLE_CONFIG, val);
+
+ regmap_set_bits(hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENABLE);
+ } else {
+ regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMI_YUV420_MODE);
+
+ val &= ~(C444_C422_CONFIG_ENABLE | C422_C420_CONFIG_ENABLE);
+ val &= ~C422_C420_CONFIG_OUT_CB_OR_CR;
+ val |= C422_C420_CONFIG_BYPASS;
+ regmap_write(hdmi->regs, VID_DOWNSAMPLE_CONFIG, val);
+
+ regmap_clear_bits(hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENABLE);
+ }
+}
+
+static int mtk_hdmi_v2_setup_audio_infoframe(struct mtk_hdmi *hdmi)
+{
+ struct hdmi_codec_params *params = &hdmi->aud_param.codec_params;
+ struct hdmi_audio_infoframe frame;
+ u8 buffer[14];
+ ssize_t ret;
+
+ memcpy(&frame, ¶ms->cea, sizeof(frame));
+
+ ret = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
+ if (ret < 0)
+ return ret;
+
+ mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer);
+
+ return 0;
+}
+
+static inline void mtk_hdmi_v2_hw_reset_av_mute_regs(struct mtk_hdmi *hdmi)
+{
+ /* GCP packet */
+ regmap_clear_bits(hdmi->regs, TOP_CFG01, CP_CLR_MUTE_EN | CP_SET_MUTE_EN);
+ regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, CP_RPT_EN);
+ regmap_clear_bits(hdmi->regs, TOP_INFO_EN, CP_EN | CP_EN_WR);
+}
+
+static inline void mtk_hdmi_v2_hw_gcp_avmute(struct mtk_hdmi *hdmi, bool mute)
+{
+ mtk_hdmi_v2_hw_reset_av_mute_regs(hdmi);
+
+ if (mute)
+ regmap_set_bits(hdmi->regs, TOP_CFG01, CP_SET_MUTE_EN);
+ else
+ regmap_set_bits(hdmi->regs, TOP_CFG01, CP_CLR_MUTE_EN);
+
+ regmap_set_bits(hdmi->regs, TOP_INFO_RPT, CP_RPT_EN);
+ regmap_set_bits(hdmi->regs, TOP_INFO_EN, CP_EN | CP_EN_WR);
+}
+
+static void mtk_hdmi_v2_hw_ncts_enable(struct mtk_hdmi *hdmi, bool enable)
+{
+ if (enable)
+ regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL);
+ else
+ regmap_clear_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL);
+}
+
+static void mtk_hdmi_v2_hw_aud_set_channel_status(struct mtk_hdmi *hdmi)
+{
+ u8 *ch_status = hdmi->aud_param.codec_params.iec.status;
+
+ /* Only the first 5 to 7 bytes of Channel Status contain useful information */
+ regmap_write(hdmi->regs, AIP_I2S_CHST0, mtk_hdmi_v2_format_hw_packet(&ch_status[0], 4));
+ regmap_write(hdmi->regs, AIP_I2S_CHST1, mtk_hdmi_v2_format_hw_packet(&ch_status[4], 3));
+}
+
+static void mtk_hdmi_v2_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
+ unsigned int sample_rate,
+ unsigned int clock)
+{
+ unsigned int n, cts;
+
+ mtk_hdmi_get_ncts(sample_rate, clock, &n, &cts);
+
+ regmap_write(hdmi->regs, AIP_N_VAL, n);
+ regmap_write(hdmi->regs, AIP_CTS_SVAL, cts);
+}
+
+static void mtk_hdmi_v2_hw_aud_enable(struct mtk_hdmi *hdmi, bool enable)
+{
+ if (enable)
+ regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP);
+ else
+ regmap_set_bits(hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP);
+}
+
+static u32 mtk_hdmi_v2_aud_output_channel_map(u8 sd0, u8 sd1, u8 sd2, u8 sd3,
+ u8 sd4, u8 sd5, u8 sd6, u8 sd7)
+{
+ u32 val;
+
+ /*
+ * Each of the Output Channels (0-7) can be mapped to get their input
+ * from any of the available Input Channels (0-7): this function
+ * takes input channel numbers and formats a value that must then
+ * be written to the TOP_AUD_MAP hardware register by the caller.
+ */
+ val = FIELD_PREP(SD0_MAP, sd0) | FIELD_PREP(SD1_MAP, sd1);
+ val |= FIELD_PREP(SD2_MAP, sd2) | FIELD_PREP(SD3_MAP, sd3);
+ val |= FIELD_PREP(SD4_MAP, sd4) | FIELD_PREP(SD5_MAP, sd5);
+ val |= FIELD_PREP(SD6_MAP, sd6) | FIELD_PREP(SD7_MAP, sd7);
+
+ return val;
+}
+
+static void mtk_hdmi_audio_dsd_config(struct mtk_hdmi *hdmi,
+ unsigned char chnum, bool dsd_bypass)
+{
+ u32 channel_map;
+
+ regmap_update_bits(hdmi->regs, AIP_CTRL, SPDIF_EN | DSD_EN | HBRA_ON, DSD_EN);
+ regmap_set_bits(hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN);
+
+ if (dsd_bypass)
+ channel_map = mtk_hdmi_v2_aud_output_channel_map(0, 2, 4, 6, 1, 3, 5, 7);
+ else
+ channel_map = mtk_hdmi_v2_aud_output_channel_map(0, 5, 1, 0, 3, 2, 4, 0);
+
+ regmap_write(hdmi->regs, TOP_AUD_MAP, channel_map);
+ regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN);
+}
+
+static inline void mtk_hdmi_v2_hw_i2s_fifo_map(struct mtk_hdmi *hdmi, u32 fifo_mapping)
+{
+ regmap_update_bits(hdmi->regs, AIP_I2S_CTRL,
+ FIFO0_MAP | FIFO1_MAP | FIFO2_MAP | FIFO3_MAP, fifo_mapping);
+}
+
+static inline void mtk_hdmi_v2_hw_i2s_ch_number(struct mtk_hdmi *hdmi, u8 chnum)
+{
+ regmap_update_bits(hdmi->regs, AIP_CTRL, I2S_EN, FIELD_PREP(I2S_EN, chnum));
+}
+
+static void mtk_hdmi_v2_hw_i2s_ch_mapping(struct mtk_hdmi *hdmi, u8 chnum, u8 mapping)
+{
+ u32 fifo_map;
+ u8 bdata;
+
+ switch (chnum) {
+ default:
+ case 2:
+ bdata = 0x1;
+ break;
+ case 3:
+ bdata = 0x3;
+ break;
+ case 6:
+ if (mapping == 0x0e) {
+ bdata = 0xf;
+ break;
+ }
+ fallthrough;
+ case 5:
+ bdata = 0x7;
+ break;
+ case 7:
+ case 8:
+ bdata = 0xf;
+ break;
+ }
+
+ /* Assign default FIFO mapping: SD0 to FIFO0, SD1 to FIFO1, etc. */
+ fifo_map = FIELD_PREP(FIFO0_MAP, 0) | FIELD_PREP(FIFO1_MAP, 1);
+ fifo_map |= FIELD_PREP(FIFO2_MAP, 2) | FIELD_PREP(FIFO3_MAP, 3);
+ mtk_hdmi_v2_hw_i2s_fifo_map(hdmi, fifo_map);
+ mtk_hdmi_v2_hw_i2s_ch_number(hdmi, bdata);
+
+ /*
+ * Set HDMI Audio packet layout indicator:
+ * Layout 0 is for two channels
+ * Layout 1 is for up to eight channels
+ */
+ if (chnum == 2)
+ regmap_set_bits(hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1);
+ else
+ regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1);
+}
+
+static void mtk_hdmi_i2s_data_fmt(struct mtk_hdmi *hdmi, unsigned char fmt)
+{
+ u32 val;
+
+ regmap_read(hdmi->regs, AIP_I2S_CTRL, &val);
+ val &= ~(WS_HIGH | I2S_1ST_BIT_NOSHIFT | JUSTIFY_RIGHT);
+
+ switch (fmt) {
+ case HDMI_I2S_MODE_RJT_24BIT:
+ case HDMI_I2S_MODE_RJT_16BIT:
+ val |= (WS_HIGH | I2S_1ST_BIT_NOSHIFT | JUSTIFY_RIGHT);
+ break;
+ case HDMI_I2S_MODE_LJT_24BIT:
+ case HDMI_I2S_MODE_LJT_16BIT:
+ val |= (WS_HIGH | I2S_1ST_BIT_NOSHIFT);
+ break;
+ case HDMI_I2S_MODE_I2S_24BIT:
+ case HDMI_I2S_MODE_I2S_16BIT:
+ default:
+ break;
+ }
+
+ regmap_write(hdmi->regs, AIP_I2S_CTRL, val);
+}
+
+static inline void mtk_hdmi_i2s_sck_edge_rise(struct mtk_hdmi *hdmi, bool rise)
+{
+ if (rise)
+ regmap_set_bits(hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE);
+ else
+ regmap_clear_bits(hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE);
+}
+
+static inline void mtk_hdmi_i2s_cbit_order(struct mtk_hdmi *hdmi, unsigned int cbit)
+{
+ regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, CBIT_ORDER_SAME, cbit);
+}
+
+static inline void mtk_hdmi_i2s_vbit(struct mtk_hdmi *hdmi, unsigned int vbit)
+{
+ /* V bit: 0 for PCM, 1 for Compressed data */
+ regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, VBIT_COMPRESSED, vbit);
+}
+
+static inline void mtk_hdmi_i2s_data_direction(struct mtk_hdmi *hdmi, unsigned int is_lsb)
+{
+ regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, I2S_DATA_DIR_LSB, is_lsb);
+}
+
+static inline void mtk_hdmi_v2_hw_audio_type(struct mtk_hdmi *hdmi, unsigned int spdif_i2s)
+{
+ regmap_update_bits(hdmi->regs, AIP_CTRL, SPDIF_EN, FIELD_PREP(SPDIF_EN, spdif_i2s));
+}
+
+static u8 mtk_hdmi_v2_get_i2s_ch_mapping(struct mtk_hdmi *hdmi, u8 channel_type)
+{
+ switch (channel_type) {
+ case HDMI_AUD_CHAN_TYPE_1_1:
+ case HDMI_AUD_CHAN_TYPE_2_1:
+ return 0x01;
+ case HDMI_AUD_CHAN_TYPE_3_0:
+ return 0x02;
+ case HDMI_AUD_CHAN_TYPE_3_1:
+ return 0x03;
+ case HDMI_AUD_CHAN_TYPE_3_0_LRS:
+ case HDMI_AUD_CHAN_TYPE_4_0:
+ return 0x08;
+ case HDMI_AUD_CHAN_TYPE_5_1:
+ return 0x0b;
+ case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
+ case HDMI_AUD_CHAN_TYPE_6_0:
+ case HDMI_AUD_CHAN_TYPE_6_0_CS:
+ case HDMI_AUD_CHAN_TYPE_6_0_CH:
+ case HDMI_AUD_CHAN_TYPE_6_0_OH:
+ case HDMI_AUD_CHAN_TYPE_6_0_CHR:
+ return 0x0e;
+ case HDMI_AUD_CHAN_TYPE_1_0:
+ case HDMI_AUD_CHAN_TYPE_2_0:
+ case HDMI_AUD_CHAN_TYPE_3_1_LRS:
+ case HDMI_AUD_CHAN_TYPE_4_1:
+ case HDMI_AUD_CHAN_TYPE_5_0:
+ case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
+ case HDMI_AUD_CHAN_TYPE_6_1:
+ case HDMI_AUD_CHAN_TYPE_6_1_CS:
+ case HDMI_AUD_CHAN_TYPE_6_1_CH:
+ case HDMI_AUD_CHAN_TYPE_6_1_OH:
+ case HDMI_AUD_CHAN_TYPE_6_1_CHR:
+ case HDMI_AUD_CHAN_TYPE_7_0:
+ case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
+ case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
+ case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
+ case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
+ case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
+ case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
+ case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
+ case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
+ case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
+ case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
+ case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
+ case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
+ case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
+ case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
+ case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
+ case HDMI_AUD_CHAN_TYPE_7_1:
+ case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
+ case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
+ case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
+ case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
+ case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
+ case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
+ case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
+ case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
+ case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
+ case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
+ case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
+ case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
+ case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
+ case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static inline void mtk_hdmi_v2_hw_i2s_ch_swap(struct mtk_hdmi *hdmi)
+{
+ regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_I2S_HI_WRITE,
+ FIELD_PREP(MAX_2UI_I2S_HI_WRITE, MAX_2UI_I2S_LFE_CC_SWAP));
+}
+
+static void mtk_hdmi_hbr_config(struct mtk_hdmi *hdmi, bool dsd_bypass)
+{
+ const u32 hbr_mask = SPDIF_EN | DSD_EN | HBRA_ON;
+
+ if (dsd_bypass) {
+ regmap_update_bits(hdmi->regs, AIP_CTRL, hbr_mask, HBRA_ON);
+ regmap_set_bits(hdmi->regs, AIP_CTRL, I2S_EN);
+ } else {
+ regmap_update_bits(hdmi->regs, AIP_CTRL, hbr_mask, SPDIF_EN);
+ regmap_set_bits(hdmi->regs, AIP_CTRL, SPDIF_INTERNAL_MODULE);
+ regmap_set_bits(hdmi->regs, AIP_CTRL, HBR_FROM_SPDIF);
+ regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_CAL_N4);
+ }
+}
+
+static inline void mtk_hdmi_v2_hw_spdif_config(struct mtk_hdmi *hdmi)
+{
+ regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, WR_1UI_LOCK);
+ regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, FS_OVERRIDE_WRITE);
+ regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, WR_2UI_LOCK);
+
+ regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_1UI_WRITE,
+ FIELD_PREP(MAX_1UI_WRITE, 4));
+ regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_SPDIF_WRITE,
+ FIELD_PREP(MAX_2UI_SPDIF_WRITE, 9));
+ regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, AUD_ERR_THRESH,
+ FIELD_PREP(AUD_ERR_THRESH, 4));
+
+ regmap_set_bits(hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN);
+}
+
+static void mtk_hdmi_v2_aud_set_input(struct mtk_hdmi *hdmi)
+{
+ struct hdmi_audio_param *aud_param = &hdmi->aud_param;
+ struct hdmi_codec_params *codec_params = &aud_param->codec_params;
+ u8 i2s_ch_map;
+ u32 out_ch_map;
+
+ /* Write the default output channel map. CH0 maps to SD0, CH1 maps to SD1, etc */
+ out_ch_map = mtk_hdmi_v2_aud_output_channel_map(0, 1, 2, 3, 4, 5, 6, 7);
+ regmap_write(hdmi->regs, TOP_AUD_MAP, out_ch_map);
+
+ regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_I2S_HI_WRITE, 0);
+ regmap_clear_bits(hdmi->regs, AIP_CTRL,
+ SPDIF_EN | DSD_EN | HBRA_ON | CTS_CAL_N4 |
+ HBR_FROM_SPDIF | SPDIF_INTERNAL_MODULE);
+ regmap_clear_bits(hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN | AUD_LAYOUT_1);
+
+ if (aud_param->aud_input_type == HDMI_AUD_INPUT_I2S) {
+ switch (aud_param->aud_codec) {
+ case HDMI_AUDIO_CODING_TYPE_DTS_HD:
+ case HDMI_AUDIO_CODING_TYPE_MLP:
+ mtk_hdmi_i2s_data_fmt(hdmi, aud_param->aud_i2s_fmt);
+ mtk_hdmi_hbr_config(hdmi, true);
+ break;
+ case HDMI_AUDIO_CODING_TYPE_DSD:
+ mtk_hdmi_audio_dsd_config(hdmi, codec_params->channels, 0);
+ mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, codec_params->channels, 1);
+ break;
+ default:
+ mtk_hdmi_i2s_data_fmt(hdmi, aud_param->aud_i2s_fmt);
+ mtk_hdmi_i2s_sck_edge_rise(hdmi, true);
+ mtk_hdmi_i2s_cbit_order(hdmi, CBIT_ORDER_SAME);
+ mtk_hdmi_i2s_vbit(hdmi, 0); /* PCM data */
+ mtk_hdmi_i2s_data_direction(hdmi, 0); /* MSB first */
+ mtk_hdmi_v2_hw_audio_type(hdmi, HDMI_AUD_INPUT_I2S);
+ i2s_ch_map = mtk_hdmi_v2_get_i2s_ch_mapping(hdmi,
+ aud_param->aud_input_chan_type);
+ mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, codec_params->channels, i2s_ch_map);
+ mtk_hdmi_v2_hw_i2s_ch_swap(hdmi);
+ }
+ } else {
+ if (codec_params->sample_rate == 768000 &&
+ (aud_param->aud_codec == HDMI_AUDIO_CODING_TYPE_DTS_HD ||
+ aud_param->aud_codec == HDMI_AUDIO_CODING_TYPE_MLP)) {
+ mtk_hdmi_hbr_config(hdmi, false);
+ } else {
+ mtk_hdmi_v2_hw_spdif_config(hdmi);
+ mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, 2, 0);
+ }
+ }
+}
+
+static inline void mtk_hdmi_v2_hw_audio_input_enable(struct mtk_hdmi *hdmi, bool ena)
+{
+ if (ena)
+ regmap_set_bits(hdmi->regs, AIP_CTRL, AUD_IN_EN);
+ else
+ regmap_clear_bits(hdmi->regs, AIP_CTRL, AUD_IN_EN);
+}
+
+static void mtk_hdmi_v2_aip_ctrl_init(struct mtk_hdmi *hdmi)
+{
+ regmap_set_bits(hdmi->regs, AIP_CTRL,
+ AUD_SEL_OWRT | NO_MCLK_CTSGEN_SEL | MCLK_EN | CTS_REQ_EN);
+ regmap_clear_bits(hdmi->regs, AIP_TPI_CTRL, TPI_AUDIO_LOOKUP_EN);
+}
+
+static void mtk_hdmi_v2_audio_reset(struct mtk_hdmi *hdmi, bool reset)
+{
+ const u32 arst_bits = RST4AUDIO | RST4AUDIO_FIFO | RST4AUDIO_ACR;
+
+ if (reset)
+ regmap_set_bits(hdmi->regs, AIP_TXCTRL, arst_bits);
+ else
+ regmap_clear_bits(hdmi->regs, AIP_TXCTRL, arst_bits);
+}
+
+static void mtk_hdmi_v2_aud_output_config(struct mtk_hdmi *hdmi,
+ struct drm_display_mode *display_mode)
+{
+ /* Shut down and reset the HDMI Audio HW to avoid glitching */
+ mtk_hdmi_v2_hw_aud_mute(hdmi, true);
+ mtk_hdmi_v2_hw_aud_enable(hdmi, false);
+ mtk_hdmi_v2_audio_reset(hdmi, true);
+
+ /* Configure the main hardware params and get out of reset */
+ mtk_hdmi_v2_aip_ctrl_init(hdmi);
+ mtk_hdmi_v2_aud_set_input(hdmi);
+ mtk_hdmi_v2_hw_aud_set_channel_status(hdmi);
+ mtk_hdmi_v2_setup_audio_infoframe(hdmi);
+ mtk_hdmi_v2_hw_audio_input_enable(hdmi, true);
+ mtk_hdmi_v2_audio_reset(hdmi, false);
+
+ /* Ignore N/CTS packet transmission requests and configure */
+ mtk_hdmi_v2_hw_ncts_enable(hdmi, false);
+ mtk_hdmi_v2_hw_aud_set_ncts(hdmi, hdmi->aud_param.codec_params.sample_rate,
+ display_mode->clock);
+
+ /* Wait for the HW to apply settings */
+ usleep_range(25, 50);
+
+ /* Hardware is fully configured: enable TX of N/CTS pkts and unmute */
+ mtk_hdmi_v2_hw_ncts_enable(hdmi, true);
+ mtk_hdmi_v2_hw_aud_enable(hdmi, true);
+ mtk_hdmi_v2_hw_aud_mute(hdmi, false);
+}
+
+static void mtk_hdmi_v2_change_video_resolution(struct mtk_hdmi *hdmi)
+{
+ mtk_hdmi_v2_hw_reset(hdmi);
+ mtk_hdmi_v2_set_sw_hpd(hdmi, true);
+ udelay(2);
+
+ regmap_write(hdmi->regs, HDCP_TOP_CTRL, 0);
+
+ /* Enable HDCP reauthentication interrupt */
+ regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HDCP2X_RX_REAUTH_REQ_DDCM_INT);
+
+ /* Enable hotplug and pord interrupts */
+ mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true);
+
+ /* Force enabling HDCP HPD */
+ regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR);
+ regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW);
+
+ /* Set 8 bits per pixel */
+ regmap_update_bits(hdmi->regs, TOP_CFG00, TMDS_PACK_MODE,
+ FIELD_PREP(TMDS_PACK_MODE, TMDS_PACK_MODE_8BPP));
+ /* Disable generating deepcolor packets */
+ regmap_clear_bits(hdmi->regs, TOP_CFG00, DEEPCOLOR_PKT_EN);
+ /* Disable adding deepcolor information to the general packet */
+ regmap_clear_bits(hdmi->regs, TOP_MISC_CTLR, DEEP_COLOR_ADD);
+
+ if (hdmi->curr_conn->display_info.is_hdmi)
+ regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI);
+ else
+ regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI);
+
+ udelay(5);
+ mtk_hdmi_v2_hw_vid_mute(hdmi, true);
+ mtk_hdmi_v2_hw_aud_mute(hdmi, true);
+ mtk_hdmi_v2_hw_gcp_avmute(hdmi, false);
+
+ regmap_update_bits(hdmi->regs, TOP_CFG01,
+ NULL_PKT_VSYNC_HIGH_EN | NULL_PKT_EN, NULL_PKT_VSYNC_HIGH_EN);
+ usleep_range(100, 150);
+
+ /* Enable scrambling if tmds clock is 340MHz or more */
+ mtk_hdmi_v2_enable_scrambling(hdmi, hdmi->mode.clock >= 340 * KILO);
+
+ /* Disable YUV420 downsampling */
+ mtk_hdmi_yuv420_downsampling(hdmi, false);
+}
+
+static void mtk_hdmi_v2_output_set_display_mode(struct mtk_hdmi *hdmi,
+ struct drm_display_mode *mode)
+{
+ union phy_configure_opts opts = {
+ .dp = { .link_rate = hdmi->mode.clock * KILO }
+ };
+ int ret;
+
+ ret = phy_configure(hdmi->phy, &opts);
+ if (ret)
+ dev_err(hdmi->dev, "Setting clock=%d failed: %d", mode->clock, ret);
+
+ mtk_hdmi_v2_change_video_resolution(hdmi);
+ mtk_hdmi_v2_aud_output_config(hdmi, mode);
+}
+
+static int mtk_hdmi_v2_clk_enable(struct mtk_hdmi *hdmi)
+{
+ int ret;
+
+ ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]);
+ if (ret)
+ goto disable_hdcp_clk;
+
+ ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]);
+ if (ret)
+ goto disable_hdcp_24m_clk;
+
+ ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI]);
+ if (ret)
+ goto disable_bus_clk;
+
+ return 0;
+
+disable_bus_clk:
+ clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]);
+disable_hdcp_24m_clk:
+ clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]);
+disable_hdcp_clk:
+ clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]);
+
+ return ret;
+}
+
+static void mtk_hdmi_v2_clk_disable(struct mtk_hdmi *hdmi)
+{
+ clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI]);
+ clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]);
+ clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]);
+ clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]);
+}
+
+static void mtk_hdmi_hpd_event(enum hdmi_hpd_state hpd, struct device *dev)
+{
+ struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+
+ if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev)
+ drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
+}
+
+static enum hdmi_hpd_state mtk_hdmi_v2_hpd_pord_status(struct mtk_hdmi *hdmi)
+{
+ u8 hpd_pin_sta, pord_pin_sta;
+ u32 hpd_status;
+
+ regmap_read(hdmi->regs, HPD_DDC_STATUS, &hpd_status);
+ hpd_pin_sta = FIELD_GET(HPD_PIN_STA, hpd_status);
+ pord_pin_sta = FIELD_GET(PORD_PIN_STA, hpd_status);
+
+ if (hpd_pin_sta && pord_pin_sta)
+ return HDMI_PLUG_IN_AND_SINK_POWER_ON;
+ else if (hpd_pin_sta)
+ return HDMI_PLUG_IN_ONLY;
+ else
+ return HDMI_PLUG_OUT;
+}
+
+static irqreturn_t mtk_hdmi_v2_isr(int irq, void *arg)
+{
+ struct mtk_hdmi *hdmi = arg;
+ unsigned int irq_sta;
+ int ret = IRQ_HANDLED;
+
+ regmap_read(hdmi->regs, TOP_INT_STA00, &irq_sta);
+
+ /* Handle Hotplug Detection interrupt */
+ if (irq_sta & (HTPLG_R_INT | HTPLG_F_INT | PORD_F_INT | PORD_R_INT)) {
+ mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, false);
+ ret = IRQ_WAKE_THREAD;
+ }
+
+ /*
+ * Clear all 32 + 19 interrupts in CLR00 and CLR01: this is important
+ * to avoid unwanted retriggering of any interrupts
+ */
+ regmap_write(hdmi->regs, TOP_INT_CLR00, GENMASK(31, 0));
+ regmap_write(hdmi->regs, TOP_INT_CLR01, GENMASK(18, 0));
+
+ /* Restore interrupt clearing registers to zero */
+ regmap_write(hdmi->regs, TOP_INT_CLR00, 0);
+ regmap_write(hdmi->regs, TOP_INT_CLR01, 0);
+
+ return ret;
+}
+
+static irqreturn_t __mtk_hdmi_v2_isr_thread(struct mtk_hdmi *hdmi)
+{
+ enum hdmi_hpd_state hpd;
+
+ hpd = mtk_hdmi_v2_hpd_pord_status(hdmi);
+ if (hpd != hdmi->hpd) {
+ hdmi->hpd = hpd;
+ mtk_hdmi_hpd_event(hpd, hdmi->dev);
+ }
+
+ mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true);
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t mtk_hdmi_v2_isr_thread(int irq, void *arg)
+{
+ struct mtk_hdmi *hdmi = arg;
+
+ /*
+ * Debounce HDMI monitor HPD status.
+ * Empirical testing shows that 30ms is enough wait
+ */
+ msleep(30);
+
+ return __mtk_hdmi_v2_isr_thread(hdmi);
+}
+
+static int mtk_hdmi_v2_enable(struct mtk_hdmi *hdmi)
+{
+ bool was_active = pm_runtime_active(hdmi->dev);
+ int ret;
+
+ ret = pm_runtime_resume_and_get(hdmi->dev);
+ if (ret) {
+ dev_err(hdmi->dev, "Cannot resume HDMI\n");
+ return ret;
+ }
+
+ ret = mtk_hdmi_v2_clk_enable(hdmi);
+ if (ret) {
+ pm_runtime_put(hdmi->dev);
+ return ret;
+ }
+
+ if (!was_active) {
+ mtk_hdmi_v2_hw_reset(hdmi);
+ mtk_hdmi_v2_set_sw_hpd(hdmi, true);
+ }
+
+ return 0;
+}
+
+static void mtk_hdmi_v2_disable(struct mtk_hdmi *hdmi)
+{
+ mtk_hdmi_v2_clk_disable(hdmi);
+ pm_runtime_put_sync(hdmi->dev);
+}
+
+/*
+ * Bridge callbacks
+ */
+
+static int mtk_hdmi_v2_bridge_attach(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+{
+ struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+ int ret;
+
+ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+ DRM_ERROR("The flag DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied\n");
+ return -EINVAL;
+ }
+ if (hdmi->next_bridge) {
+ ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, bridge, flags);
+ if (ret)
+ return ret;
+ }
+
+ ret = mtk_hdmi_v2_enable(hdmi);
+ if (ret)
+ return ret;
+
+ /* Enable Hotplug and Pord pins internal debouncing */
+ regmap_set_bits(hdmi->regs, HPD_DDC_CTRL,
+ HPD_DDC_HPD_DBNC_EN | HPD_DDC_PORD_DBNC_EN);
+
+ irq_clear_status_flags(hdmi->irq, IRQ_NOAUTOEN);
+ enable_irq(hdmi->irq);
+
+ /*
+ * Check if any HDMI monitor was connected before probing this driver
+ * and/or attaching the bridge, without debouncing: if so, we want to
+ * notify the DRM so that we start outputting an image ASAP.
+ * Note that calling the ISR thread function will also perform a HW
+ * registers write that enables both the HPD and Pord interrupts.
+ */
+ __mtk_hdmi_v2_isr_thread(hdmi);
+
+ mtk_hdmi_v2_disable(hdmi);
+
+ return 0;
+}
+
+static void mtk_hdmi_v2_bridge_detach(struct drm_bridge *bridge)
+{
+ struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+
+ WARN_ON(pm_runtime_active(hdmi->dev));
+
+ /* The controller is already powered off, just disable irq here */
+ disable_irq(hdmi->irq);
+}
+
+static void mtk_hdmi_v2_handle_plugged_change(struct mtk_hdmi *hdmi, bool plugged)
+{
+ mutex_lock(&hdmi->update_plugged_status_lock);
+ if (hdmi->plugged_cb && hdmi->codec_dev)
+ hdmi->plugged_cb(hdmi->codec_dev, plugged);
+ mutex_unlock(&hdmi->update_plugged_status_lock);
+}
+
+static void mtk_hdmi_v2_bridge_pre_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_state)
+{
+ struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+ struct drm_atomic_state *state = old_state->base.state;
+ struct drm_connector_state *conn_state;
+ union phy_configure_opts opts = {
+ .dp = { .link_rate = hdmi->mode.clock * KILO }
+ };
+ int ret;
+
+ /* Power on the controller before trying to write to registers */
+ ret = mtk_hdmi_v2_enable(hdmi);
+ if (WARN_ON(ret))
+ return;
+
+ /* Retrieve the connector through the atomic state */
+ hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
+
+ conn_state = drm_atomic_get_new_connector_state(state, hdmi->curr_conn);
+ if (WARN_ON(!conn_state))
+ return;
+
+ /*
+ * Preconfigure the HDMI controller and the HDMI PHY at pre_enable
+ * stage to make sure that this IP is ready and clocked before the
+ * mtk_dpi gets powered on and before it enables the output.
+ */
+ mtk_hdmi_v2_output_set_display_mode(hdmi, &hdmi->mode);
+
+ /* Reconfigure phy clock link with appropriate rate */
+ phy_configure(hdmi->phy, &opts);
+
+ /* Power on the PHY here to make sure that DPI_HDMI is clocked */
+ phy_power_on(hdmi->phy);
+
+ hdmi->powered = true;
+}
+
+static void mtk_hdmi_v2_bridge_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_state)
+{
+ struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+ struct drm_atomic_state *state = old_state->base.state;
+ int ret;
+
+ if (WARN_ON(!hdmi->powered))
+ return;
+
+ ret = drm_atomic_helper_connector_hdmi_update_infoframes(hdmi->curr_conn, state);
+ if (ret)
+ dev_err(hdmi->dev, "Could not update infoframes: %d\n", ret);
+
+ mtk_hdmi_v2_hw_vid_mute(hdmi, false);
+
+ /* signal the connect event to audio codec */
+ mtk_hdmi_v2_handle_plugged_change(hdmi, true);
+
+ hdmi->enabled = true;
+}
+
+static void mtk_hdmi_v2_bridge_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+
+ if (!hdmi->enabled)
+ return;
+
+ mtk_hdmi_v2_hw_gcp_avmute(hdmi, true);
+ msleep(50);
+ mtk_hdmi_v2_hw_vid_mute(hdmi, true);
+ mtk_hdmi_v2_hw_aud_mute(hdmi, true);
+ msleep(50);
+
+ hdmi->enabled = false;
+}
+
+static void mtk_hdmi_v2_bridge_post_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_state)
+{
+ struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+
+ if (!hdmi->powered)
+ return;
+
+ phy_power_off(hdmi->phy);
+ hdmi->powered = false;
+
+ /* signal the disconnect event to audio codec */
+ mtk_hdmi_v2_handle_plugged_change(hdmi, false);
+
+ /* Power off */
+ mtk_hdmi_v2_disable(hdmi);
+}
+
+static enum drm_connector_status mtk_hdmi_v2_bridge_detect(struct drm_bridge *bridge)
+{
+ struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+
+ return hdmi->hpd != HDMI_PLUG_OUT ?
+ connector_status_connected : connector_status_disconnected;
+}
+
+static const struct drm_edid *mtk_hdmi_v2_bridge_edid_read(struct drm_bridge *bridge,
+ struct drm_connector *connector)
+{
+ return drm_edid_read(connector);
+}
+
+static void mtk_hdmi_v2_hpd_enable(struct drm_bridge *bridge)
+{
+ struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+ int ret;
+
+ ret = mtk_hdmi_v2_enable(hdmi);
+ if (ret) {
+ dev_err(hdmi->dev, "Cannot power on controller for HPD: %d\n", ret);
+ return;
+ }
+
+ mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true);
+}
+
+static void mtk_hdmi_v2_hpd_disable(struct drm_bridge *bridge)
+{
+ struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+
+ mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, false);
+ mtk_hdmi_v2_disable(hdmi);
+}
+
+static int mtk_hdmi_v2_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ unsigned long long tmds_rate)
+{
+ if (mode->clock < MTK_HDMI_V2_CLOCK_MIN)
+ return MODE_CLOCK_LOW;
+ else if (mode->clock > MTK_HDMI_V2_CLOCK_MAX)
+ return MODE_CLOCK_HIGH;
+ else
+ return MODE_OK;
+}
+
+static int mtk_hdmi_v2_hdmi_clear_infoframe(struct drm_bridge *bridge,
+ enum hdmi_infoframe_type type)
+{
+ struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+
+ switch (type) {
+ case HDMI_INFOFRAME_TYPE_AUDIO:
+ regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN_WR | AUD_EN);
+ regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);
+ break;
+ case HDMI_INFOFRAME_TYPE_AVI:
+ regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);
+ regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);
+ break;
+ case HDMI_INFOFRAME_TYPE_SPD:
+ regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);
+ regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);
+ break;
+ case HDMI_INFOFRAME_TYPE_VENDOR:
+ regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);
+ regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);
+ break;
+ case HDMI_INFOFRAME_TYPE_DRM:
+ default:
+ break;
+ };
+
+ return 0;
+}
+
+static int mtk_hdmi_v2_hdmi_write_infoframe(struct drm_bridge *bridge,
+ enum hdmi_infoframe_type type,
+ const u8 *buffer, size_t len)
+{
+ struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+
+ switch (type) {
+ case HDMI_INFOFRAME_TYPE_AUDIO:
+ mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer);
+ break;
+ case HDMI_INFOFRAME_TYPE_AVI:
+ mtk_hdmi_v2_hw_write_avi_infoframe(hdmi, buffer);
+ break;
+ case HDMI_INFOFRAME_TYPE_SPD:
+ mtk_hdmi_v2_hw_write_spd_infoframe(hdmi, buffer);
+ break;
+ case HDMI_INFOFRAME_TYPE_VENDOR:
+ mtk_hdmi_v2_hw_write_vendor_infoframe(hdmi, buffer);
+ break;
+ case HDMI_INFOFRAME_TYPE_DRM:
+ default:
+ dev_err(hdmi->dev, "Unsupported HDMI infoframe type %u\n", type);
+ break;
+ };
+
+ return 0;
+}
+
+static const struct drm_bridge_funcs mtk_v2_hdmi_bridge_funcs = {
+ .attach = mtk_hdmi_v2_bridge_attach,
+ .detach = mtk_hdmi_v2_bridge_detach,
+ .mode_fixup = mtk_hdmi_bridge_mode_fixup,
+ .mode_set = mtk_hdmi_bridge_mode_set,
+ .atomic_pre_enable = mtk_hdmi_v2_bridge_pre_enable,
+ .atomic_enable = mtk_hdmi_v2_bridge_enable,
+ .atomic_disable = mtk_hdmi_v2_bridge_disable,
+ .atomic_post_disable = mtk_hdmi_v2_bridge_post_disable,
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .detect = mtk_hdmi_v2_bridge_detect,
+ .edid_read = mtk_hdmi_v2_bridge_edid_read,
+ .hpd_enable = mtk_hdmi_v2_hpd_enable,
+ .hpd_disable = mtk_hdmi_v2_hpd_disable,
+ .hdmi_tmds_char_rate_valid = mtk_hdmi_v2_hdmi_tmds_char_rate_valid,
+ .hdmi_clear_infoframe = mtk_hdmi_v2_hdmi_clear_infoframe,
+ .hdmi_write_infoframe = mtk_hdmi_v2_hdmi_write_infoframe,
+};
+
+/*
+ * HDMI audio codec callbacks
+ */
+static int mtk_hdmi_v2_audio_hook_plugged_cb(struct device *dev, void *data,
+ hdmi_codec_plugged_cb fn,
+ struct device *codec_dev)
+{
+ struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+ bool plugged;
+
+ if (!hdmi)
+ return -ENODEV;
+
+ mtk_hdmi_audio_set_plugged_cb(hdmi, fn, codec_dev);
+ plugged = (hdmi->hpd == HDMI_PLUG_IN_AND_SINK_POWER_ON);
+ mtk_hdmi_v2_handle_plugged_change(hdmi, plugged);
+
+ return 0;
+}
+
+static int mtk_hdmi_v2_audio_hw_params(struct device *dev, void *data,
+ struct hdmi_codec_daifmt *daifmt,
+ struct hdmi_codec_params *params)
+{
+ struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+
+ if (hdmi->audio_enable) {
+ mtk_hdmi_audio_params(hdmi, daifmt, params);
+ mtk_hdmi_v2_aud_output_config(hdmi, &hdmi->mode);
+ }
+ return 0;
+}
+
+static int mtk_hdmi_v2_audio_startup(struct device *dev, void *data)
+{
+ struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+
+ mtk_hdmi_v2_hw_aud_enable(hdmi, true);
+ hdmi->audio_enable = true;
+
+ return 0;
+}
+
+static void mtk_hdmi_v2_audio_shutdown(struct device *dev, void *data)
+{
+ struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+
+ hdmi->audio_enable = false;
+ mtk_hdmi_v2_hw_aud_enable(hdmi, false);
+}
+
+static int mtk_hdmi_v2_audio_mute(struct device *dev, void *data, bool enable, int dir)
+{
+ struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+
+ mtk_hdmi_v2_hw_aud_mute(hdmi, enable);
+
+ return 0;
+}
+
+static const struct hdmi_codec_ops mtk_hdmi_v2_audio_codec_ops = {
+ .hw_params = mtk_hdmi_v2_audio_hw_params,
+ .audio_startup = mtk_hdmi_v2_audio_startup,
+ .audio_shutdown = mtk_hdmi_v2_audio_shutdown,
+ .mute_stream = mtk_hdmi_v2_audio_mute,
+ .get_eld = mtk_hdmi_audio_get_eld,
+ .hook_plugged_cb = mtk_hdmi_v2_audio_hook_plugged_cb,
+};
+
+static __maybe_unused int mtk_hdmi_v2_suspend(struct device *dev)
+{
+ struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+
+ mtk_hdmi_v2_disable(hdmi);
+
+ return 0;
+}
+
+static __maybe_unused int mtk_hdmi_v2_resume(struct device *dev)
+{
+ struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+
+ return mtk_hdmi_v2_enable(hdmi);
+}
+
+static SIMPLE_DEV_PM_OPS(mtk_hdmi_v2_pm_ops, mtk_hdmi_v2_suspend, mtk_hdmi_v2_resume);
+
+static const struct mtk_hdmi_ver_conf mtk_hdmi_conf_v2 = {
+ .bridge_funcs = &mtk_v2_hdmi_bridge_funcs,
+ .codec_ops = &mtk_hdmi_v2_audio_codec_ops,
+ .mtk_hdmi_clock_names = mtk_hdmi_v2_clk_names,
+ .num_clocks = MTK_HDMI_V2_CLK_COUNT,
+ .interlace_allowed = true,
+};
+
+static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8188 = {
+ .ver_conf = &mtk_hdmi_conf_v2,
+ .reg_hdmi_tx_cfg = HDMITX_CONFIG_MT8188
+};
+
+static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8195 = {
+ .ver_conf = &mtk_hdmi_conf_v2,
+ .reg_hdmi_tx_cfg = HDMITX_CONFIG_MT8195
+};
+
+static int mtk_hdmi_v2_probe(struct platform_device *pdev)
+{
+ struct mtk_hdmi *hdmi;
+ int ret;
+
+ /* Populate HDMI sub-devices if present */
+ ret = devm_of_platform_populate(&pdev->dev);
+ if (ret)
+ return ret;
+
+ hdmi = mtk_hdmi_common_probe(pdev);
+ if (IS_ERR(hdmi))
+ return PTR_ERR(hdmi);
+
+ hdmi->hpd = HDMI_PLUG_OUT;
+
+ /*
+ * Disable all HW interrupts at probe stage and install the ISR
+ * but keep it disabled, as the rest of the interrupts setup is
+ * done in the .bridge_attach() callback, which will enable both
+ * the right HW IRQs and the ISR.
+ */
+ mtk_hdmi_v2_hwirq_disable(hdmi);
+ irq_set_status_flags(hdmi->irq, IRQ_NOAUTOEN);
+ ret = devm_request_threaded_irq(&pdev->dev, hdmi->irq, mtk_hdmi_v2_isr,
+ mtk_hdmi_v2_isr_thread,
+ IRQ_TYPE_LEVEL_HIGH,
+ dev_name(&pdev->dev), hdmi);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "Cannot request IRQ\n");
+
+ ret = devm_pm_runtime_enable(&pdev->dev);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "Cannot enable Runtime PM\n");
+
+ return 0;
+}
+
+static void mtk_hdmi_v2_remove(struct platform_device *pdev)
+{
+ struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
+
+ i2c_put_adapter(hdmi->ddc_adpt);
+}
+
+static const struct of_device_id mtk_drm_hdmi_v2_of_ids[] = {
+ { .compatible = "mediatek,mt8188-hdmi-tx", .data = &mtk_hdmi_conf_mt8188 },
+ { .compatible = "mediatek,mt8195-hdmi-tx", .data = &mtk_hdmi_conf_mt8195 },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mtk_drm_hdmi_v2_of_ids);
+
+static struct platform_driver mtk_hdmi_v2_driver = {
+ .probe = mtk_hdmi_v2_probe,
+ .remove = mtk_hdmi_v2_remove,
+ .driver = {
+ .name = "mediatek-drm-hdmi-v2",
+ .of_match_table = mtk_drm_hdmi_v2_of_ids,
+ .pm = &mtk_hdmi_v2_pm_ops,
+ },
+};
+module_platform_driver(mtk_hdmi_v2_driver);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>>");
+MODULE_DESCRIPTION("MediaTek HDMIv2 Driver");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("DRM_MTK_HDMI");
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 41/43] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188
2025-02-17 15:48 ` [PATCH v7 41/43] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188 AngeloGioacchino Del Regno
@ 2025-02-27 8:17 ` CK Hu (胡俊光)
0 siblings, 0 replies; 74+ messages in thread
From: CK Hu (胡俊光) @ 2025-02-27 8:17 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, chunkuang.hu
Cc: robh, jie.qiu, tzimmermann, simona, mripard,
Jitao Shi (石记涛),
linux-mediatek, dri-devel, maarten.lankhorst, linux-kernel,
devicetree, kernel, dmitry.baryshkov, krzk+dt,
Lewis Liao (廖柏鈞),
p.zabel, conor+dt, TommyYL Chen (陳彥良),
Ives Chenjh (陳俊弘),
airlied, linux-arm-kernel, matthias.bgg,
Jason-JH Lin (林睿祥),
junzhi.zhao
On Mon, 2025-02-17 at 16:48 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
>
>
> Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
> found in MediaTek's MT8195, MT8188 SoC and their variants, and
> including support for display modes up to 4k60 and for HDMI
> Audio, as per the HDMI 2.0 spec.
>
> HDCP and CEC functionalities are also supported by this hardware,
> but are not included in this commit and that also poses a slight
> difference between the V2 and V1 controllers in how they handle
> Hotplug Detection (HPD).
>
> While the v1 controller was using the CEC controller to check
> HDMI cable connection and disconnection, in this driver the v2
> one does not.
>
> This is due to the fact that on parts with v2 designs, like the
> MT8195 SoC, there is one CEC controller shared between the HDMI
> Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
> adding support to use the CEC HW to wake up the HDMI controllers
> it is necessary to have support for one TX, one RX *and* for both
> at the same time.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
[snip]
> +
> +static inline void mtk_hdmi_v2_hw_reset_av_mute_regs(struct mtk_hdmi *hdmi)
> +{
This function is called only by mtk_hdmi_v2_hw_gcp_avmute(), so merge it into mtk_hdmi_v2_hw_gcp_avmute().
Your point is that function name would show more information about this register setting.
I think you could merge this function and use comment to describe about this register setting.
Function name just show few information. If you want to show more things, comment is better.
If you worry that comment is too many, the comment may be as simple as function name.
It's better to use comment to describe register usage than break them into small pieces functions.
> + /* GCP packet */
> + regmap_clear_bits(hdmi->regs, TOP_CFG01, CP_CLR_MUTE_EN | CP_SET_MUTE_EN);
> + regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, CP_RPT_EN);
> + regmap_clear_bits(hdmi->regs, TOP_INFO_EN, CP_EN | CP_EN_WR);
> +}
> +
> +static inline void mtk_hdmi_v2_hw_gcp_avmute(struct mtk_hdmi *hdmi, bool mute)
> +{
> + mtk_hdmi_v2_hw_reset_av_mute_regs(hdmi);
> +
> + if (mute)
> + regmap_set_bits(hdmi->regs, TOP_CFG01, CP_SET_MUTE_EN);
> + else
> + regmap_set_bits(hdmi->regs, TOP_CFG01, CP_CLR_MUTE_EN);
> +
> + regmap_set_bits(hdmi->regs, TOP_INFO_RPT, CP_RPT_EN);
> + regmap_set_bits(hdmi->regs, TOP_INFO_EN, CP_EN | CP_EN_WR);
> +}
> +
[snip]
> +
> +static void mtk_hdmi_v2_change_video_resolution(struct mtk_hdmi *hdmi)
> +{
> + mtk_hdmi_v2_hw_reset(hdmi);
> + mtk_hdmi_v2_set_sw_hpd(hdmi, true);
> + udelay(2);
> +
> + regmap_write(hdmi->regs, HDCP_TOP_CTRL, 0);
> +
> + /* Enable HDCP reauthentication interrupt */
> + regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HDCP2X_RX_REAUTH_REQ_DDCM_INT);
You have mentioned that hardware would process this interrupt internally so we need this interrupt.
Add comment for this because this is not trivial.
> +
> + /* Enable hotplug and pord interrupts */
> + mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true);
> +
> + /* Force enabling HDCP HPD */
> + regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR);
> + regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW);
> +
> + /* Set 8 bits per pixel */
> + regmap_update_bits(hdmi->regs, TOP_CFG00, TMDS_PACK_MODE,
> + FIELD_PREP(TMDS_PACK_MODE, TMDS_PACK_MODE_8BPP));
> + /* Disable generating deepcolor packets */
> + regmap_clear_bits(hdmi->regs, TOP_CFG00, DEEPCOLOR_PKT_EN);
> + /* Disable adding deepcolor information to the general packet */
> + regmap_clear_bits(hdmi->regs, TOP_MISC_CTLR, DEEP_COLOR_ADD);
> +
> + if (hdmi->curr_conn->display_info.is_hdmi)
> + regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI);
> + else
> + regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI);
> +
> + udelay(5);
> + mtk_hdmi_v2_hw_vid_mute(hdmi, true);
> + mtk_hdmi_v2_hw_aud_mute(hdmi, true);
> + mtk_hdmi_v2_hw_gcp_avmute(hdmi, false);
> +
> + regmap_update_bits(hdmi->regs, TOP_CFG01,
> + NULL_PKT_VSYNC_HIGH_EN | NULL_PKT_EN, NULL_PKT_VSYNC_HIGH_EN);
> + usleep_range(100, 150);
> +
> + /* Enable scrambling if tmds clock is 340MHz or more */
> + mtk_hdmi_v2_enable_scrambling(hdmi, hdmi->mode.clock >= 340 * KILO);
> +
> + /* Disable YUV420 downsampling */
> + mtk_hdmi_yuv420_downsampling(hdmi, false);
> +}
> +
[snip]
> +
> +static void mtk_hdmi_hpd_event(enum hdmi_hpd_state hpd, struct device *dev)
> +{
> + struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> +
> + if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev)
> + drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
This function just do one thing and is called only by isr thread, so merge this function into isr thread.
> +}
> +
> +static enum hdmi_hpd_state mtk_hdmi_v2_hpd_pord_status(struct mtk_hdmi *hdmi)
> +{
> + u8 hpd_pin_sta, pord_pin_sta;
> + u32 hpd_status;
> +
> + regmap_read(hdmi->regs, HPD_DDC_STATUS, &hpd_status);
> + hpd_pin_sta = FIELD_GET(HPD_PIN_STA, hpd_status);
> + pord_pin_sta = FIELD_GET(PORD_PIN_STA, hpd_status);
> +
> + if (hpd_pin_sta && pord_pin_sta)
> + return HDMI_PLUG_IN_AND_SINK_POWER_ON;
> + else if (hpd_pin_sta)
> + return HDMI_PLUG_IN_ONLY;
> + else
> + return HDMI_PLUG_OUT;
In v1, cec driver treat '(hpd_pin_sta && pord_pin_sta) is true' as plug in, otherwise plug out.
It seems that v1 could support 3 status but it choose 2 status and make external connector complicated?
Add comment about the benefit for external connector.
> +}
> +
> +static irqreturn_t mtk_hdmi_v2_isr(int irq, void *arg)
> +{
> + struct mtk_hdmi *hdmi = arg;
> + unsigned int irq_sta;
> + int ret = IRQ_HANDLED;
> +
> + regmap_read(hdmi->regs, TOP_INT_STA00, &irq_sta);
> +
> + /* Handle Hotplug Detection interrupt */
> + if (irq_sta & (HTPLG_R_INT | HTPLG_F_INT | PORD_F_INT | PORD_R_INT)) {
if (irq_sta & HPD_PORD_HW_IRQS) {
> + mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, false);
The reason you dynamically enable/disable hpd irq is to prevent isr thread to be interrupted.
But I think the isr thread could be interrupted and nothing would be error.
If the isr thread is resheduled, then it just read the latest plug status again and report it to drm core.
I don't know why you don't want reschedule?
> + ret = IRQ_WAKE_THREAD;
> + }
> +
> + /*
> + * Clear all 32 + 19 interrupts in CLR00 and CLR01: this is important
> + * to avoid unwanted retriggering of any interrupts
> + */
If you does not enable interrupt in TOP_INT_ENABLE01 (I mean software disable these interrupt),
and hardware would still trigger these interrupt, add comment to describe this weird hardware behavior.
I will treat this weird behavior as hardware bug, and expect it would be fixed in next SoC.
Regards,
CK
> + regmap_write(hdmi->regs, TOP_INT_CLR00, GENMASK(31, 0));
> + regmap_write(hdmi->regs, TOP_INT_CLR01, GENMASK(18, 0));
> +
> + /* Restore interrupt clearing registers to zero */
> + regmap_write(hdmi->regs, TOP_INT_CLR00, 0);
> + regmap_write(hdmi->regs, TOP_INT_CLR01, 0);
> +
> + return ret;
> +}
> +
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 42/43] drm/mediatek: mtk_hdmi_v2: Add debugfs ops and implement ABIST
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (40 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 41/43] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188 AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-27 5:59 ` CK Hu (胡俊光)
2025-02-17 15:48 ` [PATCH v7 43/43] drm/mediatek/hdmi: Use syscon_regmap_lookup_by_phandle_args AngeloGioacchino Del Regno
2025-02-25 9:17 ` [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin
Implement the Automated Built-In Self-Test ABIST functionality
provided by the HDMIv2 IP and expose it through the "hdmi_abist"
debugfs file.
Write "1" to this file to activate ABIST, or "0" to deactivate.
The ABIST functionality can be used to validate that the HDMI
Transmitter itself works and that can output a valid image to
the HDMI Display that is connected.
This is especially useful when trying to rule out any possible
issue that is related to the display pipeline, as the HDMI Tx
is always the last component; this means that HDMI ABIST can be
used even without prior display controller pipeline configuration.
The expected output is a 100% color bar (rainbow) test pattern.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi_v2.c | 123 +++++++++++++++++++++++++
1 file changed, 123 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
index 4cf82b924124..f4ae7f4373e1 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
@@ -1157,6 +1157,128 @@ static int mtk_hdmi_v2_hdmi_write_infoframe(struct drm_bridge *bridge,
return 0;
}
+static int mtk_hdmi_v2_set_abist(struct mtk_hdmi *hdmi, bool enable)
+{
+ struct drm_display_mode *mode = &hdmi->mode;
+ int abist_format = -EINVAL;
+ bool interlaced;
+
+ if (!enable) {
+ regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE);
+ return 0;
+ }
+
+ if (!mode->hdisplay || !mode->vdisplay)
+ return -EINVAL;
+
+ interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
+
+ switch (mode->hdisplay) {
+ case 720:
+ if (mode->vdisplay == 480)
+ abist_format = 2;
+ else if (mode->vdisplay == 576)
+ abist_format = 11;
+ break;
+ case 1280:
+ if (mode->vdisplay == 720)
+ abist_format = 3;
+ break;
+ case 1440:
+ if (mode->vdisplay == 480)
+ abist_format = interlaced ? 5 : 9;
+ else if (mode->vdisplay == 576)
+ abist_format = interlaced ? 14 : 18;
+ break;
+ case 1920:
+ if (mode->vdisplay == 1080)
+ abist_format = interlaced ? 4 : 10;
+ break;
+ case 3840:
+ if (mode->vdisplay == 2160)
+ abist_format = 25;
+ break;
+ case 4096:
+ if (mode->vdisplay == 2160)
+ abist_format = 26;
+ break;
+ default:
+ break;
+ }
+ if (abist_format < 0)
+ return abist_format;
+
+ regmap_update_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_VIDEO_FORMAT,
+ FIELD_PREP(HDMI_ABIST_VIDEO_FORMAT, abist_format));
+ regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE);
+ return 0;
+}
+
+static int mtk_hdmi_v2_debug_abist_show(struct seq_file *m, void *arg)
+{
+ struct mtk_hdmi *hdmi = m->private;
+ bool en;
+ u32 val;
+ int ret;
+
+ if (!hdmi)
+ return -EINVAL;
+
+ ret = regmap_read(hdmi->regs, TOP_CFG00, &val);
+ if (ret)
+ return ret;
+
+ en = FIELD_GET(HDMI_ABIST_ENABLE, val);
+
+ seq_printf(m, "HDMI Automated Built-In Self Test: %s\n",
+ en ? "Enabled" : "Disabled");
+
+ return 0;
+}
+
+static ssize_t mtk_hdmi_v2_debug_abist_write(struct file *file,
+ const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ struct seq_file *m = file->private_data;
+ int ret;
+ u32 en;
+
+ if (!m || !m->private || *offp)
+ return -EINVAL;
+
+ ret = kstrtouint_from_user(ubuf, len, 0, &en);
+ if (ret)
+ return ret;
+
+ if (en < 0 || en > 1)
+ return -EINVAL;
+
+ mtk_hdmi_v2_set_abist((struct mtk_hdmi *)m->private, en);
+ return len;
+}
+
+static int mtk_hdmi_v2_debug_abist_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, mtk_hdmi_v2_debug_abist_show, inode->i_private);
+}
+
+static const struct file_operations mtk_hdmi_debug_abist_fops = {
+ .owner = THIS_MODULE,
+ .open = mtk_hdmi_v2_debug_abist_open,
+ .read = seq_read,
+ .write = mtk_hdmi_v2_debug_abist_write,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static void mtk_hdmi_v2_debugfs_init(struct drm_bridge *bridge, struct dentry *root)
+{
+ struct mtk_hdmi *dpi = hdmi_ctx_from_bridge(bridge);
+
+ debugfs_create_file("hdmi_abist", 0640, root, dpi, &mtk_hdmi_debug_abist_fops);
+}
+
static const struct drm_bridge_funcs mtk_v2_hdmi_bridge_funcs = {
.attach = mtk_hdmi_v2_bridge_attach,
.detach = mtk_hdmi_v2_bridge_detach,
@@ -1176,6 +1298,7 @@ static const struct drm_bridge_funcs mtk_v2_hdmi_bridge_funcs = {
.hdmi_tmds_char_rate_valid = mtk_hdmi_v2_hdmi_tmds_char_rate_valid,
.hdmi_clear_infoframe = mtk_hdmi_v2_hdmi_clear_infoframe,
.hdmi_write_infoframe = mtk_hdmi_v2_hdmi_write_infoframe,
+ .debugfs_init = mtk_hdmi_v2_debugfs_init,
};
/*
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 42/43] drm/mediatek: mtk_hdmi_v2: Add debugfs ops and implement ABIST
2025-02-17 15:48 ` [PATCH v7 42/43] drm/mediatek: mtk_hdmi_v2: Add debugfs ops and implement ABIST AngeloGioacchino Del Regno
@ 2025-02-27 5:59 ` CK Hu (胡俊光)
0 siblings, 0 replies; 74+ messages in thread
From: CK Hu (胡俊光) @ 2025-02-27 5:59 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, chunkuang.hu
Cc: robh, jie.qiu, tzimmermann, simona, mripard,
Jitao Shi (石记涛),
linux-mediatek, dri-devel, maarten.lankhorst, linux-kernel,
devicetree, kernel, dmitry.baryshkov, krzk+dt,
Lewis Liao (廖柏鈞),
p.zabel, conor+dt, TommyYL Chen (陳彥良),
Ives Chenjh (陳俊弘),
airlied, linux-arm-kernel, matthias.bgg,
Jason-JH Lin (林睿祥),
junzhi.zhao
On Mon, 2025-02-17 at 16:48 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
>
>
> Implement the Automated Built-In Self-Test ABIST functionality
> provided by the HDMIv2 IP and expose it through the "hdmi_abist"
> debugfs file.
>
> Write "1" to this file to activate ABIST, or "0" to deactivate.
>
> The ABIST functionality can be used to validate that the HDMI
> Transmitter itself works and that can output a valid image to
> the HDMI Display that is connected.
>
> This is especially useful when trying to rule out any possible
> issue that is related to the display pipeline, as the HDMI Tx
> is always the last component; this means that HDMI ABIST can be
> used even without prior display controller pipeline configuration.
>
> The expected output is a 100% color bar (rainbow) test pattern.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v7 43/43] drm/mediatek/hdmi: Use syscon_regmap_lookup_by_phandle_args
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (41 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 42/43] drm/mediatek: mtk_hdmi_v2: Add debugfs ops and implement ABIST AngeloGioacchino Del Regno
@ 2025-02-17 15:48 ` AngeloGioacchino Del Regno
2025-02-27 6:01 ` CK Hu (胡俊光)
2025-02-25 9:17 ` [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
43 siblings, 1 reply; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-17 15:48 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ck.hu, jitao.shi, jie.qiu,
junzhi.zhao, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, dmitry.baryshkov, lewis.liao,
ives.chenjh, tommyyl.chen, jason-jh.lin, Krzysztof Kozlowski
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Use syscon_regmap_lookup_by_phandle_args() which is a wrapper over
syscon_regmap_lookup_by_phandle() combined with getting the syscon
argument. Except simpler code this annotates within one line that given
phandle has arguments, so grepping for code would be easier.
There is also no real benefit in printing errors on missing syscon
argument, because this is done just too late: runtime check on
static/build-time data. Dtschema and Devicetree bindings offer the
static/build-time check for this already.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
[Angelo: Rebased over HDMIv2/DDCv2 series cleanups]
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
index 784bc05c9541..00a638a3caf4 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
@@ -269,12 +269,9 @@ static int mtk_hdmi_get_cec_dev(struct mtk_hdmi *hdmi, struct device *dev, struc
* MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
* registers it contains.
*/
- hdmi->sys_regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
+ hdmi->sys_regmap = syscon_regmap_lookup_by_phandle_args(np, "mediatek,syscon-hdmi",
+ 1, &hdmi->sys_offset);
if (IS_ERR(hdmi->sys_regmap))
- return PTR_ERR(hdmi->sys_regmap);
-
- ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1, &hdmi->sys_offset);
- if (ret)
return dev_err_probe(dev, ret,
"Failed to get system configuration registers\n");
--
2.48.1
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [PATCH v7 43/43] drm/mediatek/hdmi: Use syscon_regmap_lookup_by_phandle_args
2025-02-17 15:48 ` [PATCH v7 43/43] drm/mediatek/hdmi: Use syscon_regmap_lookup_by_phandle_args AngeloGioacchino Del Regno
@ 2025-02-27 6:01 ` CK Hu (胡俊光)
0 siblings, 0 replies; 74+ messages in thread
From: CK Hu (胡俊光) @ 2025-02-27 6:01 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, chunkuang.hu
Cc: robh, jie.qiu, tzimmermann, simona, mripard,
Jitao Shi (石记涛),
linux-mediatek, dri-devel, maarten.lankhorst, linux-kernel,
devicetree, kernel, dmitry.baryshkov, krzk+dt,
Lewis Liao (廖柏鈞),
krzysztof.kozlowski, p.zabel, conor+dt,
TommyYL Chen (陳彥良),
Ives Chenjh (陳俊弘),
airlied, linux-arm-kernel, matthias.bgg,
Jason-JH Lin (林睿祥),
junzhi.zhao
On Mon, 2025-02-17 at 16:48 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
>
>
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> Use syscon_regmap_lookup_by_phandle_args() which is a wrapper over
> syscon_regmap_lookup_by_phandle() combined with getting the syscon
> argument. Except simpler code this annotates within one line that given
> phandle has arguments, so grepping for code would be easier.
>
> There is also no real benefit in printing errors on missing syscon
> argument, because this is done just too late: runtime check on
> static/build-time data. Dtschema and Devicetree bindings offer the
> static/build-time check for this already.
I would apply bug-fix, cleanup, and refinement patches first and then apply v2 related patches.
So bug-fix, cleanup, and refinement patches could be backported to old version branch without any v2 related patches.
When I apply this patch, conflicts happen.
Please rebase this series onto mediatek-drm-next, and apply this patch before v2 related patches.
Regards,
CK
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> [Angelo: Rebased over HDMIv2/DDCv2 series cleanups]
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2
2025-02-17 15:47 [PATCH v7 00/43] Add support for MT8195/88 DPI, HDMIv2 and DDCv2 AngeloGioacchino Del Regno
` (42 preceding siblings ...)
2025-02-17 15:48 ` [PATCH v7 43/43] drm/mediatek/hdmi: Use syscon_regmap_lookup_by_phandle_args AngeloGioacchino Del Regno
@ 2025-02-25 9:17 ` AngeloGioacchino Del Regno
43 siblings, 0 replies; 74+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-02-25 9:17 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, matthias.bgg, ck.hu,
jitao.shi, jie.qiu, junzhi.zhao, dri-devel, linux-mediatek,
devicetree, linux-kernel, linux-arm-kernel, kernel,
dmitry.baryshkov, lewis.liao, ives.chenjh, tommyyl.chen,
jason-jh.lin
Il 17/02/25 16:47, AngeloGioacchino Del Regno ha scritto:
> Changes in v7:
> - Split more patches as requested by CK
> - Changed the order of the interlaced variable addition as requested
> - Cleanups in DDCv2 as requested by CK
> - Removed comment from
> drm/mediatek: mtk_hdmi: Move output init to mtk_hdmi_register_audio_driver()
> as that was forgotten from reintroduction of print in v5
> - Some more small nitpicks as pointed out by CK here and there
>
Hello CK,
Is there any other concern about this series, or can we finally get HDMI support
for MT8188/MT8195 upstream?
Regards,
Angelo
> Changes in v6:
> - Split the TVD clock enable/disable calls in a different commit
> - Changed `is_internal_hdmi` to two different variables, one for
> DPI input clock from HDMI, and one for AFIFO 1T1P output and
> conversion (mtk_dpi)
> - Clarified why MT8195/88 HDMI-reserved DPI1 is different
> - Moved `input_2p_en` bit to platform data to cleanup DPI vs DPINTF
> - 1T2P enable bit is different between DPI and DPINTF, but usage
> is actually the same
> - Cleaned up headers inclusion in mtk_hdmi_v2.c, mtk_hdmi_ddc_v2.c
> - Removed some unused headers, added missing bitfield.h header
> - Split some prints cleanup commits as requested by CK
> - Split the introduction of mtk_hdmi_conf as requested by CK
> - Split commit to make CEC optional as requested by CK
> - Reintroduced forgotten no_capture_mute in codec_pdata (mtk_hdmi_common)
> - Reintroduced error print for audio clocks enablement failure (mtk_hdmi)
> - Added cleanup syscon_regmap_lookup_by_phandle commit from Krzysztof K
>
> Changes in v5:
> - Rebased over next-20250113
> - Resolved merge issues with next-20250113
> - Added bitfield.h inclusion in mtk_dpi in commit [02/33] to resolve
> build issue from 0day CI
> - Removed .atomic_check callback from mtk_hdmi_v2 as it is now part
> of drm_bridge_connector as pointed out by Dmitry B
> - Removed call to pm_runtime_disable() as the driver uses devm
> - Tested again :-)
>
> Changes in v4:
> - DDCv2 binding erroneously dropped in v3 is included again (oops!)
> - Added reference to dai-common.yaml in HDMIv2 binding
> - Dropped pinctrl entries from HDMIv2 binding
> - Fixed required list in HDMIv2 binding and changed node name to
> 'hdmi' instead of 'hdmi-tx'
> - Fixed issue in mtk_hdmi derived from wrong commit splitting action
> from version 3
> - Exported necessary symbols and added namespaces for those
> - Fixed module build for both HDMIv1 and HDMIv2
> - Other cleanups
>
> Changes in v3:
> - Added hpd_enable() and hpd_disable() callbacks as suggested by Dmitry B
> - Removed audio mute call in bridge_enable() as suggested by CK
> - Reworked commonization commits for mtk_hdmi/mtk_hdmi_common and split
> out debugfs/abist implementation as suggested by CK
> - Removed .mode_valid() callback as it is now provided by the bridge
> API in drm_bridge_connector_helper_funcs
> - A bit of cleanups here and there
> - Tested again on HW especially for new hpd_enable/disable callbacks.
>
> Changes in v2:
> - Merged series "Add support for MT8195/8188 and Pattern Generator"
> and "drm/mediatek: Add support for HDMIv2 and DDCv2 IPs" in one
> as they are directly related, as requested by CK Hu
> - More commonization: moved some audio functions to mtk_hdmi_common
> - Fixed a bug in DDCv2 driver to allow sending a message with len=1
> - Renamed some functions in HDMIv2 to consistently use the prefix
> mtk_hdmi_v2_ across the driver
> - Added .mode_valid() callback to HDMIv2
> - Added .atomic_check() callback to HDMIv2
> - Reordered drm_bridge_funcs in HDMIv2 driver
> - Rewritten .edid_read() callback in HDMIv2 to move checking audio
> availability to bridge_pre_enable() stage, and to stop using the
> drm_edid_read_ddc() in favor of drm_edid_read()
> - Added support for API provided HDMI Helpers
> - Added .tmds_char_rate_valid() callback to HDMIv2 for HDMI helpers
> - Added .hdmi_{read,write}_infoframe() callback to HDMIv2 for helpers
> - Added support for Vendor infoframes in HDMIv2
> - Added missing audio-dai-cells to HDMIv2 binding to fix check error
> - Added more information to the HDMIv2 binding for clocks and PHY
> - Added some comments to the HDMIv2 code to clarify why the controller
> is preconfigured in bridge_pre_enable() instead of bridge_enable()
> - Added a mention of the differences in HPD between v1 and v2 to the
> commit introducing the v2 driver (v2 is not using CEC for HPD)
> - ...and tested again on HW! :-)
>
>
> This series adds support for the HDMI-TX v2 Encoder and DDCv2, and for
> the direct connection DPI as found in MT8195, MT8188 and their variants.
>
> Tested on Genio 700 EVK:
> - ABIST ON: ok, pattern generated internally from HDMI is shown on
> HDMI screen at the correct resolution;
> - ABIST OFF + DPI Pattern Generator ON: ok, pattern coming from DPI is
> shown on HDMI screen at the correct resolution;
> - Can negotiate up to 4k60
>
> and on MT8395 Radxa NIO 12L:
> - ABIST ON: ok, pattern generated internally from HDMI is shown on
> HDMI screen at the correct resolution;
> - ABIST OFF + DPI Pattern Generator ON: ok, pattern coming from DPI is
> shown on HDMI screen at the correct resolution;
> - Dual screen usecase validated (DSI + HDMI 3840x2160p 60Hz)
> - Can negotiate up to 4k60
>
> Please note that this submission does *not* include support for HDCP
> nor for CECv2, as I want this to be upstream before implementing
> additional features which are not strictly required for simple
> HDMI output.
>
> Bonus in this series is the addition of support for the Pattern Generator
> found in the DPI HW: since I needed this for debugging during development,
> I had to code in the actual support bits and it looked like a waste of
> time to just remove it.
> I instead decided to clean it up and upstream it, as this will anyway come
> handy for multiple things, of which the most important (imo) are:
> - Adding support for new SoCs in the future will be less time consuming
> as this driver already has the pattern generator in;
> - CI Testing might be able to make use of this to validate that the
> data that comes out is not garbled (so, to help testing display
> support in an automated manner).
>
> AngeloGioacchino Del Regno (41):
> dt-bindings: display: mediatek: dpi: Add MT8195 and MT8188 compat
> drm/mediatek: mtk_dpi: Add support for Pattern Generator in debugfs
> drm/mediatek: mtk_dpi: Use an array for pixclk factor calculation
> drm/mediatek: mtk_dpi: Move pixel clock setting flow to function
> drm/mediatek: mtk_dpi: Add checks for reg_h_fre_con existence
> drm/mediatek: mtk_dpi: Move the input_2p_en bit to platform data
> drm/mediatek: mtk_dpi: Add support for DPI input clock from HDMI
> drm/mediatek: mtk_dpi: Support AFIFO 1T1P output and conversion
> drm/mediatek: mtk_dpi: Explicitly manage TVD clock in power on/off
> drm/mediatek: Add support for MT8195 Digital Parallel Interface
> dt-bindings: display: mediatek: Add binding for HDMIv2 DDC
> dt-bindings: display: mediatek: Add binding for MT8195 HDMI-TX v2
> drm/mediatek: mtk_cec: Switch to register as module_platform_driver
> drm/mediatek: mtk_hdmi_ddc: Switch to register as
> module_platform_driver
> drm/mediatek: mtk_hdmi: Convert to module_platform_driver macro
> drm/mediatek: mtk_hdmi: Compress of_device_id array entries
> drm/mediatek: mtk_hdmi: Unregister audio platform device on failure
> drm/mediatek: mtk_hdmi: Fix typo for aud_sampe_size member
> drm/mediatek: mtk_hdmi: Disgregate function mtk_hdmi_audio_set_param()
> drm/mediatek: mtk_hdmi: Move audio params selection to new function
> drm/mediatek: mtk_hdmi: Move plugged_cb/codec_dev setting to new
> function
> drm/mediatek: mtk_hdmi: Move N/CTS setting to new function
> drm/mediatek: mtk_hdmi: Move vendor/product strings to drm_bridge
> drm/mediatek: mtk_hdmi: Use dev_err_probe() in
> mtk_hdmi_dt_parse_pdata()
> drm/mediatek: mtk_hdmi: Move CEC device parsing in new function
> drm/mediatek: mtk_hdmi: Remove unused members of struct mtk_hdmi
> drm/mediatek: mtk_hdmi: Move output init to
> mtk_hdmi_register_audio_driver()
> drm/mediatek: mtk_hdmi: Use devm managed version of drm_bridge_add
> drm/mediatek: mtk_hdmi: Remove ifdef for CONFIG_PM_SLEEP
> drm/mediatek: mtk_hdmi: Remove goto in mtk_hdmi_clk_enable_audio()
> drm/mediatek: mtk_hdmi: Remove driver bound to HDMI print
> drm/mediatek: mtk_hdmi: Cleanup function mtk_hdmi_resume()
> drm/mediatek: mtk_hdmi: Improve mtk_hdmi_get_all_clk() flexibility
> drm/mediatek: mtk_hdmi: Add HDMI IP version configuration to pdata
> drm/mediatek: mtk_hdmi: Split driver and add common probe function
> drm/mediatek: mtk_hdmi_common: Make CEC support optional
> drm/mediatek: mtk_hdmi_common: Assign DDC adapter pointer to bridge
> drm/mediatek: mtk_hdmi_common: Add OP_HDMI if helper funcs assigned
> drm/mediatek: mtk_hdmi_common: Add var to enable interlaced modes
> drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188
> drm/mediatek: mtk_hdmi_v2: Add debugfs ops and implement ABIST
>
> Guillaume Ranquet (1):
> drm/mediatek: hdmi: Use regmap instead of iomem for main registers
>
> Krzysztof Kozlowski (1):
> drm/mediatek/hdmi: Use syscon_regmap_lookup_by_phandle_args
>
> .../display/mediatek/mediatek,dpi.yaml | 5 +
> .../mediatek/mediatek,mt8195-hdmi-ddc.yaml | 41 +
> .../mediatek/mediatek,mt8195-hdmi.yaml | 151 ++
> drivers/gpu/drm/mediatek/Kconfig | 18 +-
> drivers/gpu/drm/mediatek/Makefile | 11 +-
> drivers/gpu/drm/mediatek/mtk_cec.c | 7 +-
> drivers/gpu/drm/mediatek/mtk_dpi.c | 323 +++-
> drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 10 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 803 ++-------
> drivers/gpu/drm/mediatek/mtk_hdmi.h | 14 -
> drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 435 +++++
> drivers/gpu/drm/mediatek/mtk_hdmi_common.h | 198 +++
> drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c | 2 +-
> drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c | 385 +++++
> drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h | 263 +++
> drivers/gpu/drm/mediatek/mtk_hdmi_v2.c | 1475 +++++++++++++++++
> 17 files changed, 3347 insertions(+), 796 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
> delete mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
>
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