* [PATCH 0/2] Exynos850: Add ACPM node and enable cpufreq
@ 2026-09-29 3:10 Alexey Klimov
2026-09-29 3:10 ` [PATCH 1/2] arm64: dts: exynos850: Add ACPM firmware node Alexey Klimov
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Alexey Klimov @ 2026-09-29 3:10 UTC (permalink / raw)
To: Sam Protsenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Peter Griffin, Alim Akhtar
Cc: Thomas Turner, Tudor Ambarus, linux-samsung-soc,
linux-arm-kernel, devicetree, linux-kernel
This series adds the ACPM IPC firmware node and CPUs operating performance
points for the Exynos850 SoC, switching CPU clock sources to the ACPM DVFS
clocks to enable cpufreq. Exynos850 has two clusters with four Cortex-A55
cores each with identical OPPs.
In theory, we could have two OPPs above known nominal max frequency (2Ghz)
but in practice the board becomes unstable with fully loaded CPU-bound
tasks and hangs pretty quickly on OPPs above 2 Ghz:
opp-2106000000 {
opp-hz = /bits/ 64 <2106000000>;
opp-microvolt = <1106250>;
clock-latency-ns = <500000>;
};
opp-2210000000 {
opp-hz = /bits/ 64 <2210000000>;
opp-microvolt = <1181250>;
clock-latency-ns = <500000>;
};
with random data aborts and illegal instructions. Maybe SoC can survive
short bursts to these frequencies but this requires a bit more messing
around with cpufreq_dt.
Also, it is currently unstable on 2.002 GHz OPP as well so this one
excluded from the series too:
opp-2002000000 {
opp-hz = /bits/ 64 <2002000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <500000>;
};
with the same symptoms but takes much longer (~1..2 hr) to reproduce on
E850-96 WinLink board.
Sustained testing overnight confirmed stability up to 1.846 GHz
(opp-1846000000). Higher OPPs are omitted for now and can be evaluated
when we will have thermal zones.
The dependency for this series is:
https://lore.kernel.org/linux-samsung-soc/20260929-exynos850-acpm-firmware-support-v3-0-473a69fc8a3d@linaro.org/
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
---
Alexey Klimov (2):
arm64: dts: exynos850: Add ACPM firmware node
arm64: dts: exynos850: Add operating points for CPUs and enable cpufreq
arch/arm64/boot/dts/exynos/exynos850.dtsi | 237 +++++++++++++++++++++++++++++-
1 file changed, 233 insertions(+), 4 deletions(-)
---
base-commit: 5a956dde5526a634dca7ccad27c051ebcc306089
change-id: 20260929-exynos850-acpm-node-cpufreq-33819039cf43
prerequisite-message-id: 20260929-exynos850-acpm-firmware-support-v3-0-473a69fc8a3d@linaro.org
prerequisite-patch-id: 5a3c87e368d6bac968f16a0e56fcff5eaec60dea
prerequisite-patch-id: 8d6d1564a919eca361aef19af5dbe1cf3205198e
Best regards,
--
Alexey Klimov <alexey.klimov@linaro.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] arm64: dts: exynos850: Add ACPM firmware node
2026-09-29 3:10 [PATCH 0/2] Exynos850: Add ACPM node and enable cpufreq Alexey Klimov
@ 2026-09-29 3:10 ` Alexey Klimov
2026-09-29 9:02 ` Tudor Ambarus
2026-09-29 3:10 ` [PATCH 2/2] arm64: dts: exynos850: Add operating points for CPUs and enable cpufreq Alexey Klimov
2026-10-03 14:05 ` [PATCH 0/2] Exynos850: Add ACPM node " Krzysztof Kozlowski
2 siblings, 1 reply; 8+ messages in thread
From: Alexey Klimov @ 2026-09-29 3:10 UTC (permalink / raw)
To: Sam Protsenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Peter Griffin, Alim Akhtar
Cc: Thomas Turner, Tudor Ambarus, linux-samsung-soc,
linux-arm-kernel, devicetree, linux-kernel
Add the ACPM firmware node with cpucl0 and cpucl1 clocks. ACPM firmware
protocol provides interface for all client drivers to actually use
features exposed by the APM co-processor.
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
---
arch/arm64/boot/dts/exynos/exynos850.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
index 8a4771899a8e..91c6cee8f483 100644
--- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
@@ -11,6 +11,7 @@
*/
#include <dt-bindings/clock/exynos850.h>
+#include <dt-bindings/clock/samsung,exynos850-acpm.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/samsung,exynos-usi.h>
@@ -170,6 +171,18 @@ timer: timer {
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
+ firmware {
+ acpm_ipc: power-management {
+ compatible = "samsung,exynos850-acpm-ipc";
+ mboxes = <&ap2apm_mailbox>;
+ shmem = <&apm_sram>;
+ clocks = <&cmu_cpucl0 CLK_FOUT_CPUCL0_PLL>,
+ <&cmu_cpucl1 CLK_FOUT_CPUCL1_PLL>;
+ clock-names = "cpucl0", "cpucl1";
+ #clock-cells = <1>;
+ };
+ };
+
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
--
2.51.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/2] arm64: dts: exynos850: Add operating points for CPUs and enable cpufreq
2026-09-29 3:10 [PATCH 0/2] Exynos850: Add ACPM node and enable cpufreq Alexey Klimov
2026-09-29 3:10 ` [PATCH 1/2] arm64: dts: exynos850: Add ACPM firmware node Alexey Klimov
@ 2026-09-29 3:10 ` Alexey Klimov
2026-10-02 14:40 ` Peter Griffin
2026-10-03 14:05 ` [PATCH 0/2] Exynos850: Add ACPM node " Krzysztof Kozlowski
2 siblings, 1 reply; 8+ messages in thread
From: Alexey Klimov @ 2026-09-29 3:10 UTC (permalink / raw)
To: Sam Protsenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Peter Griffin, Alim Akhtar
Cc: Thomas Turner, Tudor Ambarus, linux-samsung-soc,
linux-arm-kernel, devicetree, linux-kernel
Exynos850 has two clusters with four Cortex-A55 cores each. The OPPs are
identical for both clusters.
Add OPPs for both clusters and replace cpu clocks with ACPM
EXYNOS850_CLK_ACPM_DVFS_CPUCL{0,1} clocks.
The maximum nominal frequency should be 2.002 Ghz but at this point the
following OPP is not added here:
opp-2002000000 {
opp-hz = /bits/ 64 <2002000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <500000>;
};
due to stability issues. Testing on a fully loaded system with CPU-bound
tasks triggers data aborts and illegal instruction errors at 2.002 GHz
after 1-2 hours of such stress testing.
Running the same workload overnight on a CPUs fixed at previous OPP didn't
lead to any issues so opp-1846000000 is currentlly the highest one as it is
considered safe.
Higher OPPs can be re-evaluated once thermal support is implemented.
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
---
arch/arm64/boot/dts/exynos/exynos850.dtsi | 224 +++++++++++++++++++++++++++++-
1 file changed, 220 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
index 91c6cee8f483..36501e5903f8 100644
--- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
@@ -100,8 +100,9 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0x0>;
enable-method = "psci";
- clocks = <&cmu_cpucl0 CLK_CLUSTER0_SCLK>;
- clock-names = "cluster0_clk";
+ clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL0>;
+ clock-names = "cpucl0";
+ operating-points-v2 = <&cpucl0_opp_table>;
};
cpu1: cpu@1 {
@@ -109,6 +110,8 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a55";
reg = <0x1>;
enable-method = "psci";
+ clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL0>;
+ operating-points-v2 = <&cpucl0_opp_table>;
};
cpu2: cpu@2 {
@@ -116,6 +119,8 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a55";
reg = <0x2>;
enable-method = "psci";
+ clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL0>;
+ operating-points-v2 = <&cpucl0_opp_table>;
};
cpu3: cpu@3 {
@@ -123,6 +128,8 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a55";
reg = <0x3>;
enable-method = "psci";
+ clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL0>;
+ operating-points-v2 = <&cpucl0_opp_table>;
};
cpu4: cpu@100 {
@@ -130,8 +137,9 @@ cpu4: cpu@100 {
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
- clocks = <&cmu_cpucl1 CLK_CLUSTER1_SCLK>;
- clock-names = "cluster1_clk";
+ clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL1>;
+ clock-names = "cpucl1";
+ operating-points-v2 = <&cpucl1_opp_table>;
};
cpu5: cpu@101 {
@@ -139,6 +147,8 @@ cpu5: cpu@101 {
compatible = "arm,cortex-a55";
reg = <0x101>;
enable-method = "psci";
+ clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL1>;
+ operating-points-v2 = <&cpucl1_opp_table>;
};
cpu6: cpu@102 {
@@ -146,6 +156,8 @@ cpu6: cpu@102 {
compatible = "arm,cortex-a55";
reg = <0x102>;
enable-method = "psci";
+ clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL1>;
+ operating-points-v2 = <&cpucl1_opp_table>;
};
cpu7: cpu@103 {
@@ -153,6 +165,210 @@ cpu7: cpu@103 {
compatible = "arm,cortex-a55";
reg = <0x103>;
enable-method = "psci";
+ clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL1>;
+ operating-points-v2 = <&cpucl1_opp_table>;
+ };
+ };
+
+ cpucl0_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-130000000 {
+ opp-hz = /bits/ 64 <130000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-182000000 {
+ opp-hz = /bits/ 64 <182000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-247000000 {
+ opp-hz = /bits/ 64 <247000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-351000000 {
+ opp-hz = /bits/ 64 <351000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-442000000 {
+ opp-hz = /bits/ 64 <442000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-546000000 {
+ opp-hz = /bits/ 64 <546000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-806000000 {
+ opp-hz = /bits/ 64 <806000000>;
+ opp-microvolt = <656250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-949000000 {
+ opp-hz = /bits/ 64 <949000000>;
+ opp-microvolt = <681250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1053000000 {
+ opp-hz = /bits/ 64 <1053000000>;
+ opp-microvolt = <706250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1157000000 {
+ opp-hz = /bits/ 64 <1157000000>;
+ opp-microvolt = <737500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <781250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1456000000 {
+ opp-hz = /bits/ 64 <1456000000>;
+ opp-microvolt = <825000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1586000000 {
+ opp-hz = /bits/ 64 <1586000000>;
+ opp-microvolt = <875000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1742000000 {
+ opp-hz = /bits/ 64 <1742000000>;
+ opp-microvolt = <937500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1846000000 {
+ opp-hz = /bits/ 64 <1846000000>;
+ opp-microvolt = <981250>;
+ clock-latency-ns = <500000>;
+ };
+ };
+
+ cpucl1_opp_table: opp-table-1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-130000000 {
+ opp-hz = /bits/ 64 <130000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-182000000 {
+ opp-hz = /bits/ 64 <182000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-247000000 {
+ opp-hz = /bits/ 64 <247000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-351000000 {
+ opp-hz = /bits/ 64 <351000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-442000000 {
+ opp-hz = /bits/ 64 <442000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-546000000 {
+ opp-hz = /bits/ 64 <546000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-806000000 {
+ opp-hz = /bits/ 64 <806000000>;
+ opp-microvolt = <656250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-949000000 {
+ opp-hz = /bits/ 64 <949000000>;
+ opp-microvolt = <681250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1053000000 {
+ opp-hz = /bits/ 64 <1053000000>;
+ opp-microvolt = <706250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1157000000 {
+ opp-hz = /bits/ 64 <1157000000>;
+ opp-microvolt = <737500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <781250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1456000000 {
+ opp-hz = /bits/ 64 <1456000000>;
+ opp-microvolt = <825000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1586000000 {
+ opp-hz = /bits/ 64 <1586000000>;
+ opp-microvolt = <875000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1742000000 {
+ opp-hz = /bits/ 64 <1742000000>;
+ opp-microvolt = <937500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1846000000 {
+ opp-hz = /bits/ 64 <1846000000>;
+ opp-microvolt = <981250>;
+ clock-latency-ns = <500000>;
};
};
--
2.51.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] arm64: dts: exynos850: Add ACPM firmware node
2026-09-29 3:10 ` [PATCH 1/2] arm64: dts: exynos850: Add ACPM firmware node Alexey Klimov
@ 2026-09-29 9:02 ` Tudor Ambarus
2026-09-30 11:54 ` Alexey Klimov
0 siblings, 1 reply; 8+ messages in thread
From: Tudor Ambarus @ 2026-09-29 9:02 UTC (permalink / raw)
To: Alexey Klimov, Sam Protsenko, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Peter Griffin, Alim Akhtar
Cc: Thomas Turner, linux-samsung-soc, linux-arm-kernel, devicetree,
linux-kernel
Hi, Alexey,
On 9/29/26 6:10 AM, Alexey Klimov wrote:
> Add the ACPM firmware node with cpucl0 and cpucl1 clocks. ACPM firmware
> protocol provides interface for all client drivers to actually use
> features exposed by the APM co-processor.
>
> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
> ---
> arch/arm64/boot/dts/exynos/exynos850.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
> index 8a4771899a8e..91c6cee8f483 100644
> --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
> @@ -11,6 +11,7 @@
> */
>
> #include <dt-bindings/clock/exynos850.h>
> +#include <dt-bindings/clock/samsung,exynos850-acpm.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/soc/samsung,exynos-usi.h>
>
> @@ -170,6 +171,18 @@ timer: timer {
> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> };
>
> + firmware {
> + acpm_ipc: power-management {
> + compatible = "samsung,exynos850-acpm-ipc";
> + mboxes = <&ap2apm_mailbox>;
> + shmem = <&apm_sram>;
> + clocks = <&cmu_cpucl0 CLK_FOUT_CPUCL0_PLL>,
> + <&cmu_cpucl1 CLK_FOUT_CPUCL1_PLL>;
Why do you describe these clocks?
Thanks,
ta
> + clock-names = "cpucl0", "cpucl1";
> + #clock-cells = <1>;
> + };
> + };
> +
> soc: soc@0 {
> compatible = "simple-bus";
> #address-cells = <1>;
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] arm64: dts: exynos850: Add ACPM firmware node
2026-09-29 9:02 ` Tudor Ambarus
@ 2026-09-30 11:54 ` Alexey Klimov
2026-10-01 13:27 ` Tudor Ambarus
0 siblings, 1 reply; 8+ messages in thread
From: Alexey Klimov @ 2026-09-30 11:54 UTC (permalink / raw)
To: Tudor Ambarus, Sam Protsenko, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Peter Griffin, Alim Akhtar
Cc: Thomas Turner, linux-samsung-soc, linux-arm-kernel, devicetree,
linux-kernel
Hi Tudor,
On Tue Sep 29, 2026 at 10:02 AM BST, Tudor Ambarus wrote:
> Hi, Alexey,
> On 9/29/26 6:10 AM, Alexey Klimov wrote:
>> Add the ACPM firmware node with cpucl0 and cpucl1 clocks. ACPM firmware
>> protocol provides interface for all client drivers to actually use
>> features exposed by the APM co-processor.
>>
>> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
>> ---
>> arch/arm64/boot/dts/exynos/exynos850.dtsi | 13 +++++++++++++
>> 1 file changed, 13 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
>> index 8a4771899a8e..91c6cee8f483 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
>> @@ -11,6 +11,7 @@
>> */
>>
>> #include <dt-bindings/clock/exynos850.h>
>> +#include <dt-bindings/clock/samsung,exynos850-acpm.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/soc/samsung,exynos-usi.h>
>>
>> @@ -170,6 +171,18 @@ timer: timer {
>> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>> };
>>
>> + firmware {
>> + acpm_ipc: power-management {
>> + compatible = "samsung,exynos850-acpm-ipc";
>> + mboxes = <&ap2apm_mailbox>;
>> + shmem = <&apm_sram>;
>> + clocks = <&cmu_cpucl0 CLK_FOUT_CPUCL0_PLL>,
>> + <&cmu_cpucl1 CLK_FOUT_CPUCL1_PLL>;
>
> Why do you describe these clocks?
>> + clock-names = "cpucl0", "cpucl1";
To link these clocks with ACPM clocks from this list:
(file drivers/clk/samsung/clk-acpm.c)
static const struct acpm_clk_variant exynos850_acpm_clks[] = {
ACPM_CLK("mif"),
ACPM_CLK("int"),
ACPM_CLK("cpucl0"),
ACPM_CLK("cpucl1"),
ACPM_CLK("g3d"),
ACPM_CLK("aud"),
ACPM_CLK("cam"),
ACPM_CLK("disp"),
ACPM_CLK("cp"),
};
Eventually to have some sensible/working ->recalc_rate() for ACPM
cpucl{0,1} clocks.
Which is needed, for instance, for cpufreq_dt because it registers with:
static struct cpufreq_driver dt_cpufreq_driver = {
.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
CPUFREQ_IS_COOLING_DEV,
Don't know if it answers the question (if I understood it correctly)?
Best regards,
Alexey
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] arm64: dts: exynos850: Add ACPM firmware node
2026-09-30 11:54 ` Alexey Klimov
@ 2026-10-01 13:27 ` Tudor Ambarus
0 siblings, 0 replies; 8+ messages in thread
From: Tudor Ambarus @ 2026-10-01 13:27 UTC (permalink / raw)
To: Alexey Klimov, Sam Protsenko, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Peter Griffin, Alim Akhtar
Cc: Thomas Turner, linux-samsung-soc, linux-arm-kernel, devicetree,
linux-kernel, Juan Yescas, André Draszik
On 9/30/26 2:54 PM, Alexey Klimov wrote:
> Hi Tudor,
>
> On Tue Sep 29, 2026 at 10:02 AM BST, Tudor Ambarus wrote:
>> Hi, Alexey,
>> On 9/29/26 6:10 AM, Alexey Klimov wrote:
>>> Add the ACPM firmware node with cpucl0 and cpucl1 clocks. ACPM firmware
>>> protocol provides interface for all client drivers to actually use
>>> features exposed by the APM co-processor.
>>>
>>> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
>>> ---
>>> arch/arm64/boot/dts/exynos/exynos850.dtsi | 13 +++++++++++++
>>> 1 file changed, 13 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
>>> index 8a4771899a8e..91c6cee8f483 100644
>>> --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
>>> +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
>>> @@ -11,6 +11,7 @@
>>> */
>>>
>>> #include <dt-bindings/clock/exynos850.h>
>>> +#include <dt-bindings/clock/samsung,exynos850-acpm.h>
>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> #include <dt-bindings/soc/samsung,exynos-usi.h>
>>>
>>> @@ -170,6 +171,18 @@ timer: timer {
>>> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>>> };
>>>
>>> + firmware {
>>> + acpm_ipc: power-management {
>>> + compatible = "samsung,exynos850-acpm-ipc";
>>> + mboxes = <&ap2apm_mailbox>;
>>> + shmem = <&apm_sram>;
>>> + clocks = <&cmu_cpucl0 CLK_FOUT_CPUCL0_PLL>,
>>> + <&cmu_cpucl1 CLK_FOUT_CPUCL1_PLL>;
>>
>> Why do you describe these clocks?
>
>>> + clock-names = "cpucl0", "cpucl1";
>
> To link these clocks with ACPM clocks from this list:
> (file drivers/clk/samsung/clk-acpm.c)
>
> static const struct acpm_clk_variant exynos850_acpm_clks[] = {
> ACPM_CLK("mif"),
> ACPM_CLK("int"),
> ACPM_CLK("cpucl0"),
> ACPM_CLK("cpucl1"),
> ACPM_CLK("g3d"),
> ACPM_CLK("aud"),
> ACPM_CLK("cam"),
> ACPM_CLK("disp"),
> ACPM_CLK("cp"),
> };
>
> Eventually to have some sensible/working ->recalc_rate() for ACPM
> cpucl{0,1} clocks.
>
> Which is needed, for instance, for cpufreq_dt because it registers with:
>
> static struct cpufreq_driver dt_cpufreq_driver = {
> .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
> CPUFREQ_IS_COOLING_DEV,
>
> Don't know if it answers the question (if I understood it correctly)?
>
Thanks, Alexey. I see now that clk-acpm.c uses pdata.fw_name on the
parent (acpm_ipc) DT node to link the ACPM clocks to the CMU PLLs for
->recalc_rate(). Could you please clarify a few things in the commit
message (and below):
1. Physically, CLK_FOUT_CPUCL{0,1}_PLL are not input clocks feeding the
APM hardware, they are the PLLs that ACPM reconfigures behind the
scenes. Meanwhile, acpm_clk_register() sets num_parents = 1 and
pdata.fw_name = name for all 9 clocks in exynos850_acpm_clks[].
Since the DT node only lists "cpucl0" and "cpucl1", won't the other
7 ACPM clocks (mif, int, g3d, aud, cam, disp, cp) remain permanently
orphaned in CCF with rate = 0?
2. Does bypass_acpm_exynos850_get_rate() actually return the updated rate
after clk_set_rate()? When ACPM changes the PLL frequency via IPC,
CCF is unaware that the parent clock (fout_cpucl0_pll) changed in
hardware. Even with CLK_GET_RATE_NOCACHE on the ACPM clock,
__clk_recalc_rates() only reads the cached core->parent->rate without
calling ->recalc_rate() on the parent itself. Won't parent_rate remain
stuck at the initial boot frequency?
3. In drivers/clk/samsung/clk-exynos850.c, cpucl0_cmu_info and
cpucl1_cmu_info still set `.manual_plls = true`.
Does that conflict with ACPM firmware managing the CPU PLLs?
Cheers,
ta
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] arm64: dts: exynos850: Add operating points for CPUs and enable cpufreq
2026-09-29 3:10 ` [PATCH 2/2] arm64: dts: exynos850: Add operating points for CPUs and enable cpufreq Alexey Klimov
@ 2026-10-02 14:40 ` Peter Griffin
0 siblings, 0 replies; 8+ messages in thread
From: Peter Griffin @ 2026-10-02 14:40 UTC (permalink / raw)
To: Alexey Klimov
Cc: Sam Protsenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Alim Akhtar, Thomas Turner, Tudor Ambarus, linux-samsung-soc,
linux-arm-kernel, devicetree, linux-kernel
On Tue, 29 Sept 2026 at 04:11, Alexey Klimov <alexey.klimov@linaro.org> wrote:
>
> Exynos850 has two clusters with four Cortex-A55 cores each. The OPPs are
> identical for both clusters.
> Add OPPs for both clusters and replace cpu clocks with ACPM
> EXYNOS850_CLK_ACPM_DVFS_CPUCL{0,1} clocks.
>
> The maximum nominal frequency should be 2.002 Ghz but at this point the
> following OPP is not added here:
>
> opp-2002000000 {
> opp-hz = /bits/ 64 <2002000000>;
> opp-microvolt = <1050000>;
> clock-latency-ns = <500000>;
> };
>
> due to stability issues. Testing on a fully loaded system with CPU-bound
> tasks triggers data aborts and illegal instruction errors at 2.002 GHz
> after 1-2 hours of such stress testing.
> Running the same workload overnight on a CPUs fixed at previous OPP didn't
> lead to any issues so opp-1846000000 is currentlly the highest one as it is
> considered safe.
>
> Higher OPPs can be re-evaluated once thermal support is implemented.
>
> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
> ---
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
> arch/arm64/boot/dts/exynos/exynos850.dtsi | 224 +++++++++++++++++++++++++++++-
> 1 file changed, 220 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
> index 91c6cee8f483..36501e5903f8 100644
> --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
> @@ -100,8 +100,9 @@ cpu0: cpu@0 {
> compatible = "arm,cortex-a55";
> reg = <0x0>;
> enable-method = "psci";
> - clocks = <&cmu_cpucl0 CLK_CLUSTER0_SCLK>;
> - clock-names = "cluster0_clk";
> + clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL0>;
> + clock-names = "cpucl0";
> + operating-points-v2 = <&cpucl0_opp_table>;
> };
>
> cpu1: cpu@1 {
> @@ -109,6 +110,8 @@ cpu1: cpu@1 {
> compatible = "arm,cortex-a55";
> reg = <0x1>;
> enable-method = "psci";
> + clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL0>;
> + operating-points-v2 = <&cpucl0_opp_table>;
> };
>
> cpu2: cpu@2 {
> @@ -116,6 +119,8 @@ cpu2: cpu@2 {
> compatible = "arm,cortex-a55";
> reg = <0x2>;
> enable-method = "psci";
> + clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL0>;
> + operating-points-v2 = <&cpucl0_opp_table>;
> };
>
> cpu3: cpu@3 {
> @@ -123,6 +128,8 @@ cpu3: cpu@3 {
> compatible = "arm,cortex-a55";
> reg = <0x3>;
> enable-method = "psci";
> + clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL0>;
> + operating-points-v2 = <&cpucl0_opp_table>;
> };
>
> cpu4: cpu@100 {
> @@ -130,8 +137,9 @@ cpu4: cpu@100 {
> compatible = "arm,cortex-a55";
> reg = <0x100>;
> enable-method = "psci";
> - clocks = <&cmu_cpucl1 CLK_CLUSTER1_SCLK>;
> - clock-names = "cluster1_clk";
> + clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL1>;
> + clock-names = "cpucl1";
> + operating-points-v2 = <&cpucl1_opp_table>;
> };
>
> cpu5: cpu@101 {
> @@ -139,6 +147,8 @@ cpu5: cpu@101 {
> compatible = "arm,cortex-a55";
> reg = <0x101>;
> enable-method = "psci";
> + clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL1>;
> + operating-points-v2 = <&cpucl1_opp_table>;
> };
>
> cpu6: cpu@102 {
> @@ -146,6 +156,8 @@ cpu6: cpu@102 {
> compatible = "arm,cortex-a55";
> reg = <0x102>;
> enable-method = "psci";
> + clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL1>;
> + operating-points-v2 = <&cpucl1_opp_table>;
> };
>
> cpu7: cpu@103 {
> @@ -153,6 +165,210 @@ cpu7: cpu@103 {
> compatible = "arm,cortex-a55";
> reg = <0x103>;
> enable-method = "psci";
> + clocks = <&acpm_ipc EXYNOS850_CLK_ACPM_DVFS_CPUCL1>;
> + operating-points-v2 = <&cpucl1_opp_table>;
> + };
> + };
> +
> + cpucl0_opp_table: opp-table-0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-130000000 {
> + opp-hz = /bits/ 64 <130000000>;
> + opp-microvolt = <625000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-182000000 {
> + opp-hz = /bits/ 64 <182000000>;
> + opp-microvolt = <625000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-247000000 {
> + opp-hz = /bits/ 64 <247000000>;
> + opp-microvolt = <625000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-351000000 {
> + opp-hz = /bits/ 64 <351000000>;
> + opp-microvolt = <625000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-442000000 {
> + opp-hz = /bits/ 64 <442000000>;
> + opp-microvolt = <625000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-546000000 {
> + opp-hz = /bits/ 64 <546000000>;
> + opp-microvolt = <625000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-650000000 {
> + opp-hz = /bits/ 64 <650000000>;
> + opp-microvolt = <625000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-806000000 {
> + opp-hz = /bits/ 64 <806000000>;
> + opp-microvolt = <656250>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-949000000 {
> + opp-hz = /bits/ 64 <949000000>;
> + opp-microvolt = <681250>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-1053000000 {
> + opp-hz = /bits/ 64 <1053000000>;
> + opp-microvolt = <706250>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-1157000000 {
> + opp-hz = /bits/ 64 <1157000000>;
> + opp-microvolt = <737500>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-1300000000 {
> + opp-hz = /bits/ 64 <1300000000>;
> + opp-microvolt = <781250>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-1456000000 {
> + opp-hz = /bits/ 64 <1456000000>;
> + opp-microvolt = <825000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-1586000000 {
> + opp-hz = /bits/ 64 <1586000000>;
> + opp-microvolt = <875000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-1742000000 {
> + opp-hz = /bits/ 64 <1742000000>;
> + opp-microvolt = <937500>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-1846000000 {
> + opp-hz = /bits/ 64 <1846000000>;
> + opp-microvolt = <981250>;
> + clock-latency-ns = <500000>;
> + };
> + };
> +
> + cpucl1_opp_table: opp-table-1 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-130000000 {
> + opp-hz = /bits/ 64 <130000000>;
> + opp-microvolt = <625000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-182000000 {
> + opp-hz = /bits/ 64 <182000000>;
> + opp-microvolt = <625000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-247000000 {
> + opp-hz = /bits/ 64 <247000000>;
> + opp-microvolt = <625000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-351000000 {
> + opp-hz = /bits/ 64 <351000000>;
> + opp-microvolt = <625000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-442000000 {
> + opp-hz = /bits/ 64 <442000000>;
> + opp-microvolt = <625000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-546000000 {
> + opp-hz = /bits/ 64 <546000000>;
> + opp-microvolt = <625000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-650000000 {
> + opp-hz = /bits/ 64 <650000000>;
> + opp-microvolt = <625000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-806000000 {
> + opp-hz = /bits/ 64 <806000000>;
> + opp-microvolt = <656250>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-949000000 {
> + opp-hz = /bits/ 64 <949000000>;
> + opp-microvolt = <681250>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-1053000000 {
> + opp-hz = /bits/ 64 <1053000000>;
> + opp-microvolt = <706250>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-1157000000 {
> + opp-hz = /bits/ 64 <1157000000>;
> + opp-microvolt = <737500>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-1300000000 {
> + opp-hz = /bits/ 64 <1300000000>;
> + opp-microvolt = <781250>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-1456000000 {
> + opp-hz = /bits/ 64 <1456000000>;
> + opp-microvolt = <825000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-1586000000 {
> + opp-hz = /bits/ 64 <1586000000>;
> + opp-microvolt = <875000>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-1742000000 {
> + opp-hz = /bits/ 64 <1742000000>;
> + opp-microvolt = <937500>;
> + clock-latency-ns = <500000>;
> + };
> +
> + opp-1846000000 {
> + opp-hz = /bits/ 64 <1846000000>;
> + opp-microvolt = <981250>;
> + clock-latency-ns = <500000>;
> };
> };
>
>
> --
> 2.51.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 0/2] Exynos850: Add ACPM node and enable cpufreq
2026-09-29 3:10 [PATCH 0/2] Exynos850: Add ACPM node and enable cpufreq Alexey Klimov
2026-09-29 3:10 ` [PATCH 1/2] arm64: dts: exynos850: Add ACPM firmware node Alexey Klimov
2026-09-29 3:10 ` [PATCH 2/2] arm64: dts: exynos850: Add operating points for CPUs and enable cpufreq Alexey Klimov
@ 2026-10-03 14:05 ` Krzysztof Kozlowski
2 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2026-10-03 14:05 UTC (permalink / raw)
To: Alexey Klimov, Sam Protsenko, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Peter Griffin, Alim Akhtar
Cc: Thomas Turner, Tudor Ambarus, linux-samsung-soc,
linux-arm-kernel, devicetree, linux-kernel
On 29/09/2026 05:10, Alexey Klimov wrote:
> The dependency for this series is:
> https://lore.kernel.org/linux-samsung-soc/20260929-exynos850-acpm-firmware-support-v3-0-473a69fc8a3d@linaro.org/
This means it cannot be merged and will wait a cycle. But then also why
are you breaking users of this DTS? Applying the driver won't solve
anything - DTS is in general supposed to work, even without driver
changes. More over, commit msg should explain that.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-10-03 14:05 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-09-29 3:10 [PATCH 0/2] Exynos850: Add ACPM node and enable cpufreq Alexey Klimov
2026-09-29 3:10 ` [PATCH 1/2] arm64: dts: exynos850: Add ACPM firmware node Alexey Klimov
2026-09-29 9:02 ` Tudor Ambarus
2026-09-30 11:54 ` Alexey Klimov
2026-10-01 13:27 ` Tudor Ambarus
2026-09-29 3:10 ` [PATCH 2/2] arm64: dts: exynos850: Add operating points for CPUs and enable cpufreq Alexey Klimov
2026-10-02 14:40 ` Peter Griffin
2026-10-03 14:05 ` [PATCH 0/2] Exynos850: Add ACPM node " Krzysztof Kozlowski
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®