[PATCH 0/4] mmc: mmci: updates for STM32MP13

[PATCH 0/4] mmc: mmci: updates for STM32MP13

[Yann Gautier]

The new STmicroelectronics STM32MP13 SoC embeds a new version
of the SDMMC peripheral (v2.2).
It supports SDR104 and HS200 modes.

Yann Gautier (4):
  mmc: mmci: Add support for sdmmc variant revision v2.2
  mmc: mmci: increase stm32 sdmmcv2 clock max freq
  mmc: mmci: stm32: clear DLYB_CR after sending tuning command
  mmc: mmci: add hs200 support for stm32 sdmmc

 drivers/mmc/host/mmci.c             | 7 ++++++-
 drivers/mmc/host/mmci_stm32_sdmmc.c | 7 +++++--
 2 files changed, 11 insertions(+), 3 deletions(-)

-- 
2.17.1

[PATCH 1/4] mmc: mmci: Add support for sdmmc variant revision v2.2

[Yann Gautier]

The change is only hardware, and does not need driver change:
Added hardware flow control during transmit packet with variable delay.
The new id is then added to the ids list structure.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
---
 drivers/mmc/host/mmci.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index c9cacd4d5b22..c0478dfa61b9 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -2435,6 +2435,11 @@ static const struct amba_id mmci_ids[] = {
 		.mask	= 0xf0ffffff,
 		.data	= &variant_stm32_sdmmcv2,
 	},
+	{
+		.id     = 0x20253180,
+		.mask	= 0xf0ffffff,
+		.data	= &variant_stm32_sdmmcv2,
+	},
 	/* Qualcomm variants */
 	{
 		.id     = 0x00051180,
-- 
2.17.1

[PATCH 2/4] mmc: mmci: increase stm32 sdmmcv2 clock max freq

[Yann Gautier]

The variant->f_max is dependent on the IP, not on the SoC where it is
embedded. Set the max frequency of its source clock to 267MHz.
The frequency used will be limited by the IOs max frequency, set in the
SoC device tree.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
---
 drivers/mmc/host/mmci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index c0478dfa61b9..45b8608c935c 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -280,7 +280,7 @@ static struct variant_data variant_stm32_sdmmc = {
 static struct variant_data variant_stm32_sdmmcv2 = {
 	.fifosize		= 16 * 4,
 	.fifohalfsize		= 8 * 4,
-	.f_max			= 208000000,
+	.f_max			= 267000000,
 	.stm32_clkdiv		= true,
 	.cmdreg_cpsm_enable	= MCI_CPSM_STM32_ENABLE,
 	.cmdreg_lrsp_crc	= MCI_CPSM_STM32_LRSP_CRC,
-- 
2.17.1

[PATCH 3/4] mmc: mmci: stm32: clear DLYB_CR after sending tuning command

[Yann Gautier]

During test campaign, and especially after several unbind/bind sequences,
it has been seen that the SD-card on SDMMC1 thread could freeze.
The freeze always appear on a CMD23 following a CMD19.
Checking SDMMC internal registers shows that the tuning command (CMD19)
has failed.
The freeze is then due to the delay block involved in the tuning sequence.
To correct this, clear the delay block register DLYB_CR register after
the tuning commands.

Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
---
 drivers/mmc/host/mmci_stm32_sdmmc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c b/drivers/mmc/host/mmci_stm32_sdmmc.c
index fdaa11f92fe6..a75d3dd34d18 100644
--- a/drivers/mmc/host/mmci_stm32_sdmmc.c
+++ b/drivers/mmc/host/mmci_stm32_sdmmc.c
@@ -441,6 +441,8 @@ static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode)
 		return -EINVAL;
 	}
 
+	writel_relaxed(0, dlyb->base + DLYB_CR);
+
 	phase = end_of_len - max_len / 2;
 	sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
 
-- 
2.17.1

Re: [PATCH 3/4] mmc: mmci: stm32: clear DLYB_CR after sending tuning command

[Marek Vasut]

On 12/15/21 15:17, Yann Gautier wrote:
> During test campaign, and especially after several unbind/bind sequences,
> it has been seen that the SD-card on SDMMC1 thread could freeze.
> The freeze always appear on a CMD23 following a CMD19.
> Checking SDMMC internal registers shows that the tuning command (CMD19)
> has failed.
> The freeze is then due to the delay block involved in the tuning sequence.
> To correct this, clear the delay block register DLYB_CR register after
> the tuning commands.
> 
> Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
> ---
>   drivers/mmc/host/mmci_stm32_sdmmc.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c b/drivers/mmc/host/mmci_stm32_sdmmc.c
> index fdaa11f92fe6..a75d3dd34d18 100644
> --- a/drivers/mmc/host/mmci_stm32_sdmmc.c
> +++ b/drivers/mmc/host/mmci_stm32_sdmmc.c
> @@ -441,6 +441,8 @@ static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode)
>   		return -EINVAL;
>   	}
>   
> +	writel_relaxed(0, dlyb->base + DLYB_CR);
> +
>   	phase = end_of_len - max_len / 2;
>   	sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);

Shouldn't this have a Fixes: tag and be CC stable ?
This seems like a bugfix, no ?

Re: [PATCH 3/4] mmc: mmci: stm32: clear DLYB_CR after sending tuning command

[Yann Gautier]

On 12/16/21 10:13 AM, Marek Vasut wrote:
> On 12/15/21 15:17, Yann Gautier wrote:
>> During test campaign, and especially after several unbind/bind sequences,
>> it has been seen that the SD-card on SDMMC1 thread could freeze.
>> The freeze always appear on a CMD23 following a CMD19.
>> Checking SDMMC internal registers shows that the tuning command (CMD19)
>> has failed.
>> The freeze is then due to the delay block involved in the tuning 
>> sequence.
>> To correct this, clear the delay block register DLYB_CR register after
>> the tuning commands.
>>
>> Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
>> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
>> ---
>>   drivers/mmc/host/mmci_stm32_sdmmc.c | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c 
>> b/drivers/mmc/host/mmci_stm32_sdmmc.c
>> index fdaa11f92fe6..a75d3dd34d18 100644
>> --- a/drivers/mmc/host/mmci_stm32_sdmmc.c
>> +++ b/drivers/mmc/host/mmci_stm32_sdmmc.c
>> @@ -441,6 +441,8 @@ static int sdmmc_dlyb_phase_tuning(struct 
>> mmci_host *host, u32 opcode)
>>           return -EINVAL;
>>       }
>> +    writel_relaxed(0, dlyb->base + DLYB_CR);
>> +
>>       phase = end_of_len - max_len / 2;
>>       sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
> 
> Shouldn't this have a Fixes: tag and be CC stable ?
> This seems like a bugfix, no ?

Hi Marek,

You're right, I should have added:
Fixes: 1103f807a3b9 ("mmc: mmci_sdmmc: Add execute tuning with delay block")

Ulf, could you manage that, or should I push a new version?


Best regards,
Yann

Re: [PATCH 3/4] mmc: mmci: stm32: clear DLYB_CR after sending tuning command

[Ulf Hansson]

On Thu, 16 Dec 2021 at 10:49, Yann Gautier <yann.gautier@foss.st.com> wrote:
>
> On 12/16/21 10:13 AM, Marek Vasut wrote:
> > On 12/15/21 15:17, Yann Gautier wrote:
> >> During test campaign, and especially after several unbind/bind sequences,
> >> it has been seen that the SD-card on SDMMC1 thread could freeze.
> >> The freeze always appear on a CMD23 following a CMD19.
> >> Checking SDMMC internal registers shows that the tuning command (CMD19)
> >> has failed.
> >> The freeze is then due to the delay block involved in the tuning
> >> sequence.
> >> To correct this, clear the delay block register DLYB_CR register after
> >> the tuning commands.
> >>
> >> Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
> >> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
> >> ---
> >>   drivers/mmc/host/mmci_stm32_sdmmc.c | 2 ++
> >>   1 file changed, 2 insertions(+)
> >>
> >> diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c
> >> b/drivers/mmc/host/mmci_stm32_sdmmc.c
> >> index fdaa11f92fe6..a75d3dd34d18 100644
> >> --- a/drivers/mmc/host/mmci_stm32_sdmmc.c
> >> +++ b/drivers/mmc/host/mmci_stm32_sdmmc.c
> >> @@ -441,6 +441,8 @@ static int sdmmc_dlyb_phase_tuning(struct
> >> mmci_host *host, u32 opcode)
> >>           return -EINVAL;
> >>       }
> >> +    writel_relaxed(0, dlyb->base + DLYB_CR);
> >> +
> >>       phase = end_of_len - max_len / 2;
> >>       sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
> >
> > Shouldn't this have a Fixes: tag and be CC stable ?
> > This seems like a bugfix, no ?
>
> Hi Marek,
>
> You're right, I should have added:
> Fixes: 1103f807a3b9 ("mmc: mmci_sdmmc: Add execute tuning with delay block")
>
> Ulf, could you manage that, or should I push a new version?

Patch applied for fixes and by adding a stable tag too, thanks!

Kind regards
Uffe

[PATCH 4/4] mmc: mmci: add hs200 support for stm32 sdmmc

[Yann Gautier]

Use feedback clock for HS200 mode, as for SDR104.
The HS200 mode can be enabled through DT by using mmc-hs200-1_8v.
It is possible to use it on STM32MP13, but not STM32MP15 platforms.

Signed-off-by: Ludovic Barre <ludovic.barre@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
---
 drivers/mmc/host/mmci_stm32_sdmmc.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c b/drivers/mmc/host/mmci_stm32_sdmmc.c
index a75d3dd34d18..9c13f2c31365 100644
--- a/drivers/mmc/host/mmci_stm32_sdmmc.c
+++ b/drivers/mmc/host/mmci_stm32_sdmmc.c
@@ -241,11 +241,12 @@ static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired)
 
 	/*
 	 * SDMMC_FBCK is selected when an external Delay Block is needed
-	 * with SDR104.
+	 * with SDR104 or HS200.
 	 */
 	if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) {
 		clk |= MCI_STM32_CLK_BUSSPEED;
-		if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) {
+		if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104 ||
+		    host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
 			clk &= ~MCI_STM32_CLK_SEL_MSK;
 			clk |= MCI_STM32_CLK_SELFBCK;
 		}
-- 
2.17.1

Re: [PATCH 4/4] mmc: mmci: add hs200 support for stm32 sdmmc

[Marek Vasut]

On 12/15/21 15:17, Yann Gautier wrote:
> Use feedback clock for HS200 mode, as for SDR104.
> The HS200 mode can be enabled through DT by using mmc-hs200-1_8v.
> It is possible to use it on STM32MP13, but not STM32MP15 platforms.

HS200 is possible even on the MP15, it just doesn't yield any 
(performance) benefits due to the slower bus clock (125 MHz or so?), so 
it isn't worth enabling it on MP15. It is nice to see MP13 can do better.

Re: [PATCH 4/4] mmc: mmci: add hs200 support for stm32 sdmmc

[Yann Gautier]

On 12/16/21 10:14 AM, Marek Vasut wrote:
> On 12/15/21 15:17, Yann Gautier wrote:
>> Use feedback clock for HS200 mode, as for SDR104.
>> The HS200 mode can be enabled through DT by using mmc-hs200-1_8v.
>> It is possible to use it on STM32MP13, but not STM32MP15 platforms.
> 
> HS200 is possible even on the MP15, it just doesn't yield any 
> (performance) benefits due to the slower bus clock (125 MHz or so?), so 
> it isn't worth enabling it on MP15. It is nice to see MP13 can do better.

Hi Marek,

There is a limitation on MP15, please see errata sheet [1], chapter 2.3.19.
HS200 (and SDR104) shouldn't be enabled on MP15.

Best regards,
Yann

[1] https://www.st.com/resource/en/errata_sheet/dm00516256.pdf

Re: [PATCH 4/4] mmc: mmci: add hs200 support for stm32 sdmmc

[Marek Vasut]

On 12/16/21 10:44, Yann Gautier wrote:
> On 12/16/21 10:14 AM, Marek Vasut wrote:
>> On 12/15/21 15:17, Yann Gautier wrote:
>>> Use feedback clock for HS200 mode, as for SDR104.
>>> The HS200 mode can be enabled through DT by using mmc-hs200-1_8v.
>>> It is possible to use it on STM32MP13, but not STM32MP15 platforms.
>>
>> HS200 is possible even on the MP15, it just doesn't yield any 
>> (performance) benefits due to the slower bus clock (125 MHz or so?), 
>> so it isn't worth enabling it on MP15. It is nice to see MP13 can do 
>> better.
> 
> Hi Marek,
> 
> There is a limitation on MP15, please see errata sheet [1], chapter 2.3.19.
> HS200 (and SDR104) shouldn't be enabled on MP15.
> 
> Best regards,
> Yann
> 
> [1] https://www.st.com/resource/en/errata_sheet/dm00516256.pdf

Oh, I see, so I was lucky to even ever get it working at all.

Thanks for the info.

Re: [PATCH 0/4] mmc: mmci: updates for STM32MP13

[Linus Walleij]

On Wed, Dec 15, 2021 at 3:18 PM Yann Gautier <yann.gautier@foss.st.com> wrote:

> The new STmicroelectronics STM32MP13 SoC embeds a new version
> of the SDMMC peripheral (v2.2).
> It supports SDR104 and HS200 modes.

Patches look good to me!
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [PATCH 0/4] mmc: mmci: updates for STM32MP13

[Ulf Hansson]

On Wed, 15 Dec 2021 at 15:18, Yann Gautier <yann.gautier@foss.st.com> wrote:
>
> The new STmicroelectronics STM32MP13 SoC embeds a new version
> of the SDMMC peripheral (v2.2).
> It supports SDR104 and HS200 modes.
>
> Yann Gautier (4):
>   mmc: mmci: Add support for sdmmc variant revision v2.2
>   mmc: mmci: increase stm32 sdmmcv2 clock max freq
>   mmc: mmci: stm32: clear DLYB_CR after sending tuning command
>   mmc: mmci: add hs200 support for stm32 sdmmc
>
>  drivers/mmc/host/mmci.c             | 7 ++++++-
>  drivers/mmc/host/mmci_stm32_sdmmc.c | 7 +++++--
>  2 files changed, 11 insertions(+), 3 deletions(-)
>
> --
> 2.17.1
>

Patch 1, 2 and 4, applied for next, thanks!

Kind regards
Uffe