* [PATCH v9 0/4] thermal: renesas: Add support for RZ/G3E
@ 2025-09-17 17:01 John Madieu
2025-09-17 17:01 ` [PATCH v9 1/4] dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit John Madieu
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: John Madieu @ 2025-09-17 17:01 UTC (permalink / raw)
To: conor+dt, daniel.lezcano, geert+renesas, krzk+dt, lukasz.luba,
magnus.damm, mturquette, robh, rui.zhang, sboyd, will
Cc: biju.das.jz, catalin.marinas, devicetree, john.madieu,
linux-arm-kernel, linux-kernel, linux-pm, linux-renesas-soc,
p.zabel, rafael, John Madieu
This series adds support for the temperature sensor unit (TSU) found on the
Renesas RZ/G3E SoC.
The initial syscon patch [1] the series depends on has already been accepted.
Changes:
v9:
* Remove driver-specific read/write indirection and use readl/writel
* Use devm_mutex_init()
* Switch to syscon_regmap_lookup_by_phandle_args()
v8:
* Use of_parse_phandle_with_fixed_args() for trim values
* Update binding doc and collect Rb tag from Rob
* Use millidegree computation to for better precision
v6 -> v7
* Update DTS trim priperty name and specifier, updading the documentation
accordingly
* Refactor main driver: remove spinlock usage, using polling timeout as computed
from datasheet. Also use polling for get_temp() while using IRQ for trip-point
cross detection, and finally add both runtime and sleep PM support.
* Add new patch to update sys #address-cells as trim specifier now requires an
offset from sys base
v5 -> v6
* Minor typo fix
* Constify regmap config in patch 1/5
v4 -> v5
* Remove useless curly braces on single line-protected scoped guards
v3 -> v4
* Improve commit messages
v2 -> v3
* Remove useless 'renesas,tsu-operating-mode' property
v1 -> v2
* Fix yaml warnings from dt-binding
* Update IRQ names to reflect TSU expectations
Regards,
[1] https://lore.kernel.org/linux-devicetree/20250818162859.9661-2-john.madieu.xa@bp.renesas.com/
John Madieu (4):
dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit
thermal: renesas: rzg3e: Add thermal driver for the Renesas RZ/G3E SoC
arm64: dts: renesas: r9a09g047: Add TSU node
arm64: defconfig: Enable the Renesas RZ/G3E thermal driver
.../thermal/renesas,r9a09g047-tsu.yaml | 87 +++
MAINTAINERS | 7 +
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 48 ++
arch/arm64/configs/defconfig | 1 +
drivers/thermal/renesas/Kconfig | 7 +
drivers/thermal/renesas/Makefile | 1 +
drivers/thermal/renesas/rzg3e_thermal.c | 547 ++++++++++++++++++
7 files changed, 698 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
create mode 100644 drivers/thermal/renesas/rzg3e_thermal.c
--
2.25.1
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v9 1/4] dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit 2025-09-17 17:01 [PATCH v9 0/4] thermal: renesas: Add support for RZ/G3E John Madieu @ 2025-09-17 17:01 ` John Madieu 2025-09-17 17:01 ` [PATCH v9 2/4] thermal: renesas: rzg3e: Add thermal driver for the Renesas RZ/G3E SoC John Madieu ` (3 subsequent siblings) 4 siblings, 0 replies; 11+ messages in thread From: John Madieu @ 2025-09-17 17:01 UTC (permalink / raw) To: conor+dt, daniel.lezcano, geert+renesas, krzk+dt, lukasz.luba, magnus.damm, mturquette, robh, rui.zhang, sboyd, will Cc: biju.das.jz, catalin.marinas, devicetree, john.madieu, linux-arm-kernel, linux-kernel, linux-pm, linux-renesas-soc, p.zabel, rafael, John Madieu The Renesas RZ/G3E SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The device provides real-time temperature measurements for thermal management, utilizing a single dedicated channel (channel 1) for temperature sensing. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> --- Changes: v1 -> v2: * Fixes reg property specifier to get rid of yamlint warnings * Fixes IRQ name to reflect TSU expectations v2 -> v3: * Removees useless 'renesas,tsu-operating-mode' property v3 -> v4: * Fixes commit message * Fixes interrupt description * Removes trip point definition v5: no changes v6: no changes v7: Adds documentation for 'renesas,tsu-trim' and removes Rb tag from Krzysztof due to this change v8: Address Rob's comments (about node naming and line wrapping) and collect Rb tag v9: No changes .../thermal/renesas,r9a09g047-tsu.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml new file mode 100644 index 000000000000..8d3f3c24f0f2 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/renesas,r9a09g047-tsu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3E Temperature Sensor Unit (TSU) + +maintainers: + - John Madieu <john.madieu.xa@bp.renesas.com> + +description: + The Temperature Sensor Unit (TSU) is an integrated thermal sensor that + monitors the chip temperature on the Renesas RZ/G3E SoC. The TSU provides + real-time temperature measurements for thermal management. + +properties: + compatible: + const: renesas,r9a09g047-tsu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + interrupts: + items: + - description: Conversion complete interrupt signal (pulse) + - description: Comparison result interrupt signal (level) + + interrupt-names: + items: + - const: adi + - const: adcmpi + + "#thermal-sensor-cells": + const: 0 + + renesas,tsu-trim: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to system controller + - description: offset of trim registers + description: + Phandle and offset to the system controller containing the TSU + calibration trim values. The offset points to the first trim register + (OTPTSU1TRMVAL0), with the second trim register (OTPTSU1TRMVAL1) located + at offset + 4. + +required: + - compatible + - reg + - clocks + - resets + - power-domains + - interrupts + - interrupt-names + - "#thermal-sensor-cells" + - renesas,tsu-trim + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/renesas,r9a09g047-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + thermal-sensor@14002000 { + compatible = "renesas,r9a09g047-tsu"; + reg = <0x14002000 0x1000>; + clocks = <&cpg CPG_MOD 0x10a>; + resets = <&cpg 0xf8>; + power-domains = <&cpg>; + interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "adi", "adcmpi"; + #thermal-sensor-cells = <0>; + renesas,tsu-trim = <&sys 0x330>; + }; -- 2.25.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v9 2/4] thermal: renesas: rzg3e: Add thermal driver for the Renesas RZ/G3E SoC 2025-09-17 17:01 [PATCH v9 0/4] thermal: renesas: Add support for RZ/G3E John Madieu 2025-09-17 17:01 ` [PATCH v9 1/4] dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit John Madieu @ 2025-09-17 17:01 ` John Madieu 2025-09-19 17:06 ` Biju Das 2025-09-17 17:01 ` [PATCH v9 3/4] arm64: dts: renesas: r9a09g047: Add TSU node John Madieu ` (2 subsequent siblings) 4 siblings, 1 reply; 11+ messages in thread From: John Madieu @ 2025-09-17 17:01 UTC (permalink / raw) To: conor+dt, daniel.lezcano, geert+renesas, krzk+dt, lukasz.luba, magnus.damm, mturquette, robh, rui.zhang, sboyd, will Cc: biju.das.jz, catalin.marinas, devicetree, john.madieu, linux-arm-kernel, linux-kernel, linux-pm, linux-renesas-soc, p.zabel, rafael, John Madieu The RZ/G3E SoC integrates a Temperature Sensor Unit (TSU) block designed to monitor the chip's junction temperature. This sensor is connected to channel 1 of the APB port clock/reset and provides temperature measurements. It also requires calibration values stored in the system controller registers for accurate temperature measurement. Add a driver for the Renesas RZ/G3E TSU. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> --- Changes: v1 -> v2: fixes IRQ names v2 -> v3: no changes v3 -> v4: no changes v5: Removed curly braces arround single-line protected scoped guards v6: Clarified comments in driver v7: Refactored driver structure: - removes splinlock usage - updates polling timeout as per the datasheet - uses average mode to be more accurate - uses polling (faster than irq mode) for get_temp() while keeping IRQ for hw trip-point cross detection. - adds both runtime and sleep PM support v8: - Use of_parse_phandle_with_fixed_args() for trim values - Use millidegree computation to for better precision v9: - Remove driver-specific read/write indirection and use readl/writel - Use devm_mutex_init() - Switch to syscon_regmap_lookup_by_phandle_args() MAINTAINERS | 7 + drivers/thermal/renesas/Kconfig | 7 + drivers/thermal/renesas/Makefile | 1 + drivers/thermal/renesas/rzg3e_thermal.c | 547 ++++++++++++++++++++++++ 4 files changed, 562 insertions(+) create mode 100644 drivers/thermal/renesas/rzg3e_thermal.c diff --git a/MAINTAINERS b/MAINTAINERS index 10614ca41ed0..5480412f556d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21544,6 +21544,13 @@ S: Maintained F: Documentation/devicetree/bindings/iio/potentiometer/renesas,x9250.yaml F: drivers/iio/potentiometer/x9250.c +RENESAS RZ/G3E THERMAL SENSOR UNIT DRIVER +M: John Madieu <john.madieu.xa@bp.renesas.com> +L: linux-pm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml +F: drivers/thermal/renesas/rzg3e_thermal.c + RESET CONTROLLER FRAMEWORK M: Philipp Zabel <p.zabel@pengutronix.de> S: Maintained diff --git a/drivers/thermal/renesas/Kconfig b/drivers/thermal/renesas/Kconfig index dcf5fc5ae08e..10cf90fc4bfa 100644 --- a/drivers/thermal/renesas/Kconfig +++ b/drivers/thermal/renesas/Kconfig @@ -26,3 +26,10 @@ config RZG2L_THERMAL help Enable this to plug the RZ/G2L thermal sensor driver into the Linux thermal framework. + +config RZG3E_THERMAL + tristate "Renesas RZ/G3E thermal driver" + depends on ARCH_RENESAS || COMPILE_TEST + help + Enable this to plug the RZ/G3E thermal sensor driver into the Linux + thermal framework. diff --git a/drivers/thermal/renesas/Makefile b/drivers/thermal/renesas/Makefile index bf9cb3cb94d6..5a3eba0dedd0 100644 --- a/drivers/thermal/renesas/Makefile +++ b/drivers/thermal/renesas/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_RCAR_GEN3_THERMAL) += rcar_gen3_thermal.o obj-$(CONFIG_RCAR_THERMAL) += rcar_thermal.o obj-$(CONFIG_RZG2L_THERMAL) += rzg2l_thermal.o +obj-$(CONFIG_RZG3E_THERMAL) += rzg3e_thermal.o diff --git a/drivers/thermal/renesas/rzg3e_thermal.c b/drivers/thermal/renesas/rzg3e_thermal.c new file mode 100644 index 000000000000..e66d73ca6752 --- /dev/null +++ b/drivers/thermal/renesas/rzg3e_thermal.c @@ -0,0 +1,547 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G3E TSU Temperature Sensor Unit + * + * Copyright (C) 2025 Renesas Electronics Corporation + */ +#include <linux/clk.h> +#include <linux/cleanup.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <linux/reset.h> +#include <linux/thermal.h> +#include <linux/units.h> + +#include "../thermal_hwmon.h" + +/* TSU Register offsets and bits */ +#define TSU_SSUSR 0x00 +#define TSU_SSUSR_EN_TS BIT(0) +#define TSU_SSUSR_ADC_PD_TS BIT(1) +#define TSU_SSUSR_SOC_TS_EN BIT(2) + +#define TSU_STRGR 0x04 +#define TSU_STRGR_ADST BIT(0) + +#define TSU_SOSR1 0x08 +#define TSU_SOSR1_ADCT_8 0x03 +#define TSU_SOSR1_ADCS BIT(4) +#define TSU_SOSR1_OUTSEL BIT(9) + +#define TSU_SCRR 0x10 +#define TSU_SCRR_OUT12BIT_TS GENMASK(11, 0) + +#define TSU_SSR 0x14 +#define TSU_SSR_CONV BIT(0) + +#define TSU_CMSR 0x18 +#define TSU_CMSR_CMPEN BIT(0) + +#define TSU_LLSR 0x1C +#define TSU_ULSR 0x20 + +#define TSU_SISR 0x30 +#define TSU_SISR_ADF BIT(0) +#define TSU_SISR_CMPF BIT(1) + +#define TSU_SIER 0x34 +#define TSU_SIER_CMPIE BIT(1) + +#define TSU_SICR 0x38 +#define TSU_SICR_ADCLR BIT(0) +#define TSU_SICR_CMPCLR BIT(1) + +/* Temperature calculation constants from datasheet */ +#define TSU_TEMP_D (-41) +#define TSU_TEMP_E 126 +#define TSU_CODE_MAX 0xFFF + +/* Timing specifications from datasheet */ +#define TSU_POWERUP_TIME_US 120 /* 120T at 1MHz sensor clock per datasheet */ +#define TSU_CONV_TIME_US 50 /* Per sample conversion time */ +#define TSU_POLL_DELAY_US 10 /* Polling interval */ +#define TSU_MIN_CLOCK_RATE 24000000 /* TSU_PCLK minimum 24MHz */ + +/** + * struct rzg3e_thermal_priv - RZ/G3E TSU private data + * @base: TSU register base + * @dev: device pointer + * @syscon: regmap for calibration values + * @zone: thermal zone device + * @rstc: reset control + * @trmval0: calibration value 0 (b) + * @trmval1: calibration value 1 (c) + * @trim_offset: offset for trim registers in syscon + * @lock: protects hardware access during conversions + */ +struct rzg3e_thermal_priv { + void __iomem *base; + struct device *dev; + struct regmap *syscon; + struct thermal_zone_device *zone; + struct reset_control *rstc; + u16 trmval0; + u16 trmval1; + u32 trim_offset; + struct mutex lock; +}; + +static int rzg3e_thermal_power_on(struct rzg3e_thermal_priv *priv) +{ + u32 val; + int ret; + + /* Clear any pending interrupts */ + writel(TSU_SICR_ADCLR | TSU_SICR_CMPCLR, priv->base + TSU_SICR); + + /* Disable all interrupts during setup */ + writel(0, priv->base + TSU_SIER); + + /* + * Power-on sequence per datasheet 7.11.9.1: + * SOC_TS_EN must be set at same time or before EN_TS and ADC_PD_TS + */ + val = TSU_SSUSR_SOC_TS_EN | TSU_SSUSR_EN_TS; + writel(val, priv->base + TSU_SSUSR); + + /* Wait for sensor stabilization per datasheet 7.11.7.1 */ + usleep_range(TSU_POWERUP_TIME_US, TSU_POWERUP_TIME_US + 10); + + /* Configure for average mode with 8 samples */ + val = TSU_SOSR1_OUTSEL | TSU_SOSR1_ADCT_8; + writel(val, priv->base + TSU_SOSR1); + + /* Ensure we're in single scan mode (default) */ + val = readl(priv->base + TSU_SOSR1); + if (val & TSU_SOSR1_ADCS) { + dev_err(priv->dev, "Invalid scan mode setting\n"); + return -EINVAL; + } + + /* Wait for any ongoing conversion to complete */ + ret = readl_poll_timeout(priv->base + TSU_SSR, val, + !(val & TSU_SSR_CONV), + TSU_POLL_DELAY_US, + USEC_PER_MSEC); + if (ret) { + dev_err(priv->dev, "Timeout waiting for conversion\n"); + return ret; + } + + return 0; +} + +static void rzg3e_thermal_power_off(struct rzg3e_thermal_priv *priv) +{ + /* Disable all interrupts */ + writel(0, priv->base + TSU_SIER); + + /* Clear pending interrupts */ + writel(TSU_SICR_ADCLR | TSU_SICR_CMPCLR, priv->base + TSU_SICR); + + /* Power down sequence per datasheet */ + writel(TSU_SSUSR_ADC_PD_TS, priv->base + TSU_SSUSR); +} + +/* + * Convert 12-bit sensor code to temperature in millicelsius + * Formula from datasheet 7.11.7.8: + * T(°C) = ((e - d) / (c - b)) * (a - b) + d + * where: a = sensor code, b = trmval0, c = trmval1, d = -41, e = 126 + */ +static int rzg3e_thermal_code_to_temp(struct rzg3e_thermal_priv *priv, u16 code) +{ + int temp_e_mc = TSU_TEMP_E * MILLIDEGREE_PER_DEGREE; + int temp_d_mc = TSU_TEMP_D * MILLIDEGREE_PER_DEGREE; + s64 numerator, denominator; + int temp_mc; + + numerator = (temp_e_mc - temp_d_mc) * (s64)(code - priv->trmval0); + denominator = priv->trmval1 - priv->trmval0; + + temp_mc = div64_s64(numerator, denominator) + temp_d_mc; + + return clamp(temp_mc, temp_d_mc, temp_e_mc); +} + +/* + * Convert temperature in millicelsius to 12-bit sensor code + * Formula from datasheet 7.11.7.9 (inverse of above) + */ +static u16 rzg3e_thermal_temp_to_code(struct rzg3e_thermal_priv *priv, int temp_mc) +{ + int temp_e_mc = TSU_TEMP_E * MILLIDEGREE_PER_DEGREE; + int temp_d_mc = TSU_TEMP_D * MILLIDEGREE_PER_DEGREE; + s64 numerator, denominator; + s64 code; + + numerator = (temp_mc - temp_d_mc) * (priv->trmval1 - priv->trmval0); + denominator = temp_e_mc - temp_d_mc; + + code = div64_s64(numerator, denominator) + priv->trmval0; + + return clamp_val(code, 0, TSU_CODE_MAX); +} + +static int rzg3e_thermal_get_temp(struct thermal_zone_device *tz, int *temp) +{ + struct rzg3e_thermal_priv *priv = thermal_zone_device_priv(tz); + u32 status, code; + int ret, timeout; + + ret = pm_runtime_resume_and_get(priv->dev); + if (ret < 0) + return ret; + + guard(mutex)(&priv->lock); + + /* Clear any previous conversion status */ + writel(TSU_SICR_ADCLR, priv->base + TSU_SICR); + + /* Start single conversion */ + writel(TSU_STRGR_ADST, priv->base + TSU_STRGR); + + /* Wait for conversion completion - 8 samples at ~50us each */ + timeout = TSU_CONV_TIME_US * 8 * 2; /* Double for margin */ + ret = readl_poll_timeout(priv->base + TSU_SISR, status, + status & TSU_SISR_ADF, + TSU_POLL_DELAY_US, timeout); + if (ret) { + dev_err(priv->dev, "Conversion timeout (status=0x%08x)\n", status); + goto out; + } + + /* Read the averaged result and clear the complete flag */ + code = readl(priv->base + TSU_SCRR) & TSU_SCRR_OUT12BIT_TS; + writel(TSU_SICR_ADCLR, priv->base + TSU_SICR); + + /* Convert to temperature */ + *temp = rzg3e_thermal_code_to_temp(priv, code); + + dev_dbg(priv->dev, "temp=%d mC (%d.%03d°C), code=0x%03x\n", + *temp, *temp / 1000, abs(*temp) % 1000, code); + +out: + pm_runtime_mark_last_busy(priv->dev); + pm_runtime_put_autosuspend(priv->dev); + return ret; +} + +static int rzg3e_thermal_set_trips(struct thermal_zone_device *tz, + int low, int high) +{ + struct rzg3e_thermal_priv *priv = thermal_zone_device_priv(tz); + u16 low_code, high_code; + u32 val; + int ret; + + /* Hardware requires low < high */ + if (low >= high) + return -EINVAL; + + ret = pm_runtime_resume_and_get(priv->dev); + if (ret < 0) + return ret; + + guard(mutex)(&priv->lock); + + /* Convert temperatures to codes */ + low_code = rzg3e_thermal_temp_to_code(priv, low); + high_code = rzg3e_thermal_temp_to_code(priv, high); + + dev_dbg(priv->dev, "set_trips: low=%d high=%d (codes: 0x%03x/0x%03x)\n", + low, high, low_code, high_code); + + /* Disable comparison during reconfiguration */ + writel(0, priv->base + TSU_SIER); + writel(0, priv->base + TSU_CMSR); + + /* Clear any pending comparison interrupts */ + writel(TSU_SICR_CMPCLR, priv->base + TSU_SICR); + + /* Set trip points */ + writel(low_code, priv->base + TSU_LLSR); + writel(high_code, priv->base + TSU_ULSR); + + /* + * Ensure OUTSEL is set for comparison per datasheet 7.11.7.4 + * Comparison uses averaged data + */ + val = readl(priv->base + TSU_SOSR1); + val |= TSU_SOSR1_OUTSEL; + writel(val, priv->base + TSU_SOSR1); + + /* Enable comparison with "out of range" mode (CMPCOND=0) */ + writel(TSU_CMSR_CMPEN, priv->base + TSU_CMSR); + + /* Unmask compare IRQ and start a conversion to evaluate window */ + writel(TSU_SIER_CMPIE, priv->base + TSU_SIER); + writel(TSU_STRGR_ADST, priv->base + TSU_STRGR); + + pm_runtime_mark_last_busy(priv->dev); + pm_runtime_put_autosuspend(priv->dev); + + return 0; +} + +static irqreturn_t rzg3e_thermal_irq_thread(int irq, void *data) +{ + struct rzg3e_thermal_priv *priv = data; + + dev_dbg(priv->dev, "Temperature threshold crossed\n"); + + /* Notify thermal framework to re-evaluate trip points */ + thermal_zone_device_update(priv->zone, THERMAL_TRIP_VIOLATED); + + return IRQ_HANDLED; +} + +static irqreturn_t rzg3e_thermal_irq(int irq, void *data) +{ + struct rzg3e_thermal_priv *priv = data; + u32 status; + + status = readl(priv->base + TSU_SISR); + + /* Check if comparison interrupt occurred */ + if (status & TSU_SISR_CMPF) { + /* Clear irq flag and disable interrupt until reconfigured */ + writel(TSU_SICR_CMPCLR, priv->base + TSU_SICR); + writel(0, priv->base + TSU_SIER); + + return IRQ_WAKE_THREAD; + } + + return IRQ_NONE; +} + +static const struct thermal_zone_device_ops rzg3e_tz_ops = { + .get_temp = rzg3e_thermal_get_temp, + .set_trips = rzg3e_thermal_set_trips, +}; + +static int rzg3e_thermal_get_calibration(struct rzg3e_thermal_priv *priv) +{ + u32 val; + int ret; + + /* Read calibration values from syscon */ + ret = regmap_read(priv->syscon, priv->trim_offset, &val); + if (ret) + return ret; + priv->trmval0 = val & GENMASK(11, 0); + + ret = regmap_read(priv->syscon, priv->trim_offset + 4, &val); + if (ret) + return ret; + priv->trmval1 = val & GENMASK(11, 0); + + /* Validate calibration data */ + if (!priv->trmval0 || !priv->trmval1 || + priv->trmval0 == priv->trmval1 || + priv->trmval0 == 0xFFF || priv->trmval1 == 0xFFF) { + dev_err(priv->dev, "Invalid calibration: b=0x%03x, c=0x%03x\n", + priv->trmval0, priv->trmval1); + return -EINVAL; + } + + dev_dbg(priv->dev, "Calibration: b=0x%03x (%u), c=0x%03x (%u)\n", + priv->trmval0, priv->trmval0, priv->trmval1, priv->trmval1); + + return 0; +} + +static int rzg3e_thermal_parse_dt(struct rzg3e_thermal_priv *priv) +{ + struct device_node *np = priv->dev->of_node; + u32 offset; + + priv->syscon = syscon_regmap_lookup_by_phandle_args(np, "renesas,tsu-trim", 1, &offset); + if (IS_ERR(priv->syscon)) + return dev_err_probe(priv->dev, PTR_ERR(priv->syscon), + "Failed to parse renesas,tsu-trim\n"); + + priv->trim_offset = offset; + return 0; +} + +static int rzg3e_thermal_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rzg3e_thermal_priv *priv; + struct clk *clk; + int irq, ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + ret = devm_mutex_init(dev, &priv->lock); + if (ret) + return ret; + platform_set_drvdata(pdev, priv); + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + /* Parse device tree for trim register info */ + ret = rzg3e_thermal_parse_dt(priv); + if (ret) + return ret; + + /* Get clock to verify frequency - clock is managed by power domain */ + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to get clock\n"); + + if (clk_get_rate(clk) < TSU_MIN_CLOCK_RATE) + return dev_err_probe(dev, -EINVAL, + "Clock rate %lu Hz too low (min %u Hz)\n", + clk_get_rate(clk), TSU_MIN_CLOCK_RATE); + + priv->rstc = devm_reset_control_get_exclusive_deasserted(dev, NULL); + if (IS_ERR(priv->rstc)) + return dev_err_probe(dev, PTR_ERR(priv->rstc), + "Failed to get/deassert reset control\n"); + + /* Get calibration data */ + ret = rzg3e_thermal_get_calibration(priv); + if (ret) + return dev_err_probe(dev, ret, + "Failed to get valid calibration data\n"); + + /* Get comparison interrupt */ + irq = platform_get_irq_byname(pdev, "adcmpi"); + if (irq < 0) + return irq; + + /* Enable runtime PM */ + pm_runtime_set_autosuspend_delay(dev, 1000); + pm_runtime_use_autosuspend(dev); + devm_pm_runtime_enable(dev); + + /* Initial hardware setup */ + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) + return dev_err_probe(dev, ret, "Runtime resume failed\n"); + + /* Register thermal zone - this will trigger DT parsing */ + priv->zone = devm_thermal_of_zone_register(dev, 0, priv, &rzg3e_tz_ops); + if (IS_ERR(priv->zone)) { + ret = PTR_ERR(priv->zone); + dev_err(dev, "Failed to register thermal zone: %d\n", ret); + goto err_pm_put; + } + + /* Request threaded IRQ for comparison interrupt */ + ret = devm_request_threaded_irq(dev, irq, rzg3e_thermal_irq, + rzg3e_thermal_irq_thread, + IRQF_ONESHOT, "rzg3e_thermal", priv); + if (ret) { + dev_err(dev, "Failed to request IRQ: %d\n", ret); + goto err_pm_put; + } + + /* Add hwmon sysfs interface */ + ret = devm_thermal_add_hwmon_sysfs(dev, priv->zone); + if (ret) + dev_warn(dev, "Failed to add hwmon sysfs attributes\n"); + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + dev_info(dev, "RZ/G3E thermal sensor registered\n"); + + return 0; + +err_pm_put: + pm_runtime_put_sync(dev); + return ret; +} + +static int rzg3e_thermal_runtime_suspend(struct device *dev) +{ + struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev); + + rzg3e_thermal_power_off(priv); + return 0; +} + +static int rzg3e_thermal_runtime_resume(struct device *dev) +{ + struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev); + + return rzg3e_thermal_power_on(priv); +} + +static int rzg3e_thermal_suspend(struct device *dev) +{ + struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev); + + /* If device is active, power it off */ + if (pm_runtime_active(dev)) + rzg3e_thermal_power_off(priv); + + /* Assert reset to ensure clean state after resume */ + reset_control_assert(priv->rstc); + + return 0; +} + +static int rzg3e_thermal_resume(struct device *dev) +{ + struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev); + int ret; + + /* Deassert reset */ + ret = reset_control_deassert(priv->rstc); + if (ret) { + dev_err(dev, "Failed to deassert reset: %d\n", ret); + return ret; + } + + /* If device was active before suspend, power it back on */ + if (pm_runtime_active(dev)) + return rzg3e_thermal_power_on(priv); + + return 0; +} + +static const struct dev_pm_ops rzg3e_thermal_pm_ops = { + RUNTIME_PM_OPS(rzg3e_thermal_runtime_suspend, + rzg3e_thermal_runtime_resume, NULL) + SYSTEM_SLEEP_PM_OPS(rzg3e_thermal_suspend, rzg3e_thermal_resume) +}; + +static const struct of_device_id rzg3e_thermal_dt_ids[] = { + { .compatible = "renesas,r9a09g047-tsu" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzg3e_thermal_dt_ids); + +static struct platform_driver rzg3e_thermal_driver = { + .driver = { + .name = "rzg3e_thermal", + .of_match_table = rzg3e_thermal_dt_ids, + .pm = pm_ptr(&rzg3e_thermal_pm_ops), + }, + .probe = rzg3e_thermal_probe, +}; +module_platform_driver(rzg3e_thermal_driver); + +MODULE_DESCRIPTION("Renesas RZ/G3E TSU Thermal Sensor Driver"); +MODULE_AUTHOR("John Madieu <john.madieu.xa@bp.renesas.com>"); +MODULE_LICENSE("GPL"); -- 2.25.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH v9 2/4] thermal: renesas: rzg3e: Add thermal driver for the Renesas RZ/G3E SoC 2025-09-17 17:01 ` [PATCH v9 2/4] thermal: renesas: rzg3e: Add thermal driver for the Renesas RZ/G3E SoC John Madieu @ 2025-09-19 17:06 ` Biju Das 0 siblings, 0 replies; 11+ messages in thread From: Biju Das @ 2025-09-19 17:06 UTC (permalink / raw) To: John Madieu, conor+dt, daniel.lezcano, geert+renesas, krzk+dt, lukasz.luba, magnus.damm, mturquette, robh, rui.zhang, sboyd, will Cc: catalin.marinas, devicetree, john.madieu, linux-arm-kernel, linux-kernel, linux-pm, linux-renesas-soc, p.zabel, rafael, John Madieu Hi John Madieu, Thanks for the patch. > -----Original Message----- > From: John Madieu <john.madieu.xa@bp.renesas.com> > Sent: 17 September 2025 18:02 > Subject: [PATCH v9 2/4] thermal: renesas: rzg3e: Add thermal driver for the Renesas RZ/G3E SoC > > The RZ/G3E SoC integrates a Temperature Sensor Unit (TSU) block designed to monitor the chip's junction > temperature. This sensor is connected to channel 1 of the APB port clock/reset and provides temperature > measurements. > > It also requires calibration values stored in the system controller registers for accurate temperature > measurement. Add a driver for the Renesas RZ/G3E TSU. > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Cheers, Biju > --- > > Changes: > > v1 -> v2: fixes IRQ names > > v2 -> v3: no changes > > v3 -> v4: no changes > > v5: Removed curly braces arround single-line protected scoped guards > > v6: Clarified comments in driver > > v7: Refactored driver structure: > - removes splinlock usage > - updates polling timeout as per the datasheet > - uses average mode to be more accurate > - uses polling (faster than irq mode) for get_temp() while keeping IRQ for hw > trip-point cross detection. > - adds both runtime and sleep PM support > > v8: - Use of_parse_phandle_with_fixed_args() for trim values > - Use millidegree computation to for better precision > > v9: > - Remove driver-specific read/write indirection and use readl/writel > - Use devm_mutex_init() > - Switch to syscon_regmap_lookup_by_phandle_args() > > MAINTAINERS | 7 + > drivers/thermal/renesas/Kconfig | 7 + > drivers/thermal/renesas/Makefile | 1 + > drivers/thermal/renesas/rzg3e_thermal.c | 547 ++++++++++++++++++++++++ > 4 files changed, 562 insertions(+) > create mode 100644 drivers/thermal/renesas/rzg3e_thermal.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 10614ca41ed0..5480412f556d 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -21544,6 +21544,13 @@ S: Maintained > F: Documentation/devicetree/bindings/iio/potentiometer/renesas,x9250.yaml > F: drivers/iio/potentiometer/x9250.c > > +RENESAS RZ/G3E THERMAL SENSOR UNIT DRIVER > +M: John Madieu <john.madieu.xa@bp.renesas.com> > +L: linux-pm@vger.kernel.org > +S: Maintained > +F: Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml > +F: drivers/thermal/renesas/rzg3e_thermal.c > + > RESET CONTROLLER FRAMEWORK > M: Philipp Zabel <p.zabel@pengutronix.de> > S: Maintained > diff --git a/drivers/thermal/renesas/Kconfig b/drivers/thermal/renesas/Kconfig index > dcf5fc5ae08e..10cf90fc4bfa 100644 > --- a/drivers/thermal/renesas/Kconfig > +++ b/drivers/thermal/renesas/Kconfig > @@ -26,3 +26,10 @@ config RZG2L_THERMAL > help > Enable this to plug the RZ/G2L thermal sensor driver into the Linux > thermal framework. > + > +config RZG3E_THERMAL > + tristate "Renesas RZ/G3E thermal driver" > + depends on ARCH_RENESAS || COMPILE_TEST > + help > + Enable this to plug the RZ/G3E thermal sensor driver into the Linux > + thermal framework. > diff --git a/drivers/thermal/renesas/Makefile b/drivers/thermal/renesas/Makefile > index bf9cb3cb94d6..5a3eba0dedd0 100644 > --- a/drivers/thermal/renesas/Makefile > +++ b/drivers/thermal/renesas/Makefile > @@ -3,3 +3,4 @@ > obj-$(CONFIG_RCAR_GEN3_THERMAL) += rcar_gen3_thermal.o > obj-$(CONFIG_RCAR_THERMAL) += rcar_thermal.o > obj-$(CONFIG_RZG2L_THERMAL) += rzg2l_thermal.o > +obj-$(CONFIG_RZG3E_THERMAL) += rzg3e_thermal.o > diff --git a/drivers/thermal/renesas/rzg3e_thermal.c b/drivers/thermal/renesas/rzg3e_thermal.c > new file mode 100644 > index 000000000000..e66d73ca6752 > --- /dev/null > +++ b/drivers/thermal/renesas/rzg3e_thermal.c > @@ -0,0 +1,547 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Renesas RZ/G3E TSU Temperature Sensor Unit > + * > + * Copyright (C) 2025 Renesas Electronics Corporation */ #include > +<linux/clk.h> #include <linux/cleanup.h> #include <linux/delay.h> > +#include <linux/err.h> #include <linux/interrupt.h> #include > +<linux/io.h> #include <linux/iopoll.h> #include <linux/kernel.h> > +#include <linux/mfd/syscon.h> #include <linux/module.h> #include > +<linux/of.h> #include <linux/platform_device.h> #include > +<linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/reset.h> > +#include <linux/thermal.h> #include <linux/units.h> > + > +#include "../thermal_hwmon.h" > + > +/* TSU Register offsets and bits */ > +#define TSU_SSUSR 0x00 > +#define TSU_SSUSR_EN_TS BIT(0) > +#define TSU_SSUSR_ADC_PD_TS BIT(1) > +#define TSU_SSUSR_SOC_TS_EN BIT(2) > + > +#define TSU_STRGR 0x04 > +#define TSU_STRGR_ADST BIT(0) > + > +#define TSU_SOSR1 0x08 > +#define TSU_SOSR1_ADCT_8 0x03 > +#define TSU_SOSR1_ADCS BIT(4) > +#define TSU_SOSR1_OUTSEL BIT(9) > + > +#define TSU_SCRR 0x10 > +#define TSU_SCRR_OUT12BIT_TS GENMASK(11, 0) > + > +#define TSU_SSR 0x14 > +#define TSU_SSR_CONV BIT(0) > + > +#define TSU_CMSR 0x18 > +#define TSU_CMSR_CMPEN BIT(0) > + > +#define TSU_LLSR 0x1C > +#define TSU_ULSR 0x20 > + > +#define TSU_SISR 0x30 > +#define TSU_SISR_ADF BIT(0) > +#define TSU_SISR_CMPF BIT(1) > + > +#define TSU_SIER 0x34 > +#define TSU_SIER_CMPIE BIT(1) > + > +#define TSU_SICR 0x38 > +#define TSU_SICR_ADCLR BIT(0) > +#define TSU_SICR_CMPCLR BIT(1) > + > +/* Temperature calculation constants from datasheet */ > +#define TSU_TEMP_D (-41) > +#define TSU_TEMP_E 126 > +#define TSU_CODE_MAX 0xFFF > + > +/* Timing specifications from datasheet */ > +#define TSU_POWERUP_TIME_US 120 /* 120T at 1MHz sensor clock per datasheet */ > +#define TSU_CONV_TIME_US 50 /* Per sample conversion time */ > +#define TSU_POLL_DELAY_US 10 /* Polling interval */ > +#define TSU_MIN_CLOCK_RATE 24000000 /* TSU_PCLK minimum 24MHz */ > + > +/** > + * struct rzg3e_thermal_priv - RZ/G3E TSU private data > + * @base: TSU register base > + * @dev: device pointer > + * @syscon: regmap for calibration values > + * @zone: thermal zone device > + * @rstc: reset control > + * @trmval0: calibration value 0 (b) > + * @trmval1: calibration value 1 (c) > + * @trim_offset: offset for trim registers in syscon > + * @lock: protects hardware access during conversions */ struct > +rzg3e_thermal_priv { > + void __iomem *base; > + struct device *dev; > + struct regmap *syscon; > + struct thermal_zone_device *zone; > + struct reset_control *rstc; > + u16 trmval0; > + u16 trmval1; > + u32 trim_offset; > + struct mutex lock; > +}; > + > +static int rzg3e_thermal_power_on(struct rzg3e_thermal_priv *priv) { > + u32 val; > + int ret; > + > + /* Clear any pending interrupts */ > + writel(TSU_SICR_ADCLR | TSU_SICR_CMPCLR, priv->base + TSU_SICR); > + > + /* Disable all interrupts during setup */ > + writel(0, priv->base + TSU_SIER); > + > + /* > + * Power-on sequence per datasheet 7.11.9.1: > + * SOC_TS_EN must be set at same time or before EN_TS and ADC_PD_TS > + */ > + val = TSU_SSUSR_SOC_TS_EN | TSU_SSUSR_EN_TS; > + writel(val, priv->base + TSU_SSUSR); > + > + /* Wait for sensor stabilization per datasheet 7.11.7.1 */ > + usleep_range(TSU_POWERUP_TIME_US, TSU_POWERUP_TIME_US + 10); > + > + /* Configure for average mode with 8 samples */ > + val = TSU_SOSR1_OUTSEL | TSU_SOSR1_ADCT_8; > + writel(val, priv->base + TSU_SOSR1); > + > + /* Ensure we're in single scan mode (default) */ > + val = readl(priv->base + TSU_SOSR1); > + if (val & TSU_SOSR1_ADCS) { > + dev_err(priv->dev, "Invalid scan mode setting\n"); > + return -EINVAL; > + } > + > + /* Wait for any ongoing conversion to complete */ > + ret = readl_poll_timeout(priv->base + TSU_SSR, val, > + !(val & TSU_SSR_CONV), > + TSU_POLL_DELAY_US, > + USEC_PER_MSEC); > + if (ret) { > + dev_err(priv->dev, "Timeout waiting for conversion\n"); > + return ret; > + } > + > + return 0; > +} > + > +static void rzg3e_thermal_power_off(struct rzg3e_thermal_priv *priv) { > + /* Disable all interrupts */ > + writel(0, priv->base + TSU_SIER); > + > + /* Clear pending interrupts */ > + writel(TSU_SICR_ADCLR | TSU_SICR_CMPCLR, priv->base + TSU_SICR); > + > + /* Power down sequence per datasheet */ > + writel(TSU_SSUSR_ADC_PD_TS, priv->base + TSU_SSUSR); } > + > +/* > + * Convert 12-bit sensor code to temperature in millicelsius > + * Formula from datasheet 7.11.7.8: > + * T(°C) = ((e - d) / (c - b)) * (a - b) + d > + * where: a = sensor code, b = trmval0, c = trmval1, d = -41, e = 126 > +*/ static int rzg3e_thermal_code_to_temp(struct rzg3e_thermal_priv > +*priv, u16 code) { > + int temp_e_mc = TSU_TEMP_E * MILLIDEGREE_PER_DEGREE; > + int temp_d_mc = TSU_TEMP_D * MILLIDEGREE_PER_DEGREE; > + s64 numerator, denominator; > + int temp_mc; > + > + numerator = (temp_e_mc - temp_d_mc) * (s64)(code - priv->trmval0); > + denominator = priv->trmval1 - priv->trmval0; > + > + temp_mc = div64_s64(numerator, denominator) + temp_d_mc; > + > + return clamp(temp_mc, temp_d_mc, temp_e_mc); } > + > +/* > + * Convert temperature in millicelsius to 12-bit sensor code > + * Formula from datasheet 7.11.7.9 (inverse of above) */ static u16 > +rzg3e_thermal_temp_to_code(struct rzg3e_thermal_priv *priv, int > +temp_mc) { > + int temp_e_mc = TSU_TEMP_E * MILLIDEGREE_PER_DEGREE; > + int temp_d_mc = TSU_TEMP_D * MILLIDEGREE_PER_DEGREE; > + s64 numerator, denominator; > + s64 code; > + > + numerator = (temp_mc - temp_d_mc) * (priv->trmval1 - priv->trmval0); > + denominator = temp_e_mc - temp_d_mc; > + > + code = div64_s64(numerator, denominator) + priv->trmval0; > + > + return clamp_val(code, 0, TSU_CODE_MAX); } > + > +static int rzg3e_thermal_get_temp(struct thermal_zone_device *tz, int > +*temp) { > + struct rzg3e_thermal_priv *priv = thermal_zone_device_priv(tz); > + u32 status, code; > + int ret, timeout; > + > + ret = pm_runtime_resume_and_get(priv->dev); > + if (ret < 0) > + return ret; > + > + guard(mutex)(&priv->lock); > + > + /* Clear any previous conversion status */ > + writel(TSU_SICR_ADCLR, priv->base + TSU_SICR); > + > + /* Start single conversion */ > + writel(TSU_STRGR_ADST, priv->base + TSU_STRGR); > + > + /* Wait for conversion completion - 8 samples at ~50us each */ > + timeout = TSU_CONV_TIME_US * 8 * 2; /* Double for margin */ > + ret = readl_poll_timeout(priv->base + TSU_SISR, status, > + status & TSU_SISR_ADF, > + TSU_POLL_DELAY_US, timeout); > + if (ret) { > + dev_err(priv->dev, "Conversion timeout (status=0x%08x)\n", status); > + goto out; > + } > + > + /* Read the averaged result and clear the complete flag */ > + code = readl(priv->base + TSU_SCRR) & TSU_SCRR_OUT12BIT_TS; > + writel(TSU_SICR_ADCLR, priv->base + TSU_SICR); > + > + /* Convert to temperature */ > + *temp = rzg3e_thermal_code_to_temp(priv, code); > + > + dev_dbg(priv->dev, "temp=%d mC (%d.%03d°C), code=0x%03x\n", > + *temp, *temp / 1000, abs(*temp) % 1000, code); > + > +out: > + pm_runtime_mark_last_busy(priv->dev); > + pm_runtime_put_autosuspend(priv->dev); > + return ret; > +} > + > +static int rzg3e_thermal_set_trips(struct thermal_zone_device *tz, > + int low, int high) > +{ > + struct rzg3e_thermal_priv *priv = thermal_zone_device_priv(tz); > + u16 low_code, high_code; > + u32 val; > + int ret; > + > + /* Hardware requires low < high */ > + if (low >= high) > + return -EINVAL; > + > + ret = pm_runtime_resume_and_get(priv->dev); > + if (ret < 0) > + return ret; > + > + guard(mutex)(&priv->lock); > + > + /* Convert temperatures to codes */ > + low_code = rzg3e_thermal_temp_to_code(priv, low); > + high_code = rzg3e_thermal_temp_to_code(priv, high); > + > + dev_dbg(priv->dev, "set_trips: low=%d high=%d (codes: 0x%03x/0x%03x)\n", > + low, high, low_code, high_code); > + > + /* Disable comparison during reconfiguration */ > + writel(0, priv->base + TSU_SIER); > + writel(0, priv->base + TSU_CMSR); > + > + /* Clear any pending comparison interrupts */ > + writel(TSU_SICR_CMPCLR, priv->base + TSU_SICR); > + > + /* Set trip points */ > + writel(low_code, priv->base + TSU_LLSR); > + writel(high_code, priv->base + TSU_ULSR); > + > + /* > + * Ensure OUTSEL is set for comparison per datasheet 7.11.7.4 > + * Comparison uses averaged data > + */ > + val = readl(priv->base + TSU_SOSR1); > + val |= TSU_SOSR1_OUTSEL; > + writel(val, priv->base + TSU_SOSR1); > + > + /* Enable comparison with "out of range" mode (CMPCOND=0) */ > + writel(TSU_CMSR_CMPEN, priv->base + TSU_CMSR); > + > + /* Unmask compare IRQ and start a conversion to evaluate window */ > + writel(TSU_SIER_CMPIE, priv->base + TSU_SIER); > + writel(TSU_STRGR_ADST, priv->base + TSU_STRGR); > + > + pm_runtime_mark_last_busy(priv->dev); > + pm_runtime_put_autosuspend(priv->dev); > + > + return 0; > +} > + > +static irqreturn_t rzg3e_thermal_irq_thread(int irq, void *data) { > + struct rzg3e_thermal_priv *priv = data; > + > + dev_dbg(priv->dev, "Temperature threshold crossed\n"); > + > + /* Notify thermal framework to re-evaluate trip points */ > + thermal_zone_device_update(priv->zone, THERMAL_TRIP_VIOLATED); > + > + return IRQ_HANDLED; > +} > + > +static irqreturn_t rzg3e_thermal_irq(int irq, void *data) { > + struct rzg3e_thermal_priv *priv = data; > + u32 status; > + > + status = readl(priv->base + TSU_SISR); > + > + /* Check if comparison interrupt occurred */ > + if (status & TSU_SISR_CMPF) { > + /* Clear irq flag and disable interrupt until reconfigured */ > + writel(TSU_SICR_CMPCLR, priv->base + TSU_SICR); > + writel(0, priv->base + TSU_SIER); > + > + return IRQ_WAKE_THREAD; > + } > + > + return IRQ_NONE; > +} > + > +static const struct thermal_zone_device_ops rzg3e_tz_ops = { > + .get_temp = rzg3e_thermal_get_temp, > + .set_trips = rzg3e_thermal_set_trips, > +}; > + > +static int rzg3e_thermal_get_calibration(struct rzg3e_thermal_priv > +*priv) { > + u32 val; > + int ret; > + > + /* Read calibration values from syscon */ > + ret = regmap_read(priv->syscon, priv->trim_offset, &val); > + if (ret) > + return ret; > + priv->trmval0 = val & GENMASK(11, 0); > + > + ret = regmap_read(priv->syscon, priv->trim_offset + 4, &val); > + if (ret) > + return ret; > + priv->trmval1 = val & GENMASK(11, 0); > + > + /* Validate calibration data */ > + if (!priv->trmval0 || !priv->trmval1 || > + priv->trmval0 == priv->trmval1 || > + priv->trmval0 == 0xFFF || priv->trmval1 == 0xFFF) { > + dev_err(priv->dev, "Invalid calibration: b=0x%03x, c=0x%03x\n", > + priv->trmval0, priv->trmval1); > + return -EINVAL; > + } > + > + dev_dbg(priv->dev, "Calibration: b=0x%03x (%u), c=0x%03x (%u)\n", > + priv->trmval0, priv->trmval0, priv->trmval1, priv->trmval1); > + > + return 0; > +} > + > +static int rzg3e_thermal_parse_dt(struct rzg3e_thermal_priv *priv) { > + struct device_node *np = priv->dev->of_node; > + u32 offset; > + > + priv->syscon = syscon_regmap_lookup_by_phandle_args(np, "renesas,tsu-trim", 1, &offset); > + if (IS_ERR(priv->syscon)) > + return dev_err_probe(priv->dev, PTR_ERR(priv->syscon), > + "Failed to parse renesas,tsu-trim\n"); > + > + priv->trim_offset = offset; > + return 0; > +} > + > +static int rzg3e_thermal_probe(struct platform_device *pdev) { > + struct device *dev = &pdev->dev; > + struct rzg3e_thermal_priv *priv; > + struct clk *clk; > + int irq, ret; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + priv->dev = dev; > + ret = devm_mutex_init(dev, &priv->lock); > + if (ret) > + return ret; > + platform_set_drvdata(pdev, priv); > + > + priv->base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(priv->base)) > + return PTR_ERR(priv->base); > + > + /* Parse device tree for trim register info */ > + ret = rzg3e_thermal_parse_dt(priv); > + if (ret) > + return ret; > + > + /* Get clock to verify frequency - clock is managed by power domain */ > + clk = devm_clk_get(dev, NULL); > + if (IS_ERR(clk)) > + return dev_err_probe(dev, PTR_ERR(clk), > + "Failed to get clock\n"); > + > + if (clk_get_rate(clk) < TSU_MIN_CLOCK_RATE) > + return dev_err_probe(dev, -EINVAL, > + "Clock rate %lu Hz too low (min %u Hz)\n", > + clk_get_rate(clk), TSU_MIN_CLOCK_RATE); > + > + priv->rstc = devm_reset_control_get_exclusive_deasserted(dev, NULL); > + if (IS_ERR(priv->rstc)) > + return dev_err_probe(dev, PTR_ERR(priv->rstc), > + "Failed to get/deassert reset control\n"); > + > + /* Get calibration data */ > + ret = rzg3e_thermal_get_calibration(priv); > + if (ret) > + return dev_err_probe(dev, ret, > + "Failed to get valid calibration data\n"); > + > + /* Get comparison interrupt */ > + irq = platform_get_irq_byname(pdev, "adcmpi"); > + if (irq < 0) > + return irq; > + > + /* Enable runtime PM */ > + pm_runtime_set_autosuspend_delay(dev, 1000); > + pm_runtime_use_autosuspend(dev); > + devm_pm_runtime_enable(dev); > + > + /* Initial hardware setup */ > + ret = pm_runtime_resume_and_get(dev); > + if (ret < 0) > + return dev_err_probe(dev, ret, "Runtime resume failed\n"); > + > + /* Register thermal zone - this will trigger DT parsing */ > + priv->zone = devm_thermal_of_zone_register(dev, 0, priv, &rzg3e_tz_ops); > + if (IS_ERR(priv->zone)) { > + ret = PTR_ERR(priv->zone); > + dev_err(dev, "Failed to register thermal zone: %d\n", ret); > + goto err_pm_put; > + } > + > + /* Request threaded IRQ for comparison interrupt */ > + ret = devm_request_threaded_irq(dev, irq, rzg3e_thermal_irq, > + rzg3e_thermal_irq_thread, > + IRQF_ONESHOT, "rzg3e_thermal", priv); > + if (ret) { > + dev_err(dev, "Failed to request IRQ: %d\n", ret); > + goto err_pm_put; > + } > + > + /* Add hwmon sysfs interface */ > + ret = devm_thermal_add_hwmon_sysfs(dev, priv->zone); > + if (ret) > + dev_warn(dev, "Failed to add hwmon sysfs attributes\n"); > + > + pm_runtime_mark_last_busy(dev); > + pm_runtime_put_autosuspend(dev); > + > + dev_info(dev, "RZ/G3E thermal sensor registered\n"); > + > + return 0; > + > +err_pm_put: > + pm_runtime_put_sync(dev); > + return ret; > +} > + > +static int rzg3e_thermal_runtime_suspend(struct device *dev) { > + struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev); > + > + rzg3e_thermal_power_off(priv); > + return 0; > +} > + > +static int rzg3e_thermal_runtime_resume(struct device *dev) { > + struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev); > + > + return rzg3e_thermal_power_on(priv); > +} > + > +static int rzg3e_thermal_suspend(struct device *dev) { > + struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev); > + > + /* If device is active, power it off */ > + if (pm_runtime_active(dev)) > + rzg3e_thermal_power_off(priv); > + > + /* Assert reset to ensure clean state after resume */ > + reset_control_assert(priv->rstc); > + > + return 0; > +} > + > +static int rzg3e_thermal_resume(struct device *dev) { > + struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev); > + int ret; > + > + /* Deassert reset */ > + ret = reset_control_deassert(priv->rstc); > + if (ret) { > + dev_err(dev, "Failed to deassert reset: %d\n", ret); > + return ret; > + } > + > + /* If device was active before suspend, power it back on */ > + if (pm_runtime_active(dev)) > + return rzg3e_thermal_power_on(priv); > + > + return 0; > +} > + > +static const struct dev_pm_ops rzg3e_thermal_pm_ops = { > + RUNTIME_PM_OPS(rzg3e_thermal_runtime_suspend, > + rzg3e_thermal_runtime_resume, NULL) > + SYSTEM_SLEEP_PM_OPS(rzg3e_thermal_suspend, rzg3e_thermal_resume) }; > + > +static const struct of_device_id rzg3e_thermal_dt_ids[] = { > + { .compatible = "renesas,r9a09g047-tsu" }, > + { /* sentinel */ } > +}; > +MODULE_DEVICE_TABLE(of, rzg3e_thermal_dt_ids); > + > +static struct platform_driver rzg3e_thermal_driver = { > + .driver = { > + .name = "rzg3e_thermal", > + .of_match_table = rzg3e_thermal_dt_ids, > + .pm = pm_ptr(&rzg3e_thermal_pm_ops), > + }, > + .probe = rzg3e_thermal_probe, > +}; > +module_platform_driver(rzg3e_thermal_driver); > + > +MODULE_DESCRIPTION("Renesas RZ/G3E TSU Thermal Sensor Driver"); > +MODULE_AUTHOR("John Madieu <john.madieu.xa@bp.renesas.com>"); > +MODULE_LICENSE("GPL"); > -- > 2.25.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v9 3/4] arm64: dts: renesas: r9a09g047: Add TSU node 2025-09-17 17:01 [PATCH v9 0/4] thermal: renesas: Add support for RZ/G3E John Madieu 2025-09-17 17:01 ` [PATCH v9 1/4] dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit John Madieu 2025-09-17 17:01 ` [PATCH v9 2/4] thermal: renesas: rzg3e: Add thermal driver for the Renesas RZ/G3E SoC John Madieu @ 2025-09-17 17:01 ` John Madieu 2025-09-24 14:07 ` Geert Uytterhoeven 2025-09-17 17:01 ` [PATCH v9 4/4] arm64: defconfig: Enable the Renesas RZ/G3E thermal driver John Madieu 2025-09-19 16:37 ` [PATCH v9 0/4] thermal: renesas: Add support for RZ/G3E Daniel Lezcano 4 siblings, 1 reply; 11+ messages in thread From: John Madieu @ 2025-09-17 17:01 UTC (permalink / raw) To: conor+dt, daniel.lezcano, geert+renesas, krzk+dt, lukasz.luba, magnus.damm, mturquette, robh, rui.zhang, sboyd, will Cc: biju.das.jz, catalin.marinas, devicetree, john.madieu, linux-arm-kernel, linux-kernel, linux-pm, linux-renesas-soc, p.zabel, rafael, John Madieu Add TSU node along with thermal zones and keep it enabled in the SoC DTSI. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> --- v1 -> v2: Fix IRQ names v2 -> v3: remove useless 'renesas,tsu-operating-mode' property' v3 -> v4: no changes v5: no changes v6: no changes v7: updated both property name and specifier (<phandle offset>) for trim property. v8: removed #address-cells property v9: no changes arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index e4fac7e0d764..7bf0b4a6c67a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -64,6 +64,7 @@ cpu0: cpu@0 { next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -74,6 +75,7 @@ cpu1: cpu@100 { next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -84,6 +86,7 @@ cpu2: cpu@200 { next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -94,6 +97,7 @@ cpu3: cpu@300 { next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -412,6 +416,19 @@ wdt3: watchdog@13000400 { status = "disabled"; }; + tsu: thermal@14002000 { + compatible = "renesas,r9a09g047-tsu"; + reg = <0 0x14002000 0 0x1000>; + interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 0x10a>; + resets = <&cpg 0xf8>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + renesas,tsu-trim = <&sys 0x330>; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; @@ -970,6 +987,37 @@ stmmac_axi_setup: stmmac-axi-config { snps,blen = <16 8 4 0 0 0 0>; }; + thermal-zones { + cpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 3>, <&cpu1 0 3>, + <&cpu2 0 3>, <&cpu3 0 3>; + contribution = <1024>; + }; + }; + + trips { + target: trip-point { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor_crit: sensor-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, -- 2.25.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v9 3/4] arm64: dts: renesas: r9a09g047: Add TSU node 2025-09-17 17:01 ` [PATCH v9 3/4] arm64: dts: renesas: r9a09g047: Add TSU node John Madieu @ 2025-09-24 14:07 ` Geert Uytterhoeven 2025-09-29 11:34 ` Geert Uytterhoeven 0 siblings, 1 reply; 11+ messages in thread From: Geert Uytterhoeven @ 2025-09-24 14:07 UTC (permalink / raw) To: John Madieu Cc: conor+dt, daniel.lezcano, krzk+dt, lukasz.luba, magnus.damm, mturquette, robh, rui.zhang, sboyd, will, biju.das.jz, catalin.marinas, devicetree, john.madieu, linux-arm-kernel, linux-kernel, linux-pm, linux-renesas-soc, p.zabel, rafael On Wed, 17 Sept 2025 at 19:03, John Madieu <john.madieu.xa@bp.renesas.com> wrote: > Add TSU node along with thermal zones and keep it enabled in the SoC DTSI. > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> LGTM, so Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v9 3/4] arm64: dts: renesas: r9a09g047: Add TSU node 2025-09-24 14:07 ` Geert Uytterhoeven @ 2025-09-29 11:34 ` Geert Uytterhoeven 0 siblings, 0 replies; 11+ messages in thread From: Geert Uytterhoeven @ 2025-09-29 11:34 UTC (permalink / raw) To: John Madieu Cc: conor+dt, daniel.lezcano, krzk+dt, lukasz.luba, magnus.damm, mturquette, robh, rui.zhang, sboyd, will, biju.das.jz, catalin.marinas, devicetree, john.madieu, linux-arm-kernel, linux-kernel, linux-pm, linux-renesas-soc, p.zabel, rafael On Wed, 24 Sept 2025 at 16:07, Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Wed, 17 Sept 2025 at 19:03, John Madieu > <john.madieu.xa@bp.renesas.com> wrote: > > Add TSU node along with thermal zones and keep it enabled in the SoC DTSI. > > > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> > > LGTM, so > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Thanks, will queue in renesas-devel for v6.19. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v9 4/4] arm64: defconfig: Enable the Renesas RZ/G3E thermal driver 2025-09-17 17:01 [PATCH v9 0/4] thermal: renesas: Add support for RZ/G3E John Madieu ` (2 preceding siblings ...) 2025-09-17 17:01 ` [PATCH v9 3/4] arm64: dts: renesas: r9a09g047: Add TSU node John Madieu @ 2025-09-17 17:01 ` John Madieu 2025-09-29 11:36 ` Geert Uytterhoeven 2025-09-19 16:37 ` [PATCH v9 0/4] thermal: renesas: Add support for RZ/G3E Daniel Lezcano 4 siblings, 1 reply; 11+ messages in thread From: John Madieu @ 2025-09-17 17:01 UTC (permalink / raw) To: conor+dt, daniel.lezcano, geert+renesas, krzk+dt, lukasz.luba, magnus.damm, mturquette, robh, rui.zhang, sboyd, will Cc: biju.das.jz, catalin.marinas, devicetree, john.madieu, linux-arm-kernel, linux-kernel, linux-pm, linux-renesas-soc, p.zabel, rafael, John Madieu, Krzysztof Kozlowski Enable the Renesas RZ/G3E thermal driver, as used on the Renesas RZ/G3E SMARC EVK board. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 58f87d09366c..8def47e094d0 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -728,6 +728,7 @@ CONFIG_ROCKCHIP_THERMAL=m CONFIG_RCAR_THERMAL=y CONFIG_RCAR_GEN3_THERMAL=y CONFIG_RZG2L_THERMAL=y +CONFIG_RZG3E_THERMAL=y CONFIG_ARMADA_THERMAL=y CONFIG_MTK_THERMAL=m CONFIG_MTK_LVTS_THERMAL=m -- 2.25.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v9 4/4] arm64: defconfig: Enable the Renesas RZ/G3E thermal driver 2025-09-17 17:01 ` [PATCH v9 4/4] arm64: defconfig: Enable the Renesas RZ/G3E thermal driver John Madieu @ 2025-09-29 11:36 ` Geert Uytterhoeven 0 siblings, 0 replies; 11+ messages in thread From: Geert Uytterhoeven @ 2025-09-29 11:36 UTC (permalink / raw) To: John Madieu Cc: conor+dt, daniel.lezcano, krzk+dt, lukasz.luba, magnus.damm, mturquette, robh, rui.zhang, sboyd, will, biju.das.jz, catalin.marinas, devicetree, john.madieu, linux-arm-kernel, linux-kernel, linux-pm, linux-renesas-soc, p.zabel, rafael, Krzysztof Kozlowski On Wed, 17 Sept 2025 at 19:03, John Madieu <john.madieu.xa@bp.renesas.com> wrote: > Enable the Renesas RZ/G3E thermal driver, as used on the Renesas > RZ/G3E SMARC EVK board. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Thanks, will queue in renesas-devel for v6.19. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v9 0/4] thermal: renesas: Add support for RZ/G3E 2025-09-17 17:01 [PATCH v9 0/4] thermal: renesas: Add support for RZ/G3E John Madieu ` (3 preceding siblings ...) 2025-09-17 17:01 ` [PATCH v9 4/4] arm64: defconfig: Enable the Renesas RZ/G3E thermal driver John Madieu @ 2025-09-19 16:37 ` Daniel Lezcano 2025-09-19 16:55 ` John Madieu 4 siblings, 1 reply; 11+ messages in thread From: Daniel Lezcano @ 2025-09-19 16:37 UTC (permalink / raw) To: John Madieu, conor+dt, geert+renesas, krzk+dt, lukasz.luba, magnus.damm, mturquette, robh, rui.zhang, sboyd, will Cc: biju.das.jz, catalin.marinas, devicetree, john.madieu, linux-arm-kernel, linux-kernel, linux-pm, linux-renesas-soc, p.zabel, rafael On 17/09/2025 19:01, John Madieu wrote: > This series adds support for the temperature sensor unit (TSU) found on the > Renesas RZ/G3E SoC. > > The initial syscon patch [1] the series depends on has already been accepted. > > Changes: > > v9: > * Remove driver-specific read/write indirection and use readl/writel > * Use devm_mutex_init() > * Switch to syscon_regmap_lookup_by_phandle_args() Any more comments on the patches ? -- <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog ^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH v9 0/4] thermal: renesas: Add support for RZ/G3E 2025-09-19 16:37 ` [PATCH v9 0/4] thermal: renesas: Add support for RZ/G3E Daniel Lezcano @ 2025-09-19 16:55 ` John Madieu 0 siblings, 0 replies; 11+ messages in thread From: John Madieu @ 2025-09-19 16:55 UTC (permalink / raw) To: Daniel Lezcano, conor+dt, geert+renesas, krzk+dt, lukasz.luba, magnus.damm, mturquette, robh, rui.zhang, sboyd, will Cc: Biju Das, catalin.marinas, devicetree, john.madieu, linux-arm-kernel, linux-kernel, linux-pm, linux-renesas-soc, p.zabel, rafael Hi Daniel, Thanks for the feedback. > -----Original Message----- > From: Daniel Lezcano <daniel.lezcano@linaro.org> > Sent: Friday, September 19, 2025 6:37 PM > To: John Madieu <john.madieu.xa@bp.renesas.com>; conor+dt@kernel.org; > geert+renesas@glider.be; krzk+dt@kernel.org; lukasz.luba@arm.com; > magnus.damm <magnus.damm@gmail.com>; mturquette@baylibre.com; > robh@kernel.org; rui.zhang@intel.com; sboyd@kernel.org; will@kernel.org > Subject: Re: [PATCH v9 0/4] thermal: renesas: Add support for RZ/G3E > > On 17/09/2025 19:01, John Madieu wrote: > > This series adds support for the temperature sensor unit (TSU) found > > on the Renesas RZ/G3E SoC. > > > > The initial syscon patch [1] the series depends on has already been > accepted. > > > > Changes: > > > > v9: > > * Remove driver-specific read/write indirection and use readl/writel > > * Use devm_mutex_init() > > * Switch to syscon_regmap_lookup_by_phandle_args() > > > Any more comments on the patches ? > All the comments received have been addressed, hence this v9. Almost all patches from the series have received Rb tags, except the main driver and the DTS. Regards, John. > > -- > <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs > > Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | > <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro- > blog/> Blog ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2025-09-29 11:36 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2025-09-17 17:01 [PATCH v9 0/4] thermal: renesas: Add support for RZ/G3E John Madieu 2025-09-17 17:01 ` [PATCH v9 1/4] dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit John Madieu 2025-09-17 17:01 ` [PATCH v9 2/4] thermal: renesas: rzg3e: Add thermal driver for the Renesas RZ/G3E SoC John Madieu 2025-09-19 17:06 ` Biju Das 2025-09-17 17:01 ` [PATCH v9 3/4] arm64: dts: renesas: r9a09g047: Add TSU node John Madieu 2025-09-24 14:07 ` Geert Uytterhoeven 2025-09-29 11:34 ` Geert Uytterhoeven 2025-09-17 17:01 ` [PATCH v9 4/4] arm64: defconfig: Enable the Renesas RZ/G3E thermal driver John Madieu 2025-09-29 11:36 ` Geert Uytterhoeven 2025-09-19 16:37 ` [PATCH v9 0/4] thermal: renesas: Add support for RZ/G3E Daniel Lezcano 2025-09-19 16:55 ` John Madieu
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