From: Samuel Holland <samuel.holland@sifive.com>
To: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
leyfoon.tan@starfivetech.com, kernel@esmil.dk, conor@kernel.org,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, mturquette@baylibre.com, sboyd@kernel.org,
p.zabel@pengutronix.de, emil.renner.berthing@canonical.com,
hal.feng@starfivetech.com, xingyu.wu@starfivetech.com
Subject: Re: [RFC 07/16] dt-bindings: clock: Add StarFive JH8100 North-West clock and reset generator
Date: Tue, 26 Dec 2023 12:07:21 -0600 [thread overview]
Message-ID: <74649469-2b47-486e-b8d1-c89b705fe8c1@sifive.com> (raw)
In-Reply-To: <20231226053848.25089-8-jeeheng.sia@starfivetech.com>
On 2023-12-25 11:38 PM, Sia Jee Heng wrote:
> Add bindings for the North-West clock and reset generator (NWCRG) on
> JH8100 SoC.
>
> Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> ---
> .../bindings/clock/starfive,jh8100-nwcrg.yaml | 119 ++++++++++++++++++
> .../dt-bindings/clock/starfive,jh8100-crg.h | 43 +++++++
> .../dt-bindings/reset/starfive,jh8100-crg.h | 14 +++
> 3 files changed, 176 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml
> new file mode 100644
> index 000000000000..be0f94e64e6a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml
> @@ -0,0 +1,119 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/starfive,jh8100-nwcrg.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH8100 North-West Clock and Reset Generator
> +
> +maintainers:
> + - Sia Jee Heng <jeeheng.sia@starfivetech.com>
> +
> +properties:
> + compatible:
> + const: starfive,jh8100-nwcrg
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Main Oscillator (24 MHz)
> + - description: APB_BUS clock from SYSCRG
> + - description: APB_BUS_PER4 clock from SYSCRG
> + - description: SPI_CORE_100 clock from SYSCRG
> + - description: ISP_2X clock from SYSCRG
> + - description: ISP_AXI clock from SYSCRG
> + - description: VOUT_ROOT0 clock from SYSCRG
> + - description: VOUT_ROOT1 clock from SYSCRG
> + - description: VOUT_SCAN_ATS clock from SYSCRG
> + - description: VOUT_DC_CORE clock from SYSCRG
> + - description: VOUT_AXI clock from SYSCRG
> + - description: AXI_400 clock from SYSCRG
> + - description: AHB0 clock from SYSCRG
> + - description: PERH_ROOT_PREOSC from SYSCRG
> + - description: External DVP clock
> + - description: External ISP DPHY TAP TCK clock
> + - description: External golbal clock
Typo: global
> + - description: External VOUT MIPI DPHY TAP TCK
> + - description: External VOUT eDP TAP TCK
> + - description: External SPI In2 clock
> + - description: PLL5
> [...]
next prev parent reply other threads:[~2023-12-26 18:07 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-26 5:38 [RFC 00/16] Basic clock and reset support for StarFive JH8100 RISC-V SoC Sia Jee Heng
2023-12-26 5:38 ` [RFC 01/16] reset: starfive: Rename file name "jh71x0" to "common" Sia Jee Heng
2023-12-26 5:38 ` [RFC 02/16] reset: starfive: Convert the word "jh71x0" to "starfive" Sia Jee Heng
2023-12-26 5:38 ` [RFC 03/16] clk: starfive: Rename file name "jh71x0" to "common" Sia Jee Heng
2023-12-26 5:38 ` [RFC 04/16] clk: starfive: Convert the word "jh71x0" to "starfive" Sia Jee Heng
2023-12-26 5:38 ` [RFC 05/16] dt-bindings: clock: Add StarFive JH8100 System clock and reset generator Sia Jee Heng
2023-12-26 13:34 ` Krzysztof Kozlowski
2023-12-26 5:38 ` [RFC 06/16] clk: starfive: Add JH8100 System clock generator driver Sia Jee Heng
2023-12-26 5:38 ` [RFC 07/16] dt-bindings: clock: Add StarFive JH8100 North-West clock and reset generator Sia Jee Heng
2023-12-26 13:35 ` Krzysztof Kozlowski
2023-12-26 18:07 ` Samuel Holland [this message]
2023-12-27 10:51 ` JeeHeng Sia
2023-12-26 5:38 ` [RFC 08/16] clk: starfive: Add JH8100 North-West clock generator driver Sia Jee Heng
2023-12-26 5:38 ` [RFC 09/16] dt-bindings: clock: Add StarFive JH8100 North-East clock and reset generator Sia Jee Heng
2023-12-26 13:36 ` Krzysztof Kozlowski
2023-12-26 5:38 ` [RFC 10/16] clk: starfive: Add JH8100 North-East clock generator driver Sia Jee Heng
2023-12-26 5:38 ` [RFC 11/16] dt-bindings: clock: Add StarFive JH8100 South-West clock and reset generator Sia Jee Heng
2023-12-26 13:36 ` Krzysztof Kozlowski
2023-12-26 5:38 ` [RFC 12/16] clk: starfive: Add JH8100 South-West clock generator driver Sia Jee Heng
2023-12-26 5:38 ` [RFC 13/16] dt-bindings: clock: Add StarFive JH8100 Always-On clock and reset generator Sia Jee Heng
2023-12-26 13:37 ` Krzysztof Kozlowski
2023-12-26 5:38 ` [RFC 14/16] clk: starfive: Add JH8100 Always-On clock generator driver Sia Jee Heng
2023-12-26 5:38 ` [RFC 15/16] reset: starfive: Add StarFive JH8100 reset driver Sia Jee Heng
2023-12-26 5:38 ` [RFC 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes Sia Jee Heng
2023-12-26 13:38 ` Krzysztof Kozlowski
2023-12-27 11:02 ` JeeHeng Sia
2023-12-26 13:33 ` [RFC 00/16] Basic clock and reset support for StarFive JH8100 RISC-V SoC Krzysztof Kozlowski
2023-12-27 11:03 ` JeeHeng Sia
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