Re: [PATCH 2/5] arm64: dts: qcom: Add Kalambo SoC

[Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>]

Hi Konrad,

Thanks a lot for the review and for catching these
> On 7/18/26 2:06 PM, Gopikrishna Garmidi wrote:
>> Introduce support for the Qualcomm Kalambo SoC. It is derived from Mahua
>> with CPU cluster 0 removed, leaving it with just cluster 1. As a result,
>> the PDP mailbox and SCP low-priority register windows are updated to
>> match the reduced CPU complex. Everything else should work as-is.
>>
>> Add a label to the Glymur cluster0 cpu-map node to allow its removal on
>> derived SoCs.
>>
>> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
>> ---
>>   arch/arm64/boot/dts/qcom/glymur.dtsi  |  2 +-
>>   arch/arm64/boot/dts/qcom/kalambo.dtsi | 29 +++++++++++++++++++++++++++++
>>   2 files changed, 30 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> index 55d91c696a3a..f2feef362be5 100644
>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> @@ -275,7 +275,7 @@ cpu17: cpu@20500 {
>>   		};
>>   
>>   		cpu-map {
>> -			cluster0 {
>> +			cpu_map_cluster0: cluster0 {
> 
> I doubt the code that parses this will be happy about not
> being able to start from 'cluster0'
> 

Good catch, you're right. parse_cluster() in 
drivers/base/arch_topology.c walks "cluster%d" starting at 0 and bails 
out on the first missing index, so deleting cluster0 and leaving only 
cluster1 means the topology never gets parsed at all.

For v2 I'll delete both cluster0 and cluster1 and re-add the surviving 
cores as cluster0 in the Kalambo SoC file, so the scan starts at 
cluster0 as expected:
   /delete-node/ &cpu_map_cluster0;
   /delete-node/ &cpu_map_cluster1;

   &{/cpus/cpu-map} {
         cluster0 {
                 core0 {
                         cpu = <&cpu6>;
                 };
                 ...
                 core5 {
                         cpu = <&cpu11>;
                 };
         };
   };

Does this look right to you, or would you prefer re-pointing cluster0's 
cores in place rather than delete + re-add?

> 
> [...]
> 
>> +&pdp0_mbox {
>> +	reg = <0 0x17610000 0 0x8000>, <0 0x1a980000 0 0x8000>;
>> +};
> 
> Are you sure about this change?

Yes — confirmed against the SoC memory map. The Tx window is the 
NCC0/NCC1 mailbox instance; dropping the former cluster0 moves the Tx 
base from NCC0 (0x19980000) to NCC1 (0x1a980000), while reg[0] (Rx) is 
shared and unchanged. I'll note this in the commit message.

>> +&cpu_scp_lpri1 {
>> +	reg = <0x180 0x60>;
>> +};
> 
> This is specific to old firmware, at least it was on Glymur, I believe..

Right, the size was bumped permanently on the firmware side, so this
override isn't needed anymore. I'll drop it in v2.

> Konrad