[PATCH 0/3] iommu: qcom: Fix the MSM GPU and display with DMA-address based mappings

[PATCH 0/3] iommu: qcom: Fix the MSM GPU and display with DMA-address based mappings

[Dmitry Baryshkov]

Rob's drm/msm series [1] writes the addresses dma_map_sgtable() returns
for the DRM device into the GPU and display page tables, so they have to
be physical addresses, i.e. the device must not use iommu-dma. On DPU
platforms that holds, the DRM device has no iommus of its own. On MDP5
platforms it is the MDP5 device, which ends up with iommu-dma: the GPU
then fails to start on db410c and sda660 and resets db820c. The last
two patches give it an identity default domain in qcom_iommu and
arm-smmu-qcom.

The first patch fixes qcom_iommu's flush_iotlb_all, which never
invalidated the TLB. Nothing relies on it today, but the series above
does, hence no Fixes tag.

The patches are independent of [1] and a no-op for the current drm/msm,
but have to land before it. Tested on top of [1] on db410c, db820c and
IFC6560 with and without these patches, and on Open-Q 835 (DPU) as a
control.

[1] https://lore.kernel.org/r/20261027230452.130031-1-robin.clark@oss.qualcomm.com

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
Dmitry Baryshkov (3):
      iommu/qcom: Invalidate the TLB in flush_iotlb_all
      iommu/qcom: Use identity default domains for the MSM GPU and display
      iommu/arm-smmu-qcom: Use identity default domains for MDP5

 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c |  7 ++++++-
 drivers/iommu/arm/arm-smmu/qcom_iommu.c    | 26 ++++++++++++++++++++++++--
 2 files changed, 30 insertions(+), 3 deletions(-)
---
base-commit: f1ac44c32cba88ad65dcecd4a279661d14e93651
change-id: 20261030-msm-smmu-identity-6fda3323023b

Best regards,
--  
With best wishes
Dmitry

[PATCH 1/3] iommu/qcom: Invalidate the TLB in flush_iotlb_all

[Dmitry Baryshkov]

qcom_iommu_flush_iotlb_all() only waits for a TLB sync and never
invalidates anything. iommu_unmap() users do not notice, since
io-pgtable invalidates each page through the gather, but drm/msm unmaps
with a NULL gather and relies on flush_iotlb_all. On db410c the GPU then
hangs on stale TLB entries as soon as another process reuses the IOVAs.

Invalidate the whole context, as arm-smmu does, and keep iotlb_sync a
plain sync.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/iommu/arm/arm-smmu/qcom_iommu.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
index 21d18ce67b98..54130c32056a 100644
--- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
+++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
@@ -479,14 +479,22 @@ static void qcom_iommu_flush_iotlb_all(struct iommu_domain *domain)
 		return;
 
 	pm_runtime_get_sync(qcom_domain->iommu->dev);
-	qcom_iommu_tlb_sync(pgtable->cookie);
+	qcom_iommu_tlb_inv_context(pgtable->cookie);
 	pm_runtime_put_sync(qcom_domain->iommu->dev);
 }
 
 static void qcom_iommu_iotlb_sync(struct iommu_domain *domain,
 				  struct iommu_iotlb_gather *gather)
 {
-	qcom_iommu_flush_iotlb_all(domain);
+	struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
+	struct io_pgtable *pgtable = container_of(qcom_domain->pgtbl_ops,
+						  struct io_pgtable, ops);
+	if (!qcom_domain->pgtbl_ops)
+		return;
+
+	pm_runtime_get_sync(qcom_domain->iommu->dev);
+	qcom_iommu_tlb_sync(pgtable->cookie);
+	pm_runtime_put_sync(qcom_domain->iommu->dev);
 }
 
 static phys_addr_t qcom_iommu_iova_to_phys(struct iommu_domain *domain,

-- 
2.47.3

[PATCH 2/3] iommu/qcom: Use identity default domains for the MSM GPU and display

[Dmitry Baryshkov]

drm/msm writes the addresses dma_map_sgtable() returns for the DRM
device into its own page tables, so they have to be physical addresses,
i.e. the device must not use iommu-dma. qcom_iommu has no
def_domain_type, so the MDP5 and Adreno devices do get iommu-dma, the
buffers end up mapped at IOVAs of the unused default domain and the
db410c GPU fails to start.

Use identity default domains for these devices, as arm-smmu-qcom does.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/iommu/arm/arm-smmu/qcom_iommu.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
index 54130c32056a..4a9c4cf63724 100644
--- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
+++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
@@ -22,6 +22,7 @@
 #include <linux/init.h>
 #include <linux/mutex.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/pm.h>
@@ -531,6 +532,18 @@ static bool qcom_iommu_capable(struct device *dev, enum iommu_cap cap)
 	}
 }
 
+static const struct of_device_id qcom_iommu_client_of_match[] = {
+	{ .compatible = "qcom,adreno" },
+	{ .compatible = "qcom,mdp5" },
+	{ }
+};
+
+static int qcom_iommu_def_domain_type(struct device *dev)
+{
+	return of_match_device(qcom_iommu_client_of_match, dev) ?
+		IOMMU_DOMAIN_IDENTITY : 0;
+}
+
 static struct iommu_device *qcom_iommu_probe_device(struct device *dev)
 {
 	struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev);
@@ -602,6 +615,7 @@ static const struct iommu_ops qcom_iommu_ops = {
 	.capable	= qcom_iommu_capable,
 	.domain_alloc_paging = qcom_iommu_domain_alloc_paging,
 	.probe_device	= qcom_iommu_probe_device,
+	.def_domain_type = qcom_iommu_def_domain_type,
 	.device_group	= generic_device_group,
 	.of_xlate	= qcom_iommu_of_xlate,
 	.default_domain_ops = &(const struct iommu_domain_ops) {

-- 
2.47.3

[PATCH 3/3] iommu/arm-smmu-qcom: Use identity default domains for MDP5

[Dmitry Baryshkov]

drm/msm writes the addresses dma_map_sgtable() returns for the DRM
device into its own page tables, so they have to be physical addresses,
i.e. the device must not use iommu-dma. On MDP5 platforms the DRM
device is the "qcom,mdp5" node, which is missing from the client list,
and the msm8996 MMSS SMMUs have no qcom impl at all, so the device gets
iommu-dma. On db820c the SoC then resets as soon as the GPU starts.

Add "qcom,mdp5" to the list, which also covers sdm630/660, and give
msm8996 an impl with just def_domain_type, keeping the bypass emulation
out of it.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 795e8ec7e8fa..addba9074217 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -408,6 +408,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
 	{ .compatible = "qcom,adreno-gmu" },
 	{ .compatible = "qcom,glymur-mdss" },
 	{ .compatible = "qcom,mdp4" },
+	{ .compatible = "qcom,mdp5" },
 	{ .compatible = "qcom,mdss" },
 	{ .compatible = "qcom,qcm2290-mdss" },
 	{ .compatible = "qcom,sar2130p-mdss" },
@@ -642,6 +643,10 @@ static const struct arm_smmu_impl sdm845_smmu_500_impl = {
 #endif
 };
 
+static const struct arm_smmu_impl msm8996_smmu_impl = {
+	.def_domain_type = qcom_smmu_def_domain_type,
+};
+
 static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = {
 	.init_context = qcom_adreno_smmu_init_context,
 	.cfg_probe = qcom_adreno_smmuv2_cfg_probe,
@@ -711,7 +716,7 @@ static const struct qcom_smmu_config qcom_smmu_impl0_cfg = {
  * there are not enough context banks.
  */
 static const struct qcom_smmu_match_data msm8996_smmu_data = {
-	.impl = NULL,
+	.impl = &msm8996_smmu_impl,
 	.adreno_impl = &qcom_adreno_smmu_v2_impl,
 };
 

-- 
2.47.3

Re: [PATCH 1/3] iommu/qcom: Invalidate the TLB in flush_iotlb_all

[Rob Clark]

On Fri, Oct 30, 2026 at 3:05 PM Dmitry Baryshkov
<dmitry.baryshkov@oss.qualcomm.com> wrote:
>
> qcom_iommu_flush_iotlb_all() only waits for a TLB sync and never
> invalidates anything. iommu_unmap() users do not notice, since
> io-pgtable invalidates each page through the gather, but drm/msm unmaps
> with a NULL gather and relies on flush_iotlb_all. On db410c the GPU then
> hangs on stale TLB entries as soon as another process reuses the IOVAs.
>
> Invalidate the whole context, as arm-smmu does, and keep iotlb_sync a
> plain sync.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

Reviewed-by: Rob Clark <rob.clark@oss.qualcomm.com>

> ---
>  drivers/iommu/arm/arm-smmu/qcom_iommu.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> index 21d18ce67b98..54130c32056a 100644
> --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> @@ -479,14 +479,22 @@ static void qcom_iommu_flush_iotlb_all(struct iommu_domain *domain)
>                 return;
>
>         pm_runtime_get_sync(qcom_domain->iommu->dev);
> -       qcom_iommu_tlb_sync(pgtable->cookie);
> +       qcom_iommu_tlb_inv_context(pgtable->cookie);
>         pm_runtime_put_sync(qcom_domain->iommu->dev);
>  }
>
>  static void qcom_iommu_iotlb_sync(struct iommu_domain *domain,
>                                   struct iommu_iotlb_gather *gather)
>  {
> -       qcom_iommu_flush_iotlb_all(domain);
> +       struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
> +       struct io_pgtable *pgtable = container_of(qcom_domain->pgtbl_ops,
> +                                                 struct io_pgtable, ops);
> +       if (!qcom_domain->pgtbl_ops)
> +               return;
> +
> +       pm_runtime_get_sync(qcom_domain->iommu->dev);
> +       qcom_iommu_tlb_sync(pgtable->cookie);
> +       pm_runtime_put_sync(qcom_domain->iommu->dev);
>  }
>
>  static phys_addr_t qcom_iommu_iova_to_phys(struct iommu_domain *domain,
>
> --
> 2.47.3
>

Re: [PATCH 2/3] iommu/qcom: Use identity default domains for the MSM GPU and display

[Rob Clark]

On Fri, Oct 30, 2026 at 3:05 PM Dmitry Baryshkov
<dmitry.baryshkov@oss.qualcomm.com> wrote:
>
> drm/msm writes the addresses dma_map_sgtable() returns for the DRM
> device into its own page tables, so they have to be physical addresses,
> i.e. the device must not use iommu-dma. qcom_iommu has no
> def_domain_type, so the MDP5 and Adreno devices do get iommu-dma, the
> buffers end up mapped at IOVAs of the unused default domain and the
> db410c GPU fails to start.
>
> Use identity default domains for these devices, as arm-smmu-qcom does.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

Reviewed-by: Rob Clark <rob.clark@oss.qualcomm.com>

> ---
>  drivers/iommu/arm/arm-smmu/qcom_iommu.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> index 54130c32056a..4a9c4cf63724 100644
> --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> @@ -22,6 +22,7 @@
>  #include <linux/init.h>
>  #include <linux/mutex.h>
>  #include <linux/of.h>
> +#include <linux/of_device.h>
>  #include <linux/of_platform.h>
>  #include <linux/platform_device.h>
>  #include <linux/pm.h>
> @@ -531,6 +532,18 @@ static bool qcom_iommu_capable(struct device *dev, enum iommu_cap cap)
>         }
>  }
>
> +static const struct of_device_id qcom_iommu_client_of_match[] = {
> +       { .compatible = "qcom,adreno" },
> +       { .compatible = "qcom,mdp5" },
> +       { }
> +};
> +
> +static int qcom_iommu_def_domain_type(struct device *dev)
> +{
> +       return of_match_device(qcom_iommu_client_of_match, dev) ?
> +               IOMMU_DOMAIN_IDENTITY : 0;
> +}
> +
>  static struct iommu_device *qcom_iommu_probe_device(struct device *dev)
>  {
>         struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev);
> @@ -602,6 +615,7 @@ static const struct iommu_ops qcom_iommu_ops = {
>         .capable        = qcom_iommu_capable,
>         .domain_alloc_paging = qcom_iommu_domain_alloc_paging,
>         .probe_device   = qcom_iommu_probe_device,
> +       .def_domain_type = qcom_iommu_def_domain_type,
>         .device_group   = generic_device_group,
>         .of_xlate       = qcom_iommu_of_xlate,
>         .default_domain_ops = &(const struct iommu_domain_ops) {
>
> --
> 2.47.3
>

Re: [PATCH 3/3] iommu/arm-smmu-qcom: Use identity default domains for MDP5

[Rob Clark]

On Fri, Oct 30, 2026 at 3:05 PM Dmitry Baryshkov
<dmitry.baryshkov@oss.qualcomm.com> wrote:
>
> drm/msm writes the addresses dma_map_sgtable() returns for the DRM
> device into its own page tables, so they have to be physical addresses,
> i.e. the device must not use iommu-dma. On MDP5 platforms the DRM
> device is the "qcom,mdp5" node, which is missing from the client list,
> and the msm8996 MMSS SMMUs have no qcom impl at all, so the device gets
> iommu-dma. On db820c the SoC then resets as soon as the GPU starts.
>
> Add "qcom,mdp5" to the list, which also covers sdm630/660, and give
> msm8996 an impl with just def_domain_type, keeping the bypass emulation
> out of it.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

Reviewed-by: Rob Clark <rob.clark@oss.qualcomm.com>

> ---
>  drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index 795e8ec7e8fa..addba9074217 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -408,6 +408,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
>         { .compatible = "qcom,adreno-gmu" },
>         { .compatible = "qcom,glymur-mdss" },
>         { .compatible = "qcom,mdp4" },
> +       { .compatible = "qcom,mdp5" },
>         { .compatible = "qcom,mdss" },
>         { .compatible = "qcom,qcm2290-mdss" },
>         { .compatible = "qcom,sar2130p-mdss" },
> @@ -642,6 +643,10 @@ static const struct arm_smmu_impl sdm845_smmu_500_impl = {
>  #endif
>  };
>
> +static const struct arm_smmu_impl msm8996_smmu_impl = {
> +       .def_domain_type = qcom_smmu_def_domain_type,
> +};
> +
>  static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = {
>         .init_context = qcom_adreno_smmu_init_context,
>         .cfg_probe = qcom_adreno_smmuv2_cfg_probe,
> @@ -711,7 +716,7 @@ static const struct qcom_smmu_config qcom_smmu_impl0_cfg = {
>   * there are not enough context banks.
>   */
>  static const struct qcom_smmu_match_data msm8996_smmu_data = {
> -       .impl = NULL,
> +       .impl = &msm8996_smmu_impl,
>         .adreno_impl = &qcom_adreno_smmu_v2_impl,
>  };
>
>
> --
> 2.47.3
>

Re: [PATCH 0/3] iommu: qcom: Fix the MSM GPU and display with DMA-address based mappings

[Rob Clark]

On Fri, Oct 30, 2026 at 3:05 PM Dmitry Baryshkov
<dmitry.baryshkov@oss.qualcomm.com> wrote:
>
> Rob's drm/msm series [1] writes the addresses dma_map_sgtable() returns
> for the DRM device into the GPU and display page tables, so they have to
> be physical addresses, i.e. the device must not use iommu-dma. On DPU
> platforms that holds, the DRM device has no iommus of its own. On MDP5
> platforms it is the MDP5 device, which ends up with iommu-dma: the GPU
> then fails to start on db410c and sda660 and resets db820c. The last
> two patches give it an identity default domain in qcom_iommu and
> arm-smmu-qcom.
>
> The first patch fixes qcom_iommu's flush_iotlb_all, which never
> invalidated the TLB. Nothing relies on it today, but the series above
> does, hence no Fixes tag.
>
> The patches are independent of [1] and a no-op for the current drm/msm,
> but have to land before it. Tested on top of [1] on db410c, db820c and
> IFC6560 with and without these patches, and on Open-Q 835 (DPU) as a
> control.

Thanks, this should mostly supersede my untested series[1], but I
think msm_iommu.c still needs the same treatment?  Hopefully just the
def_domain_type() part?

BR,
-R

[1] https://lore.kernel.org/all/20261029212344.346069-1-robin.clark@oss.qualcomm.com/

>
> [1] https://lore.kernel.org/r/20261027230452.130031-1-robin.clark@oss.qualcomm.com
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> Dmitry Baryshkov (3):
>       iommu/qcom: Invalidate the TLB in flush_iotlb_all
>       iommu/qcom: Use identity default domains for the MSM GPU and display
>       iommu/arm-smmu-qcom: Use identity default domains for MDP5
>
>  drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c |  7 ++++++-
>  drivers/iommu/arm/arm-smmu/qcom_iommu.c    | 26 ++++++++++++++++++++++++--
>  2 files changed, 30 insertions(+), 3 deletions(-)
> ---
> base-commit: f1ac44c32cba88ad65dcecd4a279661d14e93651
> change-id: 20261030-msm-smmu-identity-6fda3323023b
>
> Best regards,
> --
> With best wishes
> Dmitry
>

Re: [PATCH 2/3] iommu/qcom: Use identity default domains for the MSM GPU and display

[Konrad Dybcio]

On 10/30/26 11:04 PM, Dmitry Baryshkov wrote:
> drm/msm writes the addresses dma_map_sgtable() returns for the DRM
> device into its own page tables, so they have to be physical addresses,
> i.e. the device must not use iommu-dma. qcom_iommu has no
> def_domain_type, so the MDP5 and Adreno devices do get iommu-dma, the
> buffers end up mapped at IOVAs of the unused default domain and the
> db410c GPU fails to start.
> 
> Use identity default domains for these devices, as arm-smmu-qcom does.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 3/3] iommu/arm-smmu-qcom: Use identity default domains for MDP5

[Konrad Dybcio]

On 10/30/26 11:04 PM, Dmitry Baryshkov wrote:
> drm/msm writes the addresses dma_map_sgtable() returns for the DRM
> device into its own page tables, so they have to be physical addresses,
> i.e. the device must not use iommu-dma. On MDP5 platforms the DRM
> device is the "qcom,mdp5" node, which is missing from the client list,
> and the msm8996 MMSS SMMUs have no qcom impl at all, so the device gets
> iommu-dma. On db820c the SoC then resets as soon as the GPU starts.
> 
> Add "qcom,mdp5" to the list, which also covers sdm630/660, and give
> msm8996 an impl with just def_domain_type, keeping the bypass emulation
> out of it.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 1/3] iommu/qcom: Invalidate the TLB in flush_iotlb_all

[Konrad Dybcio]

On 10/30/26 11:04 PM, Dmitry Baryshkov wrote:
> qcom_iommu_flush_iotlb_all() only waits for a TLB sync and never
> invalidates anything. iommu_unmap() users do not notice, since
> io-pgtable invalidates each page through the gather, but drm/msm unmaps
> with a NULL gather and relies on flush_iotlb_all. On db410c the GPU then
> hangs on stale TLB entries as soon as another process reuses the IOVAs.
> 
> Invalidate the whole context, as arm-smmu does, and keep iotlb_sync a
> plain sync.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---

Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 0/3] iommu: qcom: Fix the MSM GPU and display with DMA-address based mappings

[Dmitry Baryshkov]

On Sat, Oct 31, 2026 at 08:33:06AM -0700, Rob Clark wrote:
> On Fri, Oct 30, 2026 at 3:05 PM Dmitry Baryshkov
> <dmitry.baryshkov@oss.qualcomm.com> wrote:
> >
> > Rob's drm/msm series [1] writes the addresses dma_map_sgtable() returns
> > for the DRM device into the GPU and display page tables, so they have to
> > be physical addresses, i.e. the device must not use iommu-dma. On DPU
> > platforms that holds, the DRM device has no iommus of its own. On MDP5
> > platforms it is the MDP5 device, which ends up with iommu-dma: the GPU
> > then fails to start on db410c and sda660 and resets db820c. The last
> > two patches give it an identity default domain in qcom_iommu and
> > arm-smmu-qcom.
> >
> > The first patch fixes qcom_iommu's flush_iotlb_all, which never
> > invalidated the TLB. Nothing relies on it today, but the series above
> > does, hence no Fixes tag.
> >
> > The patches are independent of [1] and a no-op for the current drm/msm,
> > but have to land before it. Tested on top of [1] on db410c, db820c and
> > IFC6560 with and without these patches, and on Open-Q 835 (DPU) as a
> > control.
> 
> Thanks, this should mostly supersede my untested series[1], but I
> think msm_iommu.c still needs the same treatment?  Hopefully just the
> def_domain_type() part?

The msm_iommu.c needed more fixes. I will refresh my old series and
include fixes necessary for the dmabuf debug to work.

-- 
With best wishes
Dmitry