* [PATCH 1/4] dt-bindings: remoteproc: qcom: Add Glymur OOBMSS PAS binding
2026-10-09 7:17 [PATCH 0/4] Add Glymur OOBMSS support Anvesh Jain P
@ 2026-10-09 7:17 ` Anvesh Jain P
2026-10-12 8:55 ` Krzysztof Kozlowski
2026-10-09 7:17 ` [PATCH 2/4] remoteproc: qcom: pas: Support secondary images Anvesh Jain P
` (2 subsequent siblings)
3 siblings, 1 reply; 12+ messages in thread
From: Anvesh Jain P @ 2026-10-09 7:17 UTC (permalink / raw)
To: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio
Cc: linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
Sibi Sankar, Anvesh Jain P
Document the Glymur OOBMSS PAS node with its secure GLink edge,
shared-memory signaling, firmware carveouts, and power resources.
Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
---
.../bindings/remoteproc/qcom,glymur-oob-pas.yaml | 156 +++++++++++++++++++++
1 file changed, 156 insertions(+)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,glymur-oob-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,glymur-oob-pas.yaml
new file mode 100644
index 000000000000..bd4f397da40f
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,glymur-oob-pas.yaml
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/remoteproc/qcom,glymur-oob-pas.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Glymur Out-of-Band Management Subsystem (OOBMSS) PAS
+
+maintainers:
+ - Anvesh Jain P <anvesh.p@oss.qualcomm.com>
+
+description: |
+ Qualcomm Glymur Out-of-Band Management Subsystem (OOBMSS) contains two
+ processors running Zephyr, managed together as one remoteproc instance.
+ The Out-of-Band Trusted Execution Environment (OOB-TEE) is the primary
+ processor. The OOB-Non-Secure processor is an auxiliary processor that
+ depends on the primary processor and cannot function independently.
+
+ The primary processor runs the primary image, while the auxiliary
+ processor runs the secondary image. Each processor has its own DTB.
+ The two images and their DTBs have separate PAS identifiers for
+ authentication and dedicated reserved-memory carveouts.
+
+ OOBMSS is booted by earlier-stage firmware and uses an XO clock and the
+ CX and MX power domains. Shared Memory Point-to-Point (SMP2P) provides
+ boot, shutdown, handover and ping/pong signaling, as well as fatal error
+ notifications. The subsystem exposes a secure GLink edge to the host,
+ with doorbell interrupts provided by the Inter-Processor Communication
+ Controller (IPCC).
+
+properties:
+ compatible:
+ enum:
+ - qcom,glymur-oobmss-pas
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: Watchdog interrupt
+ - description: Fatal interrupt
+ - description: Ready interrupt
+ - description: Handover interrupt
+ - description: Stop acknowledge interrupt
+ - description: Pong interrupt
+
+ interrupt-names:
+ items:
+ - const: wdog
+ - const: fatal
+ - const: ready
+ - const: handover
+ - const: stop-ack
+ - const: pong
+
+ clocks:
+ items:
+ - description: XO clock
+
+ clock-names:
+ items:
+ - const: xo
+
+ power-domains:
+ items:
+ - description: CX power domain
+ - description: MX power domain
+
+ power-domain-names:
+ items:
+ - const: cx
+ - const: mx
+
+ memory-region:
+ items:
+ - description: Secure firmware carveout
+ - description: Secure device tree carveout
+ - description: Non-secure firmware carveout
+ - description: Non-secure device tree carveout
+
+ firmware-name:
+ items:
+ - description: Secure firmware
+ - description: Secure device tree firmware
+ - description: Non-secure firmware
+ - description: Non-secure device tree firmware
+
+ qcom,smem-states:
+ minItems: 2
+ description: States used by the AP to signal OOBMSS
+
+ qcom,smem-state-names:
+ minItems: 2
+ description: The names of the state bits used for SMP2P output
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - power-domain-names
+ - memory-region
+
+allOf:
+ - $ref: /schemas/remoteproc/qcom,pas-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/mailbox/qcom-ipcc.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ #define IPCC_MPROC_OOB_S 56
+ #define IPCC_MPROC_OOB 55
+
+ remoteproc@1f000000 {
+ compatible = "qcom,glymur-oobmss-pas";
+ reg = <0x1f000000 0x30000>;
+
+ interrupts-extended = <&intc GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_oobmss_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_oobmss_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_oobmss_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_oobmss_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_oobmss_in 9 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "pong";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "cx", "mx";
+
+ memory-region = <&oob_secure_mem>, <&oobdtbqc_mem>,
+ <&oob_nonsecure_mem>, <&oobdtboem_mem>;
+ firmware-name = "qcom/glymur/oobmss_tee.mbn",
+ "qcom/glymur/oobmss_qc_dtb.mbn",
+ "qcom/glymur/oobmss_ns.mbn",
+ "qcom/glymur/oobmss_oem_dtb.mbn";
+ qcom,smem-states = <&smp2p_oobmss_out 1>,
+ <&smp2p_oobmss_out 8>;
+ qcom,smem-state-names = "stop", "ping";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_MPROC_OOB_S
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_MPROC_OOB_S IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ label = "oobmss";
+ qcom,remote-pid = <20>;
+ };
+
+ };
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/4] dt-bindings: remoteproc: qcom: Add Glymur OOBMSS PAS binding
2026-10-09 7:17 ` [PATCH 1/4] dt-bindings: remoteproc: qcom: Add Glymur OOBMSS PAS binding Anvesh Jain P
@ 2026-10-12 8:55 ` Krzysztof Kozlowski
2026-10-12 9:36 ` Anvesh Jain P
0 siblings, 1 reply; 12+ messages in thread
From: Krzysztof Kozlowski @ 2026-10-12 8:55 UTC (permalink / raw)
To: Anvesh Jain P
Cc: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, Sibi Sankar
On Fri, Oct 09, 2026 at 12:47:39PM +0530, Anvesh Jain P wrote:
> Document the Glymur OOBMSS PAS node with its secure GLink edge,
> shared-memory signaling, firmware carveouts, and power resources.
>
A nit, subject: drop second/last, redundant "binding". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v7.1-rc7/source/Documentation/devicetree/bindings/submitting-patches.rst#L23
> Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
> ---
> .../bindings/remoteproc/qcom,glymur-oob-pas.yaml | 156 +++++++++++++++++++++
> 1 file changed, 156 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,glymur-oob-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,glymur-oob-pas.yaml
> new file mode 100644
> index 000000000000..bd4f397da40f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,glymur-oob-pas.yaml
> @@ -0,0 +1,156 @@
> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/remoteproc/qcom,glymur-oob-pas.yaml#
Filename must match the compatible.
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Glymur Out-of-Band Management Subsystem (OOBMSS) PAS
> +
> +maintainers:
> + - Anvesh Jain P <anvesh.p@oss.qualcomm.com>
> +
> +description: |
> + Qualcomm Glymur Out-of-Band Management Subsystem (OOBMSS) contains two
> + processors running Zephyr, managed together as one remoteproc instance.
> + The Out-of-Band Trusted Execution Environment (OOB-TEE) is the primary
> + processor. The OOB-Non-Secure processor is an auxiliary processor that
> + depends on the primary processor and cannot function independently.
> +
> + The primary processor runs the primary image, while the auxiliary
> + processor runs the secondary image. Each processor has its own DTB.
> + The two images and their DTBs have separate PAS identifiers for
> + authentication and dedicated reserved-memory carveouts.
> +
> + OOBMSS is booted by earlier-stage firmware and uses an XO clock and the
> + CX and MX power domains. Shared Memory Point-to-Point (SMP2P) provides
> + boot, shutdown, handover and ping/pong signaling, as well as fatal error
> + notifications. The subsystem exposes a secure GLink edge to the host,
> + with doorbell interrupts provided by the Inter-Processor Communication
> + Controller (IPCC).
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,glymur-oobmss-pas
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + items:
> + - description: Watchdog interrupt
> + - description: Fatal interrupt
> + - description: Ready interrupt
> + - description: Handover interrupt
> + - description: Stop acknowledge interrupt
> + - description: Pong interrupt
> +
> + interrupt-names:
> + items:
> + - const: wdog
> + - const: fatal
> + - const: ready
> + - const: handover
> + - const: stop-ack
> + - const: pong
> +
> + clocks:
> + items:
> + - description: XO clock
> +
> + clock-names:
> + items:
> + - const: xo
> +
> + power-domains:
> + items:
> + - description: CX power domain
> + - description: MX power domain
> +
> + power-domain-names:
> + items:
> + - const: cx
> + - const: mx
> +
> + memory-region:
> + items:
> + - description: Secure firmware carveout
> + - description: Secure device tree carveout
> + - description: Non-secure firmware carveout
> + - description: Non-secure device tree carveout
> +
> + firmware-name:
> + items:
> + - description: Secure firmware
> + - description: Secure device tree firmware
> + - description: Non-secure firmware
> + - description: Non-secure device tree firmware
> +
> + qcom,smem-states:
> + minItems: 2
> + description: States used by the AP to signal OOBMSS
> +
> + qcom,smem-state-names:
> + minItems: 2
> + description: The names of the state bits used for SMP2P output
> +
> +required:
> + - compatible
> + - reg
> + - power-domains
> + - power-domain-names
> + - memory-region
firmware-name as well, I guess?
> +
> +allOf:
> + - $ref: /schemas/remoteproc/qcom,pas-common.yaml#
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,rpmh.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/mailbox/qcom-ipcc.h>
> + #include <dt-bindings/power/qcom,rpmhpd.h>
> + #define IPCC_MPROC_OOB_S 56
> + #define IPCC_MPROC_OOB 55
Drop these two
> +
> + remoteproc@1f000000 {
> + compatible = "qcom,glymur-oobmss-pas";
> + reg = <0x1f000000 0x30000>;
> +
> + interrupts-extended = <&intc GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_oobmss_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_oobmss_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_oobmss_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_oobmss_in 3 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_oobmss_in 9 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "pong";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "xo";
> + power-domains = <&rpmhpd RPMHPD_CX>,
> + <&rpmhpd RPMHPD_MX>;
> + power-domain-names = "cx", "mx";
> +
> + memory-region = <&oob_secure_mem>, <&oobdtbqc_mem>,
> + <&oob_nonsecure_mem>, <&oobdtboem_mem>;
> + firmware-name = "qcom/glymur/oobmss_tee.mbn",
> + "qcom/glymur/oobmss_qc_dtb.mbn",
> + "qcom/glymur/oobmss_ns.mbn",
> + "qcom/glymur/oobmss_oem_dtb.mbn";
> + qcom,smem-states = <&smp2p_oobmss_out 1>,
> + <&smp2p_oobmss_out 8>;
> + qcom,smem-state-names = "stop", "ping";
> +
> + glink-edge {
> + interrupts-extended = <&ipcc IPCC_MPROC_OOB_S
Just use numbers here
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/4] dt-bindings: remoteproc: qcom: Add Glymur OOBMSS PAS binding
2026-10-12 8:55 ` Krzysztof Kozlowski
@ 2026-10-12 9:36 ` Anvesh Jain P
2026-10-12 10:27 ` Krzysztof Kozlowski
0 siblings, 1 reply; 12+ messages in thread
From: Anvesh Jain P @ 2026-10-12 9:36 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, Sibi Sankar
On 10/12/2026 2:25 PM, Krzysztof Kozlowski wrote:
> On Fri, Oct 09, 2026 at 12:47:39PM +0530, Anvesh Jain P wrote:
>> Document the Glymur OOBMSS PAS node with its secure GLink edge,
>> shared-memory signaling, firmware carveouts, and power resources.
>>
>
> A nit, subject: drop second/last, redundant "binding". The
> "dt-bindings" prefix is already stating that these are bindings.
> See also:
> https://elixir.bootlin.com/linux/v7.1-rc7/source/Documentation/devicetree/bindings/submitting-patches.rst#L23
>
Hi Krzysztof,
Thanks for reviewing this series. I’ll drop the redundant “binding” from
the subject in the next revision.
>> Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
>> ---
>> .../bindings/remoteproc/qcom,glymur-oob-pas.yaml | 156 +++++++++++++++++++++
>> 1 file changed, 156 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,glymur-oob-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,glymur-oob-pas.yaml
>> new file mode 100644
>> index 000000000000..bd4f397da40f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,glymur-oob-pas.yaml
>> @@ -0,0 +1,156 @@
>> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/remoteproc/qcom,glymur-oob-pas.yaml#
>
> Filename must match the compatible.
>
Ack, will rename binding file.
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Glymur Out-of-Band Management Subsystem (OOBMSS) PAS
>> +
>> +maintainers:
>> + - Anvesh Jain P <anvesh.p@oss.qualcomm.com>
>> +
>> +description: |
>> + Qualcomm Glymur Out-of-Band Management Subsystem (OOBMSS) contains two
>> + processors running Zephyr, managed together as one remoteproc instance.
>> + The Out-of-Band Trusted Execution Environment (OOB-TEE) is the primary
>> + processor. The OOB-Non-Secure processor is an auxiliary processor that
>> + depends on the primary processor and cannot function independently.
>> +
>> + The primary processor runs the primary image, while the auxiliary
>> + processor runs the secondary image. Each processor has its own DTB.
>> + The two images and their DTBs have separate PAS identifiers for
>> + authentication and dedicated reserved-memory carveouts.
>> +
>> + OOBMSS is booted by earlier-stage firmware and uses an XO clock and the
>> + CX and MX power domains. Shared Memory Point-to-Point (SMP2P) provides
>> + boot, shutdown, handover and ping/pong signaling, as well as fatal error
>> + notifications. The subsystem exposes a secure GLink edge to the host,
>> + with doorbell interrupts provided by the Inter-Processor Communication
>> + Controller (IPCC).
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - qcom,glymur-oobmss-pas
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + interrupts:
>> + items:
>> + - description: Watchdog interrupt
>> + - description: Fatal interrupt
>> + - description: Ready interrupt
>> + - description: Handover interrupt
>> + - description: Stop acknowledge interrupt
>> + - description: Pong interrupt
>> +
>> + interrupt-names:
>> + items:
>> + - const: wdog
>> + - const: fatal
>> + - const: ready
>> + - const: handover
>> + - const: stop-ack
>> + - const: pong
>> +
>> + clocks:
>> + items:
>> + - description: XO clock
>> +
>> + clock-names:
>> + items:
>> + - const: xo
>> +
>> + power-domains:
>> + items:
>> + - description: CX power domain
>> + - description: MX power domain
>> +
>> + power-domain-names:
>> + items:
>> + - const: cx
>> + - const: mx
>> +
>> + memory-region:
>> + items:
>> + - description: Secure firmware carveout
>> + - description: Secure device tree carveout
>> + - description: Non-secure firmware carveout
>> + - description: Non-secure device tree carveout
>> +
>> + firmware-name:
>> + items:
>> + - description: Secure firmware
>> + - description: Secure device tree firmware
>> + - description: Non-secure firmware
>> + - description: Non-secure device tree firmware
>> +
>> + qcom,smem-states:
>> + minItems: 2
>> + description: States used by the AP to signal OOBMSS
>> +
>> + qcom,smem-state-names:
>> + minItems: 2
>> + description: The names of the state bits used for SMP2P output
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - power-domains
>> + - power-domain-names
>> + - memory-region
>
> firmware-name as well, I guess?
>
>
I think firmware-name should remain optional. The driver provides
defaults when loading images, and attach-only operation does not request
firmware.
>> +
>> +allOf:
>> + - $ref: /schemas/remoteproc/qcom,pas-common.yaml#
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,rpmh.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/interrupt-controller/irq.h>
>> + #include <dt-bindings/mailbox/qcom-ipcc.h>
>> + #include <dt-bindings/power/qcom,rpmhpd.h>
>> + #define IPCC_MPROC_OOB_S 56
>> + #define IPCC_MPROC_OOB 55
>
> Drop these two
>
noted, will remove these definition.
>> +
>> + remoteproc@1f000000 {
>> + compatible = "qcom,glymur-oobmss-pas";
>> + reg = <0x1f000000 0x30000>;
>> +
>> + interrupts-extended = <&intc GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_oobmss_in 0 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_oobmss_in 1 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_oobmss_in 2 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_oobmss_in 3 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_oobmss_in 9 IRQ_TYPE_EDGE_RISING>;
>> + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "pong";
>> +
>> + clocks = <&rpmhcc RPMH_CXO_CLK>;
>> + clock-names = "xo";
>> + power-domains = <&rpmhpd RPMHPD_CX>,
>> + <&rpmhpd RPMHPD_MX>;
>> + power-domain-names = "cx", "mx";
>> +
>> + memory-region = <&oob_secure_mem>, <&oobdtbqc_mem>,
>> + <&oob_nonsecure_mem>, <&oobdtboem_mem>;
>> + firmware-name = "qcom/glymur/oobmss_tee.mbn",
>> + "qcom/glymur/oobmss_qc_dtb.mbn",
>> + "qcom/glymur/oobmss_ns.mbn",
>> + "qcom/glymur/oobmss_oem_dtb.mbn";
>> + qcom,smem-states = <&smp2p_oobmss_out 1>,
>> + <&smp2p_oobmss_out 8>;
>> + qcom,smem-state-names = "stop", "ping";
>> +
>> + glink-edge {
>> + interrupts-extended = <&ipcc IPCC_MPROC_OOB_S
>
> Just use numbers here
>
Ack.
> Best regards,
> Krzysztof
--
Best Regards,
Anvesh
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/4] dt-bindings: remoteproc: qcom: Add Glymur OOBMSS PAS binding
2026-10-12 9:36 ` Anvesh Jain P
@ 2026-10-12 10:27 ` Krzysztof Kozlowski
0 siblings, 0 replies; 12+ messages in thread
From: Krzysztof Kozlowski @ 2026-10-12 10:27 UTC (permalink / raw)
To: Anvesh Jain P
Cc: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, Sibi Sankar
On 12/10/2026 11:36, Anvesh Jain P wrote:
>>> +required:
>>> + - compatible
>>> + - reg
>>> + - power-domains
>>> + - power-domain-names
>>> + - memory-region
>>
>> firmware-name as well, I guess?
>>
>>
>
> I think firmware-name should remain optional. The driver provides
> defaults when loading images, and attach-only operation does not request
> firmware.
ack
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/4] remoteproc: qcom: pas: Support secondary images
2026-10-09 7:17 [PATCH 0/4] Add Glymur OOBMSS support Anvesh Jain P
2026-10-09 7:17 ` [PATCH 1/4] dt-bindings: remoteproc: qcom: Add Glymur OOBMSS PAS binding Anvesh Jain P
@ 2026-10-09 7:17 ` Anvesh Jain P
2026-10-09 7:17 ` [PATCH 3/4] remoteproc: qcom: pas: Add Glymur OOBMSS PAS parameters Anvesh Jain P
2026-10-09 7:17 ` [PATCH 4/4] remoteproc: qcom: pas: Add Glymur OOBMSS coredump support Anvesh Jain P
3 siblings, 0 replies; 12+ messages in thread
From: Anvesh Jain P @ 2026-10-09 7:17 UTC (permalink / raw)
To: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio
Cc: linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
Sibi Sankar, Anvesh Jain P
The Out-of-Band Management Subsystem (OOBMSS) is managed by a common
remote processor and consists of two Zephyr subsystems:
+----------------------------------------------------------+
| OOBMSS |
| |
| +------------------------+ +------------------------+ |
| | OOB-TEE | | OOB-Non-Secure | |
| | Primary processor | | Auxiliary processor | |
| | Primary image and DTB | | Secondary image and DTB| |
| +------------------------+ +------------------------+ |
+----------------------------------------------------------+
The primary processor is the Out-of-Band Trusted Execution Environment
(OOB-TEE) processor. The OOB-Non-Secure processor is an auxiliary processor
that depends on the primary processor and cannot function independently.
The PAS remoteproc driver currently supports one primary image and its
optional DTB. OOBMSS additionally requires the secondary image and DTB
to be loaded, authenticated, mapped, shut down, and released through
their own PAS identifiers and carveouts.
Add generic PAS support for loading, authenticating, and mapping a
secondary image and its DTB, then shutting down and releasing both while
keeping the existing primary-image lifecycle unchanged.
Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
---
drivers/remoteproc/qcom_q6v5_pas.c | 235 ++++++++++++++++++++++++++++++++++---
1 file changed, 218 insertions(+), 17 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index ca8e61254c44..604dfa947340 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -42,8 +42,12 @@ struct qcom_pas_data {
int crash_reason_smem;
const char *firmware_name;
const char *dtb_firmware_name;
+ const char *secondary_firmware_name;
+ const char *secondary_dtb_firmware_name;
int pas_id;
int dtb_pas_id;
+ int secondary_pas_id;
+ int secondary_dtb_pas_id;
int lite_pas_id;
int lite_dtb_pas_id;
unsigned int minidump_id;
@@ -83,8 +87,12 @@ struct qcom_pas {
int proxy_pd_count;
const char *dtb_firmware_name;
+ const char *secondary_firmware_name;
+ const char *secondary_dtb_firmware_name;
int pas_id;
int dtb_pas_id;
+ int secondary_pas_id;
+ int secondary_dtb_pas_id;
int lite_pas_id;
int lite_dtb_pas_id;
unsigned int minidump_id;
@@ -95,17 +103,25 @@ struct qcom_pas {
const struct firmware *firmware;
const struct firmware *dtb_firmware;
+ const struct firmware *secondary_firmware;
+ const struct firmware *secondary_dtb_firmware;
phys_addr_t mem_phys;
phys_addr_t dtb_mem_phys;
+ phys_addr_t secondary_mem_phys;
+ phys_addr_t secondary_dtb_mem_phys;
phys_addr_t mem_reloc;
phys_addr_t dtb_mem_reloc;
+ phys_addr_t secondary_mem_reloc;
+ phys_addr_t secondary_dtb_mem_reloc;
phys_addr_t region_assign_phys[MAX_ASSIGN_COUNT];
void __iomem *mem_region;
size_t mem_size;
size_t dtb_mem_size;
+ size_t secondary_mem_size;
+ size_t secondary_dtb_mem_size;
size_t region_assign_size[MAX_ASSIGN_COUNT];
int region_assign_idx;
@@ -123,6 +139,8 @@ struct qcom_pas {
struct qcom_pas_context *pas_ctx;
struct qcom_pas_context *dtb_pas_ctx;
+ struct qcom_pas_context *secondary_pas_ctx;
+ struct qcom_pas_context *secondary_dtb_pas_ctx;
};
static void qcom_pas_segment_dump(struct rproc *rproc,
@@ -198,19 +216,37 @@ static void qcom_pas_pds_disable(struct qcom_pas *pas, struct device **pds,
}
}
-static int qcom_pas_shutdown_poll_decrypt(struct qcom_pas *pas)
+static int qcom_pas_shutdown_poll_decrypt(int pas_id)
{
unsigned int retry_num = 50;
int ret;
do {
msleep(QCOM_PAS_DECRYPT_SHUTDOWN_DELAY_MS);
- ret = qcom_pas_shutdown(pas->pas_id);
+ ret = qcom_pas_shutdown(pas_id);
} while (ret == -EINVAL && --retry_num);
return ret;
}
+static void qcom_pas_release_firmware(struct qcom_pas *pas)
+{
+ if (pas->dtb_firmware) {
+ release_firmware(pas->dtb_firmware);
+ pas->dtb_firmware = NULL;
+ }
+
+ if (pas->secondary_firmware) {
+ release_firmware(pas->secondary_firmware);
+ pas->secondary_firmware = NULL;
+ }
+
+ if (pas->secondary_dtb_firmware) {
+ release_firmware(pas->secondary_dtb_firmware);
+ pas->secondary_dtb_firmware = NULL;
+ }
+}
+
static int qcom_pas_unprepare(struct rproc *rproc)
{
struct qcom_pas *pas = rproc->priv;
@@ -224,6 +260,10 @@ static int qcom_pas_unprepare(struct rproc *rproc)
qcom_pas_metadata_release(pas->pas_ctx);
if (pas->dtb_pas_id)
qcom_pas_metadata_release(pas->dtb_pas_ctx);
+ if (pas->secondary_pas_id)
+ qcom_pas_metadata_release(pas->secondary_pas_ctx);
+ if (pas->secondary_dtb_pas_id)
+ qcom_pas_metadata_release(pas->secondary_dtb_pas_ctx);
return 0;
}
@@ -241,19 +281,29 @@ static int qcom_pas_load(struct rproc *rproc, const struct firmware *fw)
if (pas->lite_dtb_pas_id)
qcom_pas_shutdown(pas->lite_dtb_pas_id);
- if (pas->dtb_pas_id) {
- ret = request_firmware(&pas->dtb_firmware, pas->dtb_firmware_name, pas->dev);
+ if (pas->secondary_dtb_pas_id) {
+ ret = request_firmware(&pas->secondary_dtb_firmware,
+ pas->secondary_dtb_firmware_name, pas->dev);
+ if (ret) {
+ qcom_pas_release_firmware(pas);
+ return ret;
+ }
+ }
+
+ if (pas->secondary_pas_id) {
+ ret = request_firmware(&pas->secondary_firmware,
+ pas->secondary_firmware_name, pas->dev);
if (ret) {
- dev_err(pas->dev, "request_firmware failed for %s: %d\n",
- pas->dtb_firmware_name, ret);
+ qcom_pas_release_firmware(pas);
return ret;
}
+ }
- ret = qcom_mdt_pas_load(pas->dtb_pas_ctx, pas->dtb_firmware,
- pas->dtb_firmware_name, &pas->dtb_mem_reloc);
+ if (pas->dtb_pas_id) {
+ ret = request_firmware(&pas->dtb_firmware, pas->dtb_firmware_name,
+ pas->dev);
if (ret) {
- qcom_pas_metadata_release(pas->dtb_pas_ctx);
- release_firmware(pas->dtb_firmware);
+ qcom_pas_release_firmware(pas);
return ret;
}
}
@@ -310,10 +360,51 @@ static int qcom_pas_start(struct rproc *rproc)
goto disable_cx_supply;
}
+ if (pas->secondary_dtb_pas_id) {
+ ret = qcom_mdt_pas_load(pas->secondary_dtb_pas_ctx,
+ pas->secondary_dtb_firmware,
+ pas->secondary_dtb_firmware_name,
+ &pas->secondary_dtb_mem_reloc);
+ if (ret)
+ goto disable_px_supply;
+
+ ret = qcom_pas_map_carveout(rproc, pas->secondary_dtb_mem_phys,
+ pas->secondary_dtb_mem_size);
+ if (ret)
+ goto release_secondary_dtb_metadata;
+
+ ret = qcom_pas_prepare_and_auth_reset(pas->secondary_dtb_pas_ctx);
+ if (ret)
+ goto unmap_secondary_dtb_carveout;
+ }
+
+ if (pas->secondary_pas_id) {
+ ret = qcom_mdt_pas_load(pas->secondary_pas_ctx,
+ pas->secondary_firmware,
+ pas->secondary_firmware_name,
+ &pas->secondary_mem_reloc);
+ if (ret)
+ goto unmap_secondary_dtb_carveout;
+
+ ret = qcom_pas_map_carveout(rproc, pas->secondary_mem_phys,
+ pas->secondary_mem_size);
+ if (ret)
+ goto release_secondary_metadata;
+
+ ret = qcom_pas_prepare_and_auth_reset(pas->secondary_pas_ctx);
+ if (ret)
+ goto unmap_secondary_carveout;
+ }
+
if (pas->dtb_pas_id) {
+ ret = qcom_mdt_pas_load(pas->dtb_pas_ctx, pas->dtb_firmware,
+ pas->dtb_firmware_name, &pas->dtb_mem_reloc);
+ if (ret)
+ goto unmap_secondary_carveout;
+
ret = qcom_pas_map_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_size);
if (ret)
- goto disable_px_supply;
+ goto release_dtb_metadata;
ret = qcom_pas_prepare_and_auth_reset(pas->dtb_pas_ctx);
if (ret) {
@@ -326,7 +417,7 @@ static int qcom_pas_start(struct rproc *rproc)
ret = qcom_mdt_pas_load(pas->pas_ctx, pas->firmware, rproc->firmware,
&pas->mem_reloc);
if (ret)
- goto release_pas_metadata;
+ goto unmap_dtb_carveout;
qcom_pil_info_store(pas->info_name, pas->mem_phys, pas->mem_size);
@@ -351,6 +442,10 @@ static int qcom_pas_start(struct rproc *rproc)
qcom_pas_metadata_release(pas->pas_ctx);
if (pas->dtb_pas_id)
qcom_pas_metadata_release(pas->dtb_pas_ctx);
+ if (pas->secondary_pas_id)
+ qcom_pas_metadata_release(pas->secondary_pas_ctx);
+ if (pas->secondary_dtb_pas_id)
+ qcom_pas_metadata_release(pas->secondary_dtb_pas_ctx);
/* firmware is used to pass reference from qcom_pas_start(), drop it now */
pas->firmware = NULL;
@@ -361,12 +456,27 @@ static int qcom_pas_start(struct rproc *rproc)
qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size);
release_pas_metadata:
qcom_pas_metadata_release(pas->pas_ctx);
- if (pas->dtb_pas_id)
- qcom_pas_metadata_release(pas->dtb_pas_ctx);
-
unmap_dtb_carveout:
if (pas->dtb_pas_id)
- qcom_pas_unmap_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_size);
+ qcom_pas_unmap_carveout(rproc, pas->dtb_mem_phys,
+ pas->dtb_mem_size);
+release_dtb_metadata:
+ if (pas->dtb_pas_id)
+ qcom_pas_metadata_release(pas->dtb_pas_ctx);
+unmap_secondary_carveout:
+ if (pas->secondary_pas_id)
+ qcom_pas_unmap_carveout(rproc, pas->secondary_mem_phys,
+ pas->secondary_mem_size);
+release_secondary_metadata:
+ if (pas->secondary_pas_id)
+ qcom_pas_metadata_release(pas->secondary_pas_ctx);
+unmap_secondary_dtb_carveout:
+ if (pas->secondary_dtb_pas_id)
+ qcom_pas_unmap_carveout(rproc, pas->secondary_dtb_mem_phys,
+ pas->secondary_dtb_mem_size);
+release_secondary_dtb_metadata:
+ if (pas->secondary_dtb_pas_id)
+ qcom_pas_metadata_release(pas->secondary_dtb_pas_ctx);
disable_px_supply:
if (pas->px_supply)
regulator_disable(pas->px_supply);
@@ -413,7 +523,7 @@ static int qcom_pas_stop(struct rproc *rproc)
ret = qcom_pas_shutdown(pas->pas_id);
if (ret && pas->decrypt_shutdown)
- ret = qcom_pas_shutdown_poll_decrypt(pas);
+ ret = qcom_pas_shutdown_poll_decrypt(pas->pas_id);
if (ret)
dev_err(pas->dev, "failed to shutdown: %d\n", ret);
@@ -426,6 +536,27 @@ static int qcom_pas_stop(struct rproc *rproc)
qcom_pas_unmap_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_size);
}
+ if (pas->secondary_pas_id) {
+ ret = qcom_pas_shutdown(pas->secondary_pas_id);
+ if (ret && pas->decrypt_shutdown)
+ ret = qcom_pas_shutdown_poll_decrypt(pas->secondary_pas_id);
+ if (ret)
+ dev_err(pas->dev, "failed to shutdown secondary: %d\n", ret);
+
+ qcom_pas_unmap_carveout(rproc, pas->secondary_mem_phys,
+ pas->secondary_mem_size);
+ }
+
+ if (pas->secondary_dtb_pas_id) {
+ ret = qcom_pas_shutdown(pas->secondary_dtb_pas_id);
+ if (ret)
+ dev_err(pas->dev,
+ "failed to shutdown secondary dtb: %d\n", ret);
+
+ qcom_pas_unmap_carveout(rproc, pas->secondary_dtb_mem_phys,
+ pas->secondary_dtb_mem_size);
+ }
+
qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size);
handover = qcom_q6v5_unprepare(&pas->q6v5);
@@ -740,6 +871,42 @@ static int qcom_pas_alloc_memory_region(struct qcom_pas *pas)
if (IS_ERR(pas->dtb_pas_ctx))
return PTR_ERR(pas->dtb_pas_ctx);
+ if (!pas->secondary_pas_id)
+ return 0;
+
+ ret = of_reserved_mem_region_to_resource(pas->dev->of_node, 2, &res);
+ if (ret)
+ return ret;
+
+ pas->secondary_mem_phys = res.start;
+ pas->secondary_mem_reloc = res.start;
+ pas->secondary_mem_size = resource_size(&res);
+
+ pas->secondary_pas_ctx =
+ devm_qcom_pas_context_alloc(pas->dev, pas->secondary_pas_id,
+ pas->secondary_mem_phys,
+ pas->secondary_mem_size);
+ if (IS_ERR(pas->secondary_pas_ctx))
+ return PTR_ERR(pas->secondary_pas_ctx);
+
+ if (!pas->secondary_dtb_pas_id)
+ return 0;
+
+ ret = of_reserved_mem_region_to_resource(pas->dev->of_node, 3, &res);
+ if (ret)
+ return ret;
+
+ pas->secondary_dtb_mem_phys = res.start;
+ pas->secondary_dtb_mem_reloc = res.start;
+ pas->secondary_dtb_mem_size = resource_size(&res);
+
+ pas->secondary_dtb_pas_ctx =
+ devm_qcom_pas_context_alloc(pas->dev, pas->secondary_dtb_pas_id,
+ pas->secondary_dtb_mem_phys,
+ pas->secondary_dtb_mem_size);
+ if (IS_ERR(pas->secondary_dtb_pas_ctx))
+ return PTR_ERR(pas->secondary_dtb_pas_ctx);
+
return 0;
}
@@ -823,6 +990,8 @@ static int qcom_pas_probe(struct platform_device *pdev)
struct rproc *rproc;
struct device_node *node;
const char *fw_name, *dtb_fw_name = NULL;
+ const char *secondary_fw_name = NULL;
+ const char *secondary_dtb_fw_name = NULL;
const struct rproc_ops *ops = &qcom_pas_ops;
int ret;
@@ -847,6 +1016,24 @@ static int qcom_pas_probe(struct platform_device *pdev)
return ret;
}
+ if (desc->secondary_firmware_name) {
+ secondary_fw_name = desc->secondary_firmware_name;
+ ret = of_property_read_string_index(pdev->dev.of_node,
+ "firmware-name", 2,
+ &secondary_fw_name);
+ if (ret < 0 && ret != -EINVAL)
+ return ret;
+ }
+
+ if (desc->secondary_dtb_firmware_name) {
+ secondary_dtb_fw_name = desc->secondary_dtb_firmware_name;
+ ret = of_property_read_string_index(pdev->dev.of_node,
+ "firmware-name", 3,
+ &secondary_dtb_fw_name);
+ if (ret < 0 && ret != -EINVAL)
+ return ret;
+ }
+
if (desc->minidump_id)
ops = &qcom_pas_minidump_ops;
@@ -868,6 +1055,8 @@ static int qcom_pas_probe(struct platform_device *pdev)
pas->pas_id = desc->pas_id;
pas->lite_pas_id = desc->lite_pas_id;
pas->lite_dtb_pas_id = desc->lite_dtb_pas_id;
+ pas->secondary_pas_id = desc->secondary_pas_id;
+ pas->secondary_dtb_pas_id = desc->secondary_dtb_pas_id;
pas->info_name = desc->sysmon_name;
pas->smem_host_id = desc->smem_host_id;
pas->decrypt_shutdown = desc->decrypt_shutdown;
@@ -879,6 +1068,14 @@ static int qcom_pas_probe(struct platform_device *pdev)
pas->dtb_firmware_name = dtb_fw_name;
pas->dtb_pas_id = desc->dtb_pas_id;
}
+ if (secondary_fw_name) {
+ pas->secondary_firmware_name = secondary_fw_name;
+ pas->secondary_pas_id = desc->secondary_pas_id;
+ }
+ if (secondary_dtb_fw_name) {
+ pas->secondary_dtb_firmware_name = secondary_dtb_fw_name;
+ pas->secondary_dtb_pas_id = desc->secondary_dtb_pas_id;
+ }
platform_set_drvdata(pdev, pas);
ret = device_init_wakeup(pas->dev, true);
@@ -925,6 +1122,10 @@ static int qcom_pas_probe(struct platform_device *pdev)
pas->pas_ctx->use_tzmem = desc->needs_tzmem || rproc->has_iommu;
if (pas->dtb_pas_id)
pas->dtb_pas_ctx->use_tzmem = desc->needs_tzmem || rproc->has_iommu;
+ if (pas->secondary_pas_id)
+ pas->secondary_pas_ctx->use_tzmem = desc->needs_tzmem || rproc->has_iommu;
+ if (pas->secondary_dtb_pas_id)
+ pas->secondary_dtb_pas_ctx->use_tzmem = desc->needs_tzmem || rproc->has_iommu;
if (desc->early_boot)
pas->rproc->state = RPROC_DETACHED;
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 3/4] remoteproc: qcom: pas: Add Glymur OOBMSS PAS parameters
2026-10-09 7:17 [PATCH 0/4] Add Glymur OOBMSS support Anvesh Jain P
2026-10-09 7:17 ` [PATCH 1/4] dt-bindings: remoteproc: qcom: Add Glymur OOBMSS PAS binding Anvesh Jain P
2026-10-09 7:17 ` [PATCH 2/4] remoteproc: qcom: pas: Support secondary images Anvesh Jain P
@ 2026-10-09 7:17 ` Anvesh Jain P
2026-10-09 7:17 ` [PATCH 4/4] remoteproc: qcom: pas: Add Glymur OOBMSS coredump support Anvesh Jain P
3 siblings, 0 replies; 12+ messages in thread
From: Anvesh Jain P @ 2026-10-09 7:17 UTC (permalink / raw)
To: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio
Cc: linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
Sibi Sankar, Anvesh Jain P
The OOBMSS consists of separate OOB-TEE and OOB-NS Zephyr subsystems,
each with its own firmware, DTB, and dedicated PAS ID. Add support for
the OOBMSS PAS loader on Glymur platforms.
Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
---
drivers/remoteproc/qcom_q6v5_pas.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 604dfa947340..31fdde351bed 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -1997,6 +1997,30 @@ static const struct qcom_pas_data glymur_soccp_resource = {
.needs_tzmem = true,
};
+static const struct qcom_pas_data glymur_oobmss_resource = {
+ .crash_reason_smem = 669,
+ .firmware_name = "oobmss_tee.mbn",
+ .dtb_firmware_name = "oobmss_qc_dtb.mbn",
+ .secondary_firmware_name = "oobmss_ns.mbn",
+ .secondary_dtb_firmware_name = "oobmss_oem_dtb.mbn",
+ .pas_id = 0x42,
+ .dtb_pas_id = 0x43,
+ .secondary_pas_id = 0x44,
+ .secondary_dtb_pas_id = 0x45,
+ .proxy_pd_names = (char *[]){
+ "cx",
+ "mx",
+ NULL
+ },
+ .ssr_name = "oobmss",
+ .sysmon_name = "oobmss",
+ .ssctl_id = 0x21,
+ .auto_boot = true,
+ .early_boot = true,
+ .needs_tzmem = true,
+ .decrypt_shutdown = true,
+};
+
static const struct qcom_pas_data eliza_cdsp_resource = {
.crash_reason_smem = 601,
.firmware_name = "cdsp.mbn",
@@ -2025,6 +2049,7 @@ static const struct qcom_pas_data eliza_cdsp_resource = {
static const struct of_device_id qcom_pas_of_match[] = {
{ .compatible = "qcom,eliza-adsp-pas", .data = &sm8550_adsp_resource },
{ .compatible = "qcom,eliza-cdsp-pas", .data = &eliza_cdsp_resource },
+ { .compatible = "qcom,glymur-oobmss-pas", .data = &glymur_oobmss_resource },
{ .compatible = "qcom,glymur-soccp-pas", .data = &glymur_soccp_resource },
{ .compatible = "qcom,kaanapali-soccp-pas", .data = &kaanapali_soccp_resource },
{ .compatible = "qcom,milos-adsp-pas", .data = &sm8550_adsp_resource },
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 4/4] remoteproc: qcom: pas: Add Glymur OOBMSS coredump support
2026-10-09 7:17 [PATCH 0/4] Add Glymur OOBMSS support Anvesh Jain P
` (2 preceding siblings ...)
2026-10-09 7:17 ` [PATCH 3/4] remoteproc: qcom: pas: Add Glymur OOBMSS PAS parameters Anvesh Jain P
@ 2026-10-09 7:17 ` Anvesh Jain P
2026-10-12 8:56 ` Krzysztof Kozlowski
3 siblings, 1 reply; 12+ messages in thread
From: Anvesh Jain P @ 2026-10-09 7:17 UTC (permalink / raw)
To: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio
Cc: linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
Sibi Sankar, Anvesh Jain P
Add coredump support for the secure and non-secure OOBMSS carveouts.
Register fixed dump segments at probe time for attached-state recovery.
Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
---
drivers/remoteproc/qcom_q6v5_pas.c | 85 ++++++++++++++++++++++++++++++++++----
1 file changed, 77 insertions(+), 8 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 31fdde351bed..0dc9985f01f9 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -117,6 +117,7 @@ struct qcom_pas {
phys_addr_t region_assign_phys[MAX_ASSIGN_COUNT];
void __iomem *mem_region;
+ void __iomem *secondary_mem_region;
size_t mem_size;
size_t dtb_mem_size;
@@ -162,6 +163,28 @@ static void qcom_pas_segment_dump(struct rproc *rproc,
memcpy_fromio(dest, pas->mem_region + total_offset, size);
}
+static bool qcom_pas_has_secondary(const struct qcom_pas *pas)
+{
+ return pas->secondary_pas_id && pas->secondary_dtb_pas_id;
+}
+
+static int qcom_pas_register_dump_segments(struct rproc *rproc,
+ struct qcom_pas *pas)
+{
+ int ret;
+
+ ret = rproc_coredump_add_segment(rproc, pas->mem_phys, pas->mem_size);
+ if (ret)
+ return ret;
+
+ ret = rproc_coredump_add_segment(rproc, pas->secondary_mem_phys,
+ pas->secondary_mem_size);
+ if (ret)
+ rproc_coredump_cleanup(rproc);
+
+ return ret;
+}
+
static void qcom_pas_minidump(struct rproc *rproc)
{
struct qcom_pas *pas = rproc->priv;
@@ -572,16 +595,29 @@ static int qcom_pas_stop(struct rproc *rproc)
static void *qcom_pas_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
{
struct qcom_pas *pas = rproc->priv;
- int offset;
+ phys_addr_t base;
+ void __iomem *region;
+
+ if (da >= pas->mem_reloc && len <= pas->mem_size &&
+ da - pas->mem_reloc <= pas->mem_size - len) {
+ base = pas->mem_reloc;
+ region = pas->mem_region;
+ } else if (da >= pas->secondary_mem_reloc &&
+ len <= pas->secondary_mem_size &&
+ da - pas->secondary_mem_reloc <= pas->secondary_mem_size - len) {
+ base = pas->secondary_mem_reloc;
+ region = pas->secondary_mem_region;
+ } else {
+ return NULL;
+ }
- offset = da - pas->mem_reloc;
- if (offset < 0 || offset + len > pas->mem_size)
+ if (!region)
return NULL;
if (is_iomem)
*is_iomem = true;
- return (__force void *)pas->mem_region + offset;
+ return (__force void *)region + (da - base);
}
static int qcom_pas_parse_firmware(struct rproc *rproc, const struct firmware *fw)
@@ -593,10 +629,21 @@ static int qcom_pas_parse_firmware(struct rproc *rproc, const struct firmware *f
size_t table_sz;
int ret;
- ret = qcom_register_dump_segments(rproc, fw);
- if (ret) {
- dev_err(pas->dev, "Error in registering dump segments\n");
- return ret;
+ if (qcom_pas_has_secondary(pas)) {
+ if (list_empty(&rproc->dump_segments)) {
+ ret = qcom_pas_register_dump_segments(rproc, pas);
+ if (ret) {
+ dev_err(pas->dev,
+ "failed to register dump segments: %d\n", ret);
+ return ret;
+ }
+ }
+ } else {
+ ret = qcom_register_dump_segments(rproc, fw);
+ if (ret) {
+ dev_err(pas->dev, "Error in registering dump segments\n");
+ return ret;
+ }
}
if (!rproc->has_iommu)
@@ -715,7 +762,22 @@ static void qcom_pas_coredump(struct rproc *rproc)
if (!pas->mem_region)
return;
+ if (qcom_pas_has_secondary(pas)) {
+ pas->secondary_mem_region =
+ qcom_pas_ctx_map(pas->secondary_pas_ctx);
+ if (!pas->secondary_mem_region) {
+ dev_err(pas->dev, "unable to map secondary memory for coredump\n");
+ iounmap(pas->mem_region);
+ pas->mem_region = NULL;
+ return;
+ }
+ }
+
rproc_coredump(rproc);
+ if (pas->secondary_mem_region) {
+ iounmap(pas->secondary_mem_region);
+ pas->secondary_mem_region = NULL;
+ }
iounmap(pas->mem_region);
pas->mem_region = NULL;
}
@@ -1130,6 +1192,12 @@ static int qcom_pas_probe(struct platform_device *pdev)
if (desc->early_boot)
pas->rproc->state = RPROC_DETACHED;
+ if (qcom_pas_has_secondary(pas)) {
+ ret = qcom_pas_register_dump_segments(rproc, pas);
+ if (ret)
+ goto remove_ssr_sysmon;
+ }
+
ret = rproc_add(rproc);
if (ret)
goto remove_ssr_sysmon;
@@ -1141,6 +1209,7 @@ static int qcom_pas_probe(struct platform_device *pdev)
return 0;
remove_ssr_sysmon:
+ rproc_coredump_cleanup(rproc);
qcom_remove_ssr_subdev(rproc, &pas->ssr_subdev);
qcom_remove_sysmon_subdev(pas->sysmon);
deinit_remove_pdm_smd_glink:
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 4/4] remoteproc: qcom: pas: Add Glymur OOBMSS coredump support
2026-10-09 7:17 ` [PATCH 4/4] remoteproc: qcom: pas: Add Glymur OOBMSS coredump support Anvesh Jain P
@ 2026-10-12 8:56 ` Krzysztof Kozlowski
2026-10-12 9:50 ` Anvesh Jain P
0 siblings, 1 reply; 12+ messages in thread
From: Krzysztof Kozlowski @ 2026-10-12 8:56 UTC (permalink / raw)
To: Anvesh Jain P
Cc: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, Sibi Sankar
On Fri, Oct 09, 2026 at 12:47:42PM +0530, Anvesh Jain P wrote:
> Add coredump support for the secure and non-secure OOBMSS carveouts.
> Register fixed dump segments at probe time for attached-state recovery.
>
> Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
> ---
> drivers/remoteproc/qcom_q6v5_pas.c | 85 ++++++++++++++++++++++++++++++++++----
> 1 file changed, 77 insertions(+), 8 deletions(-)
Why is this separate from Glymur support? How is your device suppose to
work without this patch?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/4] remoteproc: qcom: pas: Add Glymur OOBMSS coredump support
2026-10-12 8:56 ` Krzysztof Kozlowski
@ 2026-10-12 9:50 ` Anvesh Jain P
2026-10-12 10:28 ` Krzysztof Kozlowski
0 siblings, 1 reply; 12+ messages in thread
From: Anvesh Jain P @ 2026-10-12 9:50 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, Sibi Sankar
On 10/12/2026 2:26 PM, Krzysztof Kozlowski wrote:
> On Fri, Oct 09, 2026 at 12:47:42PM +0530, Anvesh Jain P wrote:
>> Add coredump support for the secure and non-secure OOBMSS carveouts.
>> Register fixed dump segments at probe time for attached-state recovery.
>>
>> Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
>> ---
>> drivers/remoteproc/qcom_q6v5_pas.c | 85 ++++++++++++++++++++++++++++++++++----
>> 1 file changed, 77 insertions(+), 8 deletions(-)
>
> Why is this separate from Glymur support? How is your device suppose to
> work without this patch?
>
> Best regards,
> Krzysztof
This patch is diagnostic-only and is not required for OOBMSS boot or SSR
recovery; without it, the device works but no OOB coredump is collected.
I kept it separate to isolate the optional coredump support. I will make
the subject and description generic for coredump support on PAS
subsystems with secondary processors, rather than limiting it to
Glymur/OOBMSS.
--
Best Regards,
Anvesh
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/4] remoteproc: qcom: pas: Add Glymur OOBMSS coredump support
2026-10-12 9:50 ` Anvesh Jain P
@ 2026-10-12 10:28 ` Krzysztof Kozlowski
2026-10-12 15:33 ` Anvesh Jain P
0 siblings, 1 reply; 12+ messages in thread
From: Krzysztof Kozlowski @ 2026-10-12 10:28 UTC (permalink / raw)
To: Anvesh Jain P
Cc: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, Sibi Sankar
On 12/10/2026 11:50, Anvesh Jain P wrote:
>
>
> On 10/12/2026 2:26 PM, Krzysztof Kozlowski wrote:
>> On Fri, Oct 09, 2026 at 12:47:42PM +0530, Anvesh Jain P wrote:
>>> Add coredump support for the secure and non-secure OOBMSS carveouts.
>>> Register fixed dump segments at probe time for attached-state recovery.
>>>
>>> Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
>>> ---
>>> drivers/remoteproc/qcom_q6v5_pas.c | 85 ++++++++++++++++++++++++++++++++++----
>>> 1 file changed, 77 insertions(+), 8 deletions(-)
>>
>> Why is this separate from Glymur support? How is your device suppose to
>> work without this patch?
>>
>> Best regards,
>> Krzysztof
>
> This patch is diagnostic-only and is not required for OOBMSS boot or SSR
> recovery; without it, the device works but no OOB coredump is collected.
>
> I kept it separate to isolate the optional coredump support. I will make
> the subject and description generic for coredump support on PAS
> subsystems with secondary processors, rather than limiting it to
> Glymur/OOBMSS.
>
Commit msg probably should mention that "recovery" is here for
debugging, not proper device operation. Otherwise single commit, if
moderately small, is usually bringing entire support for a device.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/4] remoteproc: qcom: pas: Add Glymur OOBMSS coredump support
2026-10-12 10:28 ` Krzysztof Kozlowski
@ 2026-10-12 15:33 ` Anvesh Jain P
0 siblings, 0 replies; 12+ messages in thread
From: Anvesh Jain P @ 2026-10-12 15:33 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel, Sibi Sankar
On 10/12/2026 3:58 PM, Krzysztof Kozlowski wrote:
> On 12/10/2026 11:50, Anvesh Jain P wrote:
>>
>>
>> On 10/12/2026 2:26 PM, Krzysztof Kozlowski wrote:
>>> On Fri, Oct 09, 2026 at 12:47:42PM +0530, Anvesh Jain P wrote:
>>>> Add coredump support for the secure and non-secure OOBMSS carveouts.
>>>> Register fixed dump segments at probe time for attached-state recovery.
>>>>
>>>> Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
>>>> ---
>>>> drivers/remoteproc/qcom_q6v5_pas.c | 85 ++++++++++++++++++++++++++++++++++----
>>>> 1 file changed, 77 insertions(+), 8 deletions(-)
>>>
>>> Why is this separate from Glymur support? How is your device suppose to
>>> work without this patch?
>>>
>>> Best regards,
>>> Krzysztof
>>
>> This patch is diagnostic-only and is not required for OOBMSS boot or SSR
>> recovery; without it, the device works but no OOB coredump is collected.
>>
>> I kept it separate to isolate the optional coredump support. I will make
>> the subject and description generic for coredump support on PAS
>> subsystems with secondary processors, rather than limiting it to
>> Glymur/OOBMSS.
>>
>
> Commit msg probably should mention that "recovery" is here for
> debugging, not proper device operation. Otherwise single commit, if
> moderately small, is usually bringing entire support for a device.
>
> Best regards,
> Krzysztof
sure, I will update commit message accordingly.
--
Best Regards,
Anvesh
^ permalink raw reply [flat|nested] 12+ messages in thread