Re: [PATCH v2 3/3] clk: qcom: dprxcc: Add Nord DPRX clock controller support

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 9/23/26 9:21 PM, Taniya Das wrote:
> Add support for the DisplayPort Receiver (DPRX) clock controllers on
> Nord devices. There are two identical DPRX clock controller
> instances (DPRX0 and DPRX1), each providing clocks for the DPRX core,
> audio, AHB and video memory paths, along with core PLLs.
> 
> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> ---

[...]

> +	/*
> +	 * Configure cdiv 20 for core aud and 11 for core ahb clks of DPRX CC
> +	 */

Nit: this fits in a /* single-line comment */

> +	regmap_write(regmap, dprx_1_dprx_cc_core_aud_div_clk_src.reg, 0x13);
> +	regmap_write(regmap, dprx_1_dprx_cc_core_ahb_div_clk_src.reg, 0x0A);

Hex should be lowercase, but preferably please define some sort of a bitfield
that this value is written into and run regmap_update_bits()

You should also set `.use_rpm = true`

Konrad