From: "Suthikulpanit, Suravee" <suravee.suthikulpanit@amd.com>
To: Guixin Liu <kanie@linux.alibaba.com>,
linux-kernel@vger.kernel.org, iommu@lists.linux.dev,
joro@8bytes.org, jgg@nvidia.com
Cc: yi.l.liu@intel.com, kevin.tian@intel.com, nicolinc@nvidia.com,
vasant.hegde@amd.com, jon.grimm@amd.com, santosh.shukla@amd.com,
Sairaj.K@amd.com, jay.chen@amd.com, Ming.Shu@amd.com,
SooJin.Tan@amd.com, wvw@google.com, wnliu@google.com,
dantuluris@google.com, chriscli@google.com, kpsingh@google.com,
alejandro.j.jimenez@oracle.com, joao.m.martins@oracle.com,
guanghuifeng@linux.alibaba.com
Subject: Re: [PATCH v5 23/24] iommu/amd: Assign per-vIOMMU translate device ID
Date: Mon, 28 Sep 2026 17:24:28 +0700 [thread overview]
Message-ID: <7afc648b-6d4e-4b06-9601-995b6acc7577@amd.com> (raw)
In-Reply-To: <d4a0360a-fae1-484d-81ca-c926e4450265@linux.alibaba.com>
On 9/22/2026 2:09 PM, Guixin Liu wrote:
>> @@ -93,31 +98,63 @@ int amd_iommufd_viommu_init(struct iommufd_viommu *viommu, struct iommu_domain *
>>
>> data.out_vfmmio_mmap_offset = aviommu->vfmmio_mmap_offset;
>>
>> - /* Reset vIOMMU MMIOs to initialize the vIOMMU */
>> + /* Reset vIOMMU MMIOs before the trans_devid is visible in the pool. */
>> ret = amd_iommu_reset_vmmio(iommu, aviommu->gid);
>> if (ret)
>> - goto err_init;
>> + goto err_trans_devid;
>> +
>> + mutex_lock(&aviommu->trans_devid_lock);
>> + ret = amd_iommu_trans_devid_alloc(iommu->pci_seg, aviommu);
>> + if (ret < 0) {
>> + mutex_unlock(&aviommu->trans_devid_lock);
>> + goto err_trans_devid;
>> + }
>> + trans_devid_allocated = true;
>> + aviommu->trans_devid = ret;
>> +
>> + ret = amd_iommu_set_translate_dte(viommu);
>> + if (ret)
>> + goto err_init_unlock;
>> + trans_dte_set = true;
>> + amd_iommu_update_vfctrl_mmio_translate_devid(iommu, aviommu->gid,
>> + aviommu->trans_devid);
>> + mutex_unlock(&aviommu->trans_devid_lock);
>>
>> ret = amd_viommu_init_one(iommu, aviommu);
>> if (ret)
>> goto err_init;
>> + uninit_on_err = true;
>>
>> ret = iommu_copy_struct_to_user(user_data, &data,
>> IOMMU_VIOMMU_TYPE_AMD,
>> out_vfmmio_mmap_offset);
>> if (ret)
>> - goto err_init_one;
>> + goto err_init;
>>
>> viommu->ops = &amd_viommu_ops;
>>
>> - spin_lock_irqsave(&pdom->lock, flags);
>> - list_add(&aviommu->pdom_list, &pdom->viommu_list);
>> - spin_unlock_irqrestore(&pdom->lock, flags);
>> -
>> return 0;
>> -err_init_one:
>> - amd_viommu_uninit_one(iommu, aviommu);
>> err_init:
>> + mutex_lock(&aviommu->trans_devid_lock);
>> +err_init_unlock:
>> + if (trans_dte_set) {
>> + spin_lock_irqsave(&pdom->lock, flags);
>> + if (!list_empty(&aviommu->pdom_list))
>> + list_del_init(&aviommu->pdom_list);
>> + spin_unlock_irqrestore(&pdom->lock, flags);
>> + amd_iommu_update_vfctrl_mmio_translate_devid(iommu, aviommu->gid, 0);
>> + amd_iommu_clear_translate_dte(iommu, aviommu->trans_dev_data,
>> + aviommu->trans_devid);
>> + amd_iommu_free_dev_data(iommu, aviommu->trans_dev_data);
>> + aviommu->trans_dev_data = NULL;
>> + }
>> + if (trans_devid_allocated)
>> + amd_iommu_trans_devid_free(iommu->pci_seg, aviommu->trans_devid,
>> + aviommu);
>> + mutex_unlock(&aviommu->trans_devid_lock);
>> + if (uninit_on_err)
>> + amd_viommu_uninit_one(iommu, aviommu);
>> +err_trans_devid:
>> iommufd_viommu_destroy_mmap(&aviommu->core, aviommu->vfmmio_mmap_offset);
>> err_mmap:
>> amd_iommu_gid_free(iommu, aviommu->gid);
>> @@ -140,6 +177,17 @@ static void amd_iommufd_viommu_destroy(struct iommufd_viommu *viommu)
>> spin_unlock_irqrestore(&pdom->lock, flags);
>> xa_destroy(&aviommu->gdomid_array);
>> iommufd_viommu_destroy_mmap(&aviommu->core, aviommu->vfmmio_mmap_offset);
>> +
>> + mutex_lock(&aviommu->trans_devid_lock);
>> + amd_iommu_update_vfctrl_mmio_translate_devid(iommu, aviommu->gid, 0);
>> + amd_iommu_clear_translate_dte(iommu, aviommu->trans_dev_data,
>> + aviommu->trans_devid);
>> + amd_iommu_free_dev_data(iommu, aviommu->trans_dev_data);
>> + aviommu->trans_dev_data = NULL;
>> + amd_iommu_trans_devid_free(iommu->pci_seg, aviommu->trans_devid,
>> + aviommu);
>> + mutex_unlock(&aviommu->trans_devid_lock);
>> +
>> amd_viommu_uninit_one(iommu, aviommu);
>> amd_iommu_gid_free(iommu, aviommu->gid);
>> mutex_destroy(&aviommu->vfctrl_lock);
> Should destroy trans_devid_lock too.
Correct. I'll update in v6.
Thanks,
Suravee
next prev parent reply other threads:[~2026-09-28 10:24 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-14 18:47 [PATCH v5 00/24] iommu/amd: Introduce AMD Hardware-accelerated Virtualized IOMMU (vIOMMU) Support Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 01/24] iommu/amd: Introduce vIOMMU-specific events and event Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 02/24] iommu/amd: Introduce EVENT_TYPE_GUEST_EVENT_FAULT Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 03/24] iommu/amd: Detect and initialize AMD vIOMMU feature Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 04/24] iommu/amd: Introduce IOMMUFD vIOMMU support for AMD Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 05/24] iommu/amd: Allocate Guest IDs for IOMMUFD vIOMMU instances Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 06/24] iommu/amd: Map vIOMMU VF and VF Control MMIO BARs Suravee Suthikulpanit
2026-09-22 6:43 ` Guixin Liu
2026-09-28 1:26 ` Suthikulpanit, Suravee
2026-09-14 18:47 ` [PATCH v5 07/24] iommu/amd: Add support for AMD vIOMMU VF MMIO region Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 08/24] iommu/amd: Introduce Reset vMMIO Command Suravee Suthikulpanit
2026-09-19 15:11 ` guanghuifeng
2026-09-21 9:10 ` Suthikulpanit, Suravee
2026-09-14 18:47 ` [PATCH v5 09/24] iommu/amd: Introduce and map vIOMMU private IPA region Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 10/24] iommu/amd: Pass iommu to device_flush_dte() Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 11/24] iommu/amd: Pass iommu and devid to amd_iommu_make_clear_dte() Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 12/24] iommu/amd: Store per-segment iommu_dev_data in an xarray Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 13/24] iommu/amd: Program IOMMU DTE with the private IPA domain Suravee Suthikulpanit
2026-09-19 15:26 ` guanghuifeng
2026-09-22 6:57 ` Guixin Liu
2026-09-14 18:47 ` [PATCH v5 14/24] iommu/amd: Add per-VM private IPA alloc/map helpers Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 15/24] iommu/amd: Add helper functions to manage DevID / DomID mapping tables Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 16/24] iommu/amd: Add IOMMUFD vDevice and DevID mapping Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 17/24] iommu/amd: Program nested DTE and DomID map on attach Suravee Suthikulpanit
2026-09-22 7:11 ` Guixin Liu
2026-09-28 7:56 ` Suthikulpanit, Suravee
2026-09-14 18:47 ` [PATCH v5 18/24] iommu/amd: Init and clear vIOMMU DevID and DomID maps Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 19/24] iommu/amd: Add per-segment translate device ID pool Suravee Suthikulpanit
2026-09-24 12:44 ` fuwenxin
2026-09-28 9:32 ` Suthikulpanit, Suravee
2026-09-28 1:49 ` fuwenxin
2026-09-14 18:47 ` [PATCH v5 20/24] iommu/amd: Reserve translate-device-id for PCI requestor aliases Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 21/24] iommu/amd: Add translation DTE and VFctrl TransDevID helpers Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 22/24] iommu/amd: Add translate-device-id alloc/free with vIOMMU owner Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 23/24] iommu/amd: Assign per-vIOMMU translate device ID Suravee Suthikulpanit
2026-09-22 7:09 ` Guixin Liu
2026-09-28 10:24 ` Suthikulpanit, Suravee [this message]
2026-09-14 18:47 ` [PATCH v5 24/24] iommu/amd: Relocate vIOMMU translate-device-id on PCI reserve Suravee Suthikulpanit
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=7afc648b-6d4e-4b06-9601-995b6acc7577@amd.com \
--to=suravee.suthikulpanit@amd.com \
--cc=Ming.Shu@amd.com \
--cc=Sairaj.K@amd.com \
--cc=SooJin.Tan@amd.com \
--cc=alejandro.j.jimenez@oracle.com \
--cc=chriscli@google.com \
--cc=dantuluris@google.com \
--cc=guanghuifeng@linux.alibaba.com \
--cc=iommu@lists.linux.dev \
--cc=jay.chen@amd.com \
--cc=jgg@nvidia.com \
--cc=joao.m.martins@oracle.com \
--cc=jon.grimm@amd.com \
--cc=joro@8bytes.org \
--cc=kanie@linux.alibaba.com \
--cc=kevin.tian@intel.com \
--cc=kpsingh@google.com \
--cc=linux-kernel@vger.kernel.org \
--cc=nicolinc@nvidia.com \
--cc=santosh.shukla@amd.com \
--cc=vasant.hegde@amd.com \
--cc=wnliu@google.com \
--cc=wvw@google.com \
--cc=yi.l.liu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®