Re: [PATCH v2 3/4] iio: adc: ad7124: add external clock support

[David Lechner <dlechner@baylibre.com>]

On 8/26/25 3:10 AM, Andy Shevchenko wrote:
> On Tue, Aug 26, 2025 at 1:55 AM David Lechner <dlechner@baylibre.com> wrote:
>>
>> Add support for an external clock source to the AD7124 ADC driver.
>>
>> Previously, the driver only supported using the internal clock and had
>> bad devicetree bindings that used a fake clock to essentially select
>> the power mode. This is preserved for backwards compatibility.
>>
>> If the clock is not named "mclk", then we know that the devicetree is
>> using the correct bindings and we can configure the chip to use an
>> external clock source rather than internal.
>>
>> Also drop a redundant comment when configuring the register fields
>> instead of adding more.
> 
> ...
> 
>> +                       /*
>> +                        * The external clock may be 4x the nominal clock rate,
>> +                        * in which case the ADC needs to be configured to
>> +                        * divide it by 4. Using MEGA is a bit arbitrary, but
>> +                        * the expected clock rates are either 614.4 kHz or
>> +                        * 2.4576 MHz, so this should work.
>> +                        */
>> +                       if (clk_hz > MEGA)
> 
> This is (1 * HZ_PER_MHZ), but as the comment says, this arbitrary
> check may be improved by using the exact values.

The datasheet wasn't clear if an exact value was required or if
there was some tolerance, so this is why I didn't try comparing
to exact values.

> 
>> +                               clk_sel = AD7124_ADC_CONTROL_CLK_SEL_EXT_DIV4;
>> +                       else
>> +                               clk_sel = AD7124_ADC_CONTROL_CLK_SEL_EXT;
>