[PATCH v2 0/3] Enable QoS configuration on X1E80100

[PATCH v2 0/3] Enable QoS configuration on X1E80100

[Raviteja Laggyshetty]

This series enables QoS configuration for QNOC type device which
can be found on X1E80100 platform. It enables QoS configuration
for master ports with predefined priority and urgency forwarding.
This helps in prioritizing the traffic originating from different
interconnect masters at NOC (Network On Chip).

The system may function normally without this feature. However,
enabling QoS helps optimize latency and bandwidth across subsystems
like CPU, GPU, and multimedia engines, which becomes important in
high-throughput scenarios. This is a feature aimed at performance
enhancement to improve system performance under concurrent workloads.

Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
Changes in v2:
 - Update the dt-bindings to make the clock property optional, since the
   device can operate without QoS, preserving the backward compatibility.
   [Krzysztof]
 - Link to v1: https://patch.msgid.link/20260422-x1e80100_qos-v1-0-bcc2afe4cc78@oss.qualcomm.com

---
Raviteja Laggyshetty (3):
      dt-bindings: interconnect: qcom,x1e80100-rpmh: add clocks property to enable QoS
      interconnect: qcom: x1e80100: enable QoS configuration
      arm64: dts: qcom: x1e80100: Add clocks for QoS configuration

 .../bindings/interconnect/qcom,x1e80100-rpmh.yaml  |  72 +++
 arch/arm64/boot/dts/qcom/hamoa.dtsi                |   9 +
 drivers/interconnect/qcom/x1e80100.c               | 485 +++++++++++++++++++++
 3 files changed, 566 insertions(+)
---
base-commit: e7e28506af98ce4e1059e5ec59334b335c00a246
change-id: 20260414-x1e80100_qos-7d96c8b47bdf

Best regards,
--  
Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>

[PATCH v2 1/3] dt-bindings: interconnect: qcom,x1e80100-rpmh: add clocks property to enable QoS

[Raviteja Laggyshetty]

Some interconnect nodes on X1E80100 have QoS registers located inside
a block whose interface is clock-gated. For those nodes, driver
must enable the corresponding clock(s) before accessing the
registers. Add the 'clocks' property so the driver can obtain
and enable the required clock(s).

Only interconnects that have clock-gated QoS register interface
use this property; it is not applicable to all interconnect nodes.

Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
 .../bindings/interconnect/qcom,x1e80100-rpmh.yaml  | 72 ++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml
index 0840b0ec6e27..d863cddb21ac 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml
@@ -46,6 +46,10 @@ properties:
   reg:
     maxItems: 1
 
+  clocks:
+    minItems: 1
+    maxItems: 6
+
 required:
   - compatible
 
@@ -65,6 +69,73 @@ allOf:
       required:
         - reg
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,x1e80100-aggre1-noc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: aggre UFS PHY AXI clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,x1e80100-usb-north-anoc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: aggre USB2 PRIM AXI clock
+            - description: aggre USB3 MP AXI clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,x1e80100-usb-south-anoc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: aggre USB3 PRIM AXI clock
+            - description: aggre USB3 SEC AXI clock
+            - description: aggre USB3 TERT AXI clock
+            - description: aggre USB4_0 AXI clock
+            - description: aggre USB4_1 AXI clock
+            - description: aggre USB4_2 AXI clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,x1e80100-aggre2-noc
+              - qcom,x1e80100-clk-virt
+              - qcom,x1e80100-cnoc-cfg
+              - qcom,x1e80100-cnoc-main
+              - qcom,x1e80100-gem-noc
+              - qcom,x1e80100-lpass-ag-noc
+              - qcom,x1e80100-lpass-lpiaon-noc
+              - qcom,x1e80100-lpass-lpicx-noc
+              - qcom,x1e80100-mc-virt
+              - qcom,x1e80100-mmss-noc
+              - qcom,x1e80100-nsp-noc
+              - qcom,x1e80100-pcie-center-anoc
+              - qcom,x1e80100-pcie-north-anoc
+              - qcom,x1e80100-pcie-south-anoc
+              - qcom,x1e80100-system-noc
+              - qcom,x1e80100-usb-center-anoc
+    then:
+      properties:
+        clocks: false
+
 unevaluatedProperties: false
 
 examples:
@@ -80,4 +151,5 @@ examples:
       reg = <0x016e0000 0x14400>;
       #interconnect-cells = <2>;
       qcom,bcm-voters = <&apps_bcm_voter>;
+      clocks = <&gcc_aggre_ufs_phy_axi_clk>;
     };

-- 
2.43.0

Re: [PATCH v2 1/3] dt-bindings: interconnect: qcom,x1e80100-rpmh: add clocks property to enable QoS

[Krzysztof Kozlowski]

On Wed, May 27, 2026 at 05:37:09AM +0000, Raviteja Laggyshetty wrote:
> Some interconnect nodes on X1E80100 have QoS registers located inside
> a block whose interface is clock-gated. For those nodes, driver
> must enable the corresponding clock(s) before accessing the
> registers. Add the 'clocks' property so the driver can obtain
> and enable the required clock(s).
> 
> Only interconnects that have clock-gated QoS register interface
> use this property; it is not applicable to all interconnect nodes.
> 
> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> ---
>  .../bindings/interconnect/qcom,x1e80100-rpmh.yaml  | 72 ++++++++++++++++++++++
>  1 file changed, 72 insertions(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH v2 2/3] interconnect: qcom: x1e80100: enable QoS configuration

[Raviteja Laggyshetty]

Enable QoS configuration for master ports with predefined priority
and urgency forwarding.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
 drivers/interconnect/qcom/x1e80100.c | 485 +++++++++++++++++++++++++++++++++++
 1 file changed, 485 insertions(+)

diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qcom/x1e80100.c
index 2ba2823c7860..8075e0ff2059 100644
--- a/drivers/interconnect/qcom/x1e80100.c
+++ b/drivers/interconnect/qcom/x1e80100.c
@@ -173,6 +173,13 @@ static struct qcom_icc_node qhm_qspi = {
 	.name = "qhm_qspi",
 	.channels = 1,
 	.buswidth = 4,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xb000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -181,6 +188,13 @@ static struct qcom_icc_node qhm_qup1 = {
 	.name = "qhm_qup1",
 	.channels = 1,
 	.buswidth = 4,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xc000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -189,6 +203,13 @@ static struct qcom_icc_node xm_sdc4 = {
 	.name = "xm_sdc4",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xd000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -197,6 +218,13 @@ static struct qcom_icc_node xm_ufs_mem = {
 	.name = "xm_ufs_mem",
 	.channels = 1,
 	.buswidth = 16,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xe000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -205,6 +233,13 @@ static struct qcom_icc_node qhm_qup0 = {
 	.name = "qhm_qup0",
 	.channels = 1,
 	.buswidth = 4,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x16000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a2noc_snoc },
 };
@@ -213,6 +248,13 @@ static struct qcom_icc_node qhm_qup2 = {
 	.name = "qhm_qup2",
 	.channels = 1,
 	.buswidth = 4,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x11000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a2noc_snoc },
 };
@@ -221,6 +263,13 @@ static struct qcom_icc_node qxm_crypto = {
 	.name = "qxm_crypto",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x12000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a2noc_snoc },
 };
@@ -237,6 +286,13 @@ static struct qcom_icc_node xm_qdss_etr_0 = {
 	.name = "xm_qdss_etr_0",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x13000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a2noc_snoc },
 };
@@ -245,6 +301,13 @@ static struct qcom_icc_node xm_qdss_etr_1 = {
 	.name = "xm_qdss_etr_1",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x14000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a2noc_snoc },
 };
@@ -253,6 +316,13 @@ static struct qcom_icc_node xm_sdc2 = {
 	.name = "xm_sdc2",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x15000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a2noc_snoc },
 };
@@ -337,6 +407,13 @@ static struct qcom_icc_node alm_gpu_tcu = {
 	.name = "alm_gpu_tcu",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x271000 },
+		.prio = 1,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 2,
 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 };
@@ -345,6 +422,13 @@ static struct qcom_icc_node alm_pcie_tcu = {
 	.name = "alm_pcie_tcu",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x27d000 },
+		.prio = 3,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 2,
 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 };
@@ -353,6 +437,13 @@ static struct qcom_icc_node alm_sys_tcu = {
 	.name = "alm_sys_tcu",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x273000 },
+		.prio = 6,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 2,
 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 };
@@ -370,6 +461,13 @@ static struct qcom_icc_node qnm_gpu = {
 	.name = "qnm_gpu",
 	.channels = 4,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 4,
+		.port_offsets = { 0x51000, 0x58000, 0xd1000, 0xd8000 },
+		.prio = 0,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 2,
 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 };
@@ -378,6 +476,13 @@ static struct qcom_icc_node qnm_lpass = {
 	.name = "qnm_lpass",
 	.channels = 1,
 	.buswidth = 16,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x275000 },
+		.prio = 0,
+		.urg_fwd = 1,
+		.prio_fwd_disable = 0,
+	},
 	.num_links = 3,
 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 			&qns_pcie },
@@ -387,6 +492,13 @@ static struct qcom_icc_node qnm_mnoc_hf = {
 	.name = "qnm_mnoc_hf",
 	.channels = 2,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 2,
+		.port_offsets = { 0x53000, 0xd3000 },
+		.prio = 0,
+		.urg_fwd = 1,
+		.prio_fwd_disable = 0,
+	},
 	.num_links = 2,
 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 };
@@ -395,6 +507,13 @@ static struct qcom_icc_node qnm_mnoc_sf = {
 	.name = "qnm_mnoc_sf",
 	.channels = 2,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 2,
+		.port_offsets = { 0x55000, 0xd5000 },
+		.prio = 0,
+		.urg_fwd = 1,
+		.prio_fwd_disable = 0,
+	},
 	.num_links = 2,
 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 };
@@ -403,6 +522,13 @@ static struct qcom_icc_node qnm_nsp_noc = {
 	.name = "qnm_nsp_noc",
 	.channels = 2,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 2,
+		.port_offsets = { 0x57000, 0xd7000 },
+		.prio = 0,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 3,
 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 			&qns_pcie },
@@ -412,6 +538,13 @@ static struct qcom_icc_node qnm_pcie = {
 	.name = "qnm_pcie",
 	.channels = 1,
 	.buswidth = 64,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x277000 },
+		.prio = 0,
+		.urg_fwd = 1,
+		.prio_fwd_disable = 0,
+	},
 	.num_links = 2,
 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
 };
@@ -420,6 +553,13 @@ static struct qcom_icc_node qnm_snoc_sf = {
 	.name = "qnm_snoc_sf",
 	.channels = 1,
 	.buswidth = 64,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x27b000 },
+		.prio = 2,
+		.urg_fwd = 1,
+		.prio_fwd_disable = 0,
+	},
 	.num_links = 3,
 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
 			&qns_pcie },
@@ -429,6 +569,13 @@ static struct qcom_icc_node xm_gic = {
 	.name = "xm_gic",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x27f000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_llcc },
 };
@@ -469,6 +616,13 @@ static struct qcom_icc_node qnm_av1_enc = {
 	.name = "qnm_av1_enc",
 	.channels = 1,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x2f000 },
+		.prio = 4,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_mem_noc_sf },
 };
@@ -477,6 +631,13 @@ static struct qcom_icc_node qnm_camnoc_hf = {
 	.name = "qnm_camnoc_hf",
 	.channels = 2,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 2,
+		.port_offsets = { 0x28000, 0x29000 },
+		.prio = 0,
+		.urg_fwd = 1,
+		.prio_fwd_disable = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_mem_noc_hf },
 };
@@ -485,6 +646,13 @@ static struct qcom_icc_node qnm_camnoc_icp = {
 	.name = "qnm_camnoc_icp",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x2a000 },
+		.prio = 4,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_mem_noc_sf },
 };
@@ -493,6 +661,13 @@ static struct qcom_icc_node qnm_camnoc_sf = {
 	.name = "qnm_camnoc_sf",
 	.channels = 2,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 2,
+		.port_offsets = { 0x2b000, 0x2c000 },
+		.prio = 0,
+		.urg_fwd = 1,
+		.prio_fwd_disable = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_mem_noc_sf },
 };
@@ -501,6 +676,13 @@ static struct qcom_icc_node qnm_eva = {
 	.name = "qnm_eva",
 	.channels = 1,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x33000 },
+		.prio = 0,
+		.urg_fwd = 1,
+		.prio_fwd_disable = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_mem_noc_sf },
 };
@@ -509,6 +691,13 @@ static struct qcom_icc_node qnm_mdp = {
 	.name = "qnm_mdp",
 	.channels = 2,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 2,
+		.port_offsets = { 0x2d000, 0x2e000 },
+		.prio = 0,
+		.urg_fwd = 1,
+		.prio_fwd_disable = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_mem_noc_hf },
 };
@@ -517,6 +706,13 @@ static struct qcom_icc_node qnm_video = {
 	.name = "qnm_video",
 	.channels = 2,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 2,
+		.port_offsets = { 0x30000, 0x31000 },
+		.prio = 0,
+		.urg_fwd = 1,
+		.prio_fwd_disable = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_mem_noc_sf },
 };
@@ -525,6 +721,13 @@ static struct qcom_icc_node qnm_video_cv_cpu = {
 	.name = "qnm_video_cv_cpu",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x32000 },
+		.prio = 4,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_mem_noc_sf },
 };
@@ -533,6 +736,13 @@ static struct qcom_icc_node qnm_video_v_cpu = {
 	.name = "qnm_video_v_cpu",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x34000 },
+		.prio = 4,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_mem_noc_sf },
 };
@@ -573,6 +783,13 @@ static struct qcom_icc_node xm_pcie_3 = {
 	.name = "xm_pcie_3",
 	.channels = 1,
 	.buswidth = 64,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x7000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_pcie_north_gem_noc },
 };
@@ -581,6 +798,13 @@ static struct qcom_icc_node xm_pcie_4 = {
 	.name = "xm_pcie_4",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x8000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_pcie_north_gem_noc },
 };
@@ -589,6 +813,13 @@ static struct qcom_icc_node xm_pcie_5 = {
 	.name = "xm_pcie_5",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x9000 },
+		.prio = 3,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_pcie_north_gem_noc },
 };
@@ -597,6 +828,13 @@ static struct qcom_icc_node xm_pcie_0 = {
 	.name = "xm_pcie_0",
 	.channels = 1,
 	.buswidth = 16,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x9000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_pcie_south_gem_noc },
 };
@@ -605,6 +843,13 @@ static struct qcom_icc_node xm_pcie_1 = {
 	.name = "xm_pcie_1",
 	.channels = 1,
 	.buswidth = 16,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xa000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_pcie_south_gem_noc },
 };
@@ -613,6 +858,13 @@ static struct qcom_icc_node xm_pcie_2 = {
 	.name = "xm_pcie_2",
 	.channels = 1,
 	.buswidth = 16,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xb000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_pcie_south_gem_noc },
 };
@@ -621,6 +873,13 @@ static struct qcom_icc_node xm_pcie_6a = {
 	.name = "xm_pcie_6a",
 	.channels = 1,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xc000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_pcie_south_gem_noc },
 };
@@ -629,6 +888,13 @@ static struct qcom_icc_node xm_pcie_6b = {
 	.name = "xm_pcie_6b",
 	.channels = 1,
 	.buswidth = 16,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xd000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_pcie_south_gem_noc },
 };
@@ -653,6 +919,13 @@ static struct qcom_icc_node qnm_gic = {
 	.name = "qnm_gic",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x1c000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_gemnoc_sf },
 };
@@ -685,6 +958,13 @@ static struct qcom_icc_node xm_usb2_0 = {
 	.name = "xm_usb2_0",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x6000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_aggre_usb_north_snoc },
 };
@@ -693,6 +973,13 @@ static struct qcom_icc_node xm_usb3_mp = {
 	.name = "xm_usb3_mp",
 	.channels = 1,
 	.buswidth = 16,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x7000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_aggre_usb_north_snoc },
 };
@@ -701,6 +988,13 @@ static struct qcom_icc_node xm_usb3_0 = {
 	.name = "xm_usb3_0",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xa000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_aggre_usb_south_snoc },
 };
@@ -709,6 +1003,13 @@ static struct qcom_icc_node xm_usb3_1 = {
 	.name = "xm_usb3_1",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xb000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_aggre_usb_south_snoc },
 };
@@ -717,6 +1018,13 @@ static struct qcom_icc_node xm_usb3_2 = {
 	.name = "xm_usb3_2",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xc000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_aggre_usb_south_snoc },
 };
@@ -725,6 +1033,13 @@ static struct qcom_icc_node xm_usb4_0 = {
 	.name = "xm_usb4_0",
 	.channels = 1,
 	.buswidth = 16,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xd000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_aggre_usb_south_snoc },
 };
@@ -733,6 +1048,13 @@ static struct qcom_icc_node xm_usb4_1 = {
 	.name = "xm_usb4_1",
 	.channels = 1,
 	.buswidth = 16,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xe000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_aggre_usb_south_snoc },
 };
@@ -741,6 +1063,13 @@ static struct qcom_icc_node xm_usb4_2 = {
 	.name = "xm_usb4_2",
 	.channels = 1,
 	.buswidth = 16,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xf000 },
+		.prio = 2,
+		.urg_fwd = 0,
+		.prio_fwd_disable = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_aggre_usb_south_snoc },
 };
@@ -1466,11 +1795,21 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
 	[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
 };
 
+static const struct regmap_config x1e80100_aggre1_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x14400,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_aggre1_noc = {
+	.config = &x1e80100_aggre1_noc_regmap_config,
 	.nodes = aggre1_noc_nodes,
 	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
 	.bcms = aggre1_noc_bcms,
 	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
+	.qos_requires_clocks = true,
 };
 
 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
@@ -1488,7 +1827,16 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
 	[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
 };
 
+static const struct regmap_config x1e80100_aggre2_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x1c400,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_aggre2_noc = {
+	.config = &x1e80100_aggre2_noc_regmap_config,
 	.nodes = aggre2_noc_nodes,
 	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
 	.bcms = aggre2_noc_bcms,
@@ -1573,7 +1921,16 @@ static struct qcom_icc_node * const cnoc_cfg_nodes[] = {
 	[SLAVE_TCU] = &xs_sys_tcu_cfg,
 };
 
+static const struct regmap_config x1e80100_cnoc_cfg_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x6600,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_cnoc_cfg = {
+	.config = &x1e80100_cnoc_cfg_regmap_config,
 	.nodes = cnoc_cfg_nodes,
 	.num_nodes = ARRAY_SIZE(cnoc_cfg_nodes),
 	.bcms = cnoc_cfg_bcms,
@@ -1603,7 +1960,16 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = {
 	[SLAVE_PCIE_6B] = &xs_pcie_6b,
 };
 
+static const struct regmap_config x1e80100_cnoc_main_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x14400,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_cnoc_main = {
+	.config = &x1e80100_cnoc_main_regmap_config,
 	.nodes = cnoc_main_nodes,
 	.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
 	.bcms = cnoc_main_bcms,
@@ -1633,7 +1999,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
 	[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
 };
 
+static const struct regmap_config x1e80100_gem_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x311200,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_gem_noc = {
+	.config = &x1e80100_gem_noc_regmap_config,
 	.nodes = gem_noc_nodes,
 	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
 	.bcms = gem_noc_bcms,
@@ -1648,7 +2023,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
 	[SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
 };
 
+static const struct regmap_config x1e80100_lpass_ag_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0xe080,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_lpass_ag_noc = {
+	.config = &x1e80100_lpass_ag_noc_regmap_config,
 	.nodes = lpass_ag_noc_nodes,
 	.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
 	.bcms = lpass_ag_noc_bcms,
@@ -1664,7 +2048,16 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
 	[SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
 };
 
+static const struct regmap_config x1e80100_lpass_lpiaon_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x19080,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc = {
+	.config = &x1e80100_lpass_lpiaon_noc_regmap_config,
 	.nodes = lpass_lpiaon_noc_nodes,
 	.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
 	.bcms = lpass_lpiaon_noc_bcms,
@@ -1679,7 +2072,16 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
 	[SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
 };
 
+static const struct regmap_config x1e80100_lpass_lpicx_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x3a200,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = {
+	.config = &x1e80100_lpass_lpicx_noc_regmap_config,
 	.nodes = lpass_lpicx_noc_nodes,
 	.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
 	.bcms = lpass_lpicx_noc_bcms,
@@ -1724,7 +2126,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
 	[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
 };
 
+static const struct regmap_config x1e80100_mmss_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x5b800,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_mmss_noc = {
+	.config = &x1e80100_mmss_noc_regmap_config,
 	.nodes = mmss_noc_nodes,
 	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
 	.bcms = mmss_noc_bcms,
@@ -1740,7 +2151,16 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
 	[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
 };
 
+static const struct regmap_config x1e80100_nsp_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0xe080,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_nsp_noc = {
+	.config = &x1e80100_nsp_noc_regmap_config,
 	.nodes = nsp_noc_nodes,
 	.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
 	.bcms = nsp_noc_bcms,
@@ -1757,7 +2177,16 @@ static struct qcom_icc_node * const pcie_center_anoc_nodes[] = {
 	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
 };
 
+static const struct regmap_config x1e80100_pcie_center_anoc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x7000,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_pcie_center_anoc = {
+	.config = &x1e80100_pcie_center_anoc_regmap_config,
 	.nodes = pcie_center_anoc_nodes,
 	.num_nodes = ARRAY_SIZE(pcie_center_anoc_nodes),
 	.bcms = pcie_center_anoc_bcms,
@@ -1774,7 +2203,16 @@ static struct qcom_icc_node * const pcie_north_anoc_nodes[] = {
 	[SLAVE_PCIE_NORTH] = &qns_pcie_north_gem_noc,
 };
 
+static const struct regmap_config x1e80100_pcie_north_anoc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x9080,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_pcie_north_anoc = {
+	.config = &x1e80100_pcie_north_anoc_regmap_config,
 	.nodes = pcie_north_anoc_nodes,
 	.num_nodes = ARRAY_SIZE(pcie_north_anoc_nodes),
 	.bcms = pcie_north_anoc_bcms,
@@ -1793,7 +2231,16 @@ static struct qcom_icc_node * const pcie_south_anoc_nodes[] = {
 	[SLAVE_PCIE_SOUTH] = &qns_pcie_south_gem_noc,
 };
 
+static const struct regmap_config x1e80100_pcie_south_anoc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0xd080,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_pcie_south_anoc = {
+	.config = &x1e80100_pcie_south_anoc_regmap_config,
 	.nodes = pcie_south_anoc_nodes,
 	.num_nodes = ARRAY_SIZE(pcie_south_anoc_nodes),
 	.bcms = pcie_south_anoc_bcms,
@@ -1815,7 +2262,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
 	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
 };
 
+static const struct regmap_config x1e80100_system_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x1c080,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_system_noc = {
+	.config = &x1e80100_system_noc_regmap_config,
 	.nodes = system_noc_nodes,
 	.num_nodes = ARRAY_SIZE(system_noc_nodes),
 	.bcms = system_noc_bcms,
@@ -1831,7 +2287,16 @@ static struct qcom_icc_node * const usb_center_anoc_nodes[] = {
 	[SLAVE_USB_NOC_SNOC] = &qns_aggre_usb_snoc,
 };
 
+static const struct regmap_config x1e80100_usb_center_anoc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x8800,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_usb_center_anoc = {
+	.config = &x1e80100_usb_center_anoc_regmap_config,
 	.nodes = usb_center_anoc_nodes,
 	.num_nodes = ARRAY_SIZE(usb_center_anoc_nodes),
 	.bcms = usb_center_anoc_bcms,
@@ -1847,11 +2312,21 @@ static struct qcom_icc_node * const usb_north_anoc_nodes[] = {
 	[SLAVE_AGGRE_USB_NORTH] = &qns_aggre_usb_north_snoc,
 };
 
+static const struct regmap_config x1e80100_usb_north_anoc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x7080,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_usb_north_anoc = {
+	.config = &x1e80100_usb_north_anoc_regmap_config,
 	.nodes = usb_north_anoc_nodes,
 	.num_nodes = ARRAY_SIZE(usb_north_anoc_nodes),
 	.bcms = usb_north_anoc_bcms,
 	.num_bcms = ARRAY_SIZE(usb_north_anoc_bcms),
+	.qos_requires_clocks = true,
 };
 
 static struct qcom_icc_bcm * const usb_south_anoc_bcms[] = {
@@ -1867,11 +2342,21 @@ static struct qcom_icc_node * const usb_south_anoc_nodes[] = {
 	[SLAVE_AGGRE_USB_SOUTH] = &qns_aggre_usb_south_snoc,
 };
 
+static const struct regmap_config x1e80100_usb_south_anoc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0xf080,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc x1e80100_usb_south_anoc = {
+	.config = &x1e80100_usb_south_anoc_regmap_config,
 	.nodes = usb_south_anoc_nodes,
 	.num_nodes = ARRAY_SIZE(usb_south_anoc_nodes),
 	.bcms = usb_south_anoc_bcms,
 	.num_bcms = ARRAY_SIZE(usb_south_anoc_bcms),
+	.qos_requires_clocks = true,
 };
 
 static const struct of_device_id qnoc_of_match[] = {

-- 
2.43.0

Re: [PATCH v2 2/3] interconnect: qcom: x1e80100: enable QoS configuration

[Mostafa Saleh]

On Wed, May 27, 2026 at 05:37:10AM +0000, Raviteja Laggyshetty wrote:
> Enable QoS configuration for master ports with predefined priority
> and urgency forwarding.
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>

Testing with Linus's tree, this patch broke my Lenovo IdeaCenter Mini X
booting, the board resets very early during boot.
I see that the last patch (device tree) is missing from the tree, I
included it, but that doesn't fix it, disabling the driver also
doesn't help. I can boot again by reverting this patch.

I have my own device tree as my device is Purwa based [1]

[1] https://lore.kernel.org/all/20260429141815.827157-1-smostafa@google.com/

Thanks,
Mostafa

> ---
>  drivers/interconnect/qcom/x1e80100.c | 485 +++++++++++++++++++++++++++++++++++
>  1 file changed, 485 insertions(+)
> 
> diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qcom/x1e80100.c
> index 2ba2823c7860..8075e0ff2059 100644
> --- a/drivers/interconnect/qcom/x1e80100.c
> +++ b/drivers/interconnect/qcom/x1e80100.c
> @@ -173,6 +173,13 @@ static struct qcom_icc_node qhm_qspi = {
>  	.name = "qhm_qspi",
>  	.channels = 1,
>  	.buswidth = 4,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xb000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_a1noc_snoc },
>  };
> @@ -181,6 +188,13 @@ static struct qcom_icc_node qhm_qup1 = {
>  	.name = "qhm_qup1",
>  	.channels = 1,
>  	.buswidth = 4,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xc000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_a1noc_snoc },
>  };
> @@ -189,6 +203,13 @@ static struct qcom_icc_node xm_sdc4 = {
>  	.name = "xm_sdc4",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xd000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_a1noc_snoc },
>  };
> @@ -197,6 +218,13 @@ static struct qcom_icc_node xm_ufs_mem = {
>  	.name = "xm_ufs_mem",
>  	.channels = 1,
>  	.buswidth = 16,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xe000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_a1noc_snoc },
>  };
> @@ -205,6 +233,13 @@ static struct qcom_icc_node qhm_qup0 = {
>  	.name = "qhm_qup0",
>  	.channels = 1,
>  	.buswidth = 4,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x16000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_a2noc_snoc },
>  };
> @@ -213,6 +248,13 @@ static struct qcom_icc_node qhm_qup2 = {
>  	.name = "qhm_qup2",
>  	.channels = 1,
>  	.buswidth = 4,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x11000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_a2noc_snoc },
>  };
> @@ -221,6 +263,13 @@ static struct qcom_icc_node qxm_crypto = {
>  	.name = "qxm_crypto",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x12000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_a2noc_snoc },
>  };
> @@ -237,6 +286,13 @@ static struct qcom_icc_node xm_qdss_etr_0 = {
>  	.name = "xm_qdss_etr_0",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x13000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_a2noc_snoc },
>  };
> @@ -245,6 +301,13 @@ static struct qcom_icc_node xm_qdss_etr_1 = {
>  	.name = "xm_qdss_etr_1",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x14000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_a2noc_snoc },
>  };
> @@ -253,6 +316,13 @@ static struct qcom_icc_node xm_sdc2 = {
>  	.name = "xm_sdc2",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x15000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_a2noc_snoc },
>  };
> @@ -337,6 +407,13 @@ static struct qcom_icc_node alm_gpu_tcu = {
>  	.name = "alm_gpu_tcu",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x271000 },
> +		.prio = 1,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 2,
>  	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
>  };
> @@ -345,6 +422,13 @@ static struct qcom_icc_node alm_pcie_tcu = {
>  	.name = "alm_pcie_tcu",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x27d000 },
> +		.prio = 3,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 2,
>  	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
>  };
> @@ -353,6 +437,13 @@ static struct qcom_icc_node alm_sys_tcu = {
>  	.name = "alm_sys_tcu",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x273000 },
> +		.prio = 6,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 2,
>  	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
>  };
> @@ -370,6 +461,13 @@ static struct qcom_icc_node qnm_gpu = {
>  	.name = "qnm_gpu",
>  	.channels = 4,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 4,
> +		.port_offsets = { 0x51000, 0x58000, 0xd1000, 0xd8000 },
> +		.prio = 0,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 2,
>  	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
>  };
> @@ -378,6 +476,13 @@ static struct qcom_icc_node qnm_lpass = {
>  	.name = "qnm_lpass",
>  	.channels = 1,
>  	.buswidth = 16,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x275000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +		.prio_fwd_disable = 0,
> +	},
>  	.num_links = 3,
>  	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
>  			&qns_pcie },
> @@ -387,6 +492,13 @@ static struct qcom_icc_node qnm_mnoc_hf = {
>  	.name = "qnm_mnoc_hf",
>  	.channels = 2,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 2,
> +		.port_offsets = { 0x53000, 0xd3000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +		.prio_fwd_disable = 0,
> +	},
>  	.num_links = 2,
>  	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
>  };
> @@ -395,6 +507,13 @@ static struct qcom_icc_node qnm_mnoc_sf = {
>  	.name = "qnm_mnoc_sf",
>  	.channels = 2,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 2,
> +		.port_offsets = { 0x55000, 0xd5000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +		.prio_fwd_disable = 0,
> +	},
>  	.num_links = 2,
>  	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
>  };
> @@ -403,6 +522,13 @@ static struct qcom_icc_node qnm_nsp_noc = {
>  	.name = "qnm_nsp_noc",
>  	.channels = 2,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 2,
> +		.port_offsets = { 0x57000, 0xd7000 },
> +		.prio = 0,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 3,
>  	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
>  			&qns_pcie },
> @@ -412,6 +538,13 @@ static struct qcom_icc_node qnm_pcie = {
>  	.name = "qnm_pcie",
>  	.channels = 1,
>  	.buswidth = 64,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x277000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +		.prio_fwd_disable = 0,
> +	},
>  	.num_links = 2,
>  	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
>  };
> @@ -420,6 +553,13 @@ static struct qcom_icc_node qnm_snoc_sf = {
>  	.name = "qnm_snoc_sf",
>  	.channels = 1,
>  	.buswidth = 64,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x27b000 },
> +		.prio = 2,
> +		.urg_fwd = 1,
> +		.prio_fwd_disable = 0,
> +	},
>  	.num_links = 3,
>  	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
>  			&qns_pcie },
> @@ -429,6 +569,13 @@ static struct qcom_icc_node xm_gic = {
>  	.name = "xm_gic",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x27f000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_llcc },
>  };
> @@ -469,6 +616,13 @@ static struct qcom_icc_node qnm_av1_enc = {
>  	.name = "qnm_av1_enc",
>  	.channels = 1,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x2f000 },
> +		.prio = 4,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_mem_noc_sf },
>  };
> @@ -477,6 +631,13 @@ static struct qcom_icc_node qnm_camnoc_hf = {
>  	.name = "qnm_camnoc_hf",
>  	.channels = 2,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 2,
> +		.port_offsets = { 0x28000, 0x29000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +		.prio_fwd_disable = 0,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_mem_noc_hf },
>  };
> @@ -485,6 +646,13 @@ static struct qcom_icc_node qnm_camnoc_icp = {
>  	.name = "qnm_camnoc_icp",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x2a000 },
> +		.prio = 4,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_mem_noc_sf },
>  };
> @@ -493,6 +661,13 @@ static struct qcom_icc_node qnm_camnoc_sf = {
>  	.name = "qnm_camnoc_sf",
>  	.channels = 2,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 2,
> +		.port_offsets = { 0x2b000, 0x2c000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +		.prio_fwd_disable = 0,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_mem_noc_sf },
>  };
> @@ -501,6 +676,13 @@ static struct qcom_icc_node qnm_eva = {
>  	.name = "qnm_eva",
>  	.channels = 1,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x33000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +		.prio_fwd_disable = 0,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_mem_noc_sf },
>  };
> @@ -509,6 +691,13 @@ static struct qcom_icc_node qnm_mdp = {
>  	.name = "qnm_mdp",
>  	.channels = 2,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 2,
> +		.port_offsets = { 0x2d000, 0x2e000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +		.prio_fwd_disable = 0,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_mem_noc_hf },
>  };
> @@ -517,6 +706,13 @@ static struct qcom_icc_node qnm_video = {
>  	.name = "qnm_video",
>  	.channels = 2,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 2,
> +		.port_offsets = { 0x30000, 0x31000 },
> +		.prio = 0,
> +		.urg_fwd = 1,
> +		.prio_fwd_disable = 0,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_mem_noc_sf },
>  };
> @@ -525,6 +721,13 @@ static struct qcom_icc_node qnm_video_cv_cpu = {
>  	.name = "qnm_video_cv_cpu",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x32000 },
> +		.prio = 4,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_mem_noc_sf },
>  };
> @@ -533,6 +736,13 @@ static struct qcom_icc_node qnm_video_v_cpu = {
>  	.name = "qnm_video_v_cpu",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x34000 },
> +		.prio = 4,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_mem_noc_sf },
>  };
> @@ -573,6 +783,13 @@ static struct qcom_icc_node xm_pcie_3 = {
>  	.name = "xm_pcie_3",
>  	.channels = 1,
>  	.buswidth = 64,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x7000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_pcie_north_gem_noc },
>  };
> @@ -581,6 +798,13 @@ static struct qcom_icc_node xm_pcie_4 = {
>  	.name = "xm_pcie_4",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x8000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_pcie_north_gem_noc },
>  };
> @@ -589,6 +813,13 @@ static struct qcom_icc_node xm_pcie_5 = {
>  	.name = "xm_pcie_5",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x9000 },
> +		.prio = 3,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_pcie_north_gem_noc },
>  };
> @@ -597,6 +828,13 @@ static struct qcom_icc_node xm_pcie_0 = {
>  	.name = "xm_pcie_0",
>  	.channels = 1,
>  	.buswidth = 16,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x9000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_pcie_south_gem_noc },
>  };
> @@ -605,6 +843,13 @@ static struct qcom_icc_node xm_pcie_1 = {
>  	.name = "xm_pcie_1",
>  	.channels = 1,
>  	.buswidth = 16,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xa000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_pcie_south_gem_noc },
>  };
> @@ -613,6 +858,13 @@ static struct qcom_icc_node xm_pcie_2 = {
>  	.name = "xm_pcie_2",
>  	.channels = 1,
>  	.buswidth = 16,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xb000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_pcie_south_gem_noc },
>  };
> @@ -621,6 +873,13 @@ static struct qcom_icc_node xm_pcie_6a = {
>  	.name = "xm_pcie_6a",
>  	.channels = 1,
>  	.buswidth = 32,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xc000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_pcie_south_gem_noc },
>  };
> @@ -629,6 +888,13 @@ static struct qcom_icc_node xm_pcie_6b = {
>  	.name = "xm_pcie_6b",
>  	.channels = 1,
>  	.buswidth = 16,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xd000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_pcie_south_gem_noc },
>  };
> @@ -653,6 +919,13 @@ static struct qcom_icc_node qnm_gic = {
>  	.name = "qnm_gic",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x1c000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_gemnoc_sf },
>  };
> @@ -685,6 +958,13 @@ static struct qcom_icc_node xm_usb2_0 = {
>  	.name = "xm_usb2_0",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x6000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_aggre_usb_north_snoc },
>  };
> @@ -693,6 +973,13 @@ static struct qcom_icc_node xm_usb3_mp = {
>  	.name = "xm_usb3_mp",
>  	.channels = 1,
>  	.buswidth = 16,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0x7000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_aggre_usb_north_snoc },
>  };
> @@ -701,6 +988,13 @@ static struct qcom_icc_node xm_usb3_0 = {
>  	.name = "xm_usb3_0",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xa000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_aggre_usb_south_snoc },
>  };
> @@ -709,6 +1003,13 @@ static struct qcom_icc_node xm_usb3_1 = {
>  	.name = "xm_usb3_1",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xb000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_aggre_usb_south_snoc },
>  };
> @@ -717,6 +1018,13 @@ static struct qcom_icc_node xm_usb3_2 = {
>  	.name = "xm_usb3_2",
>  	.channels = 1,
>  	.buswidth = 8,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xc000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_aggre_usb_south_snoc },
>  };
> @@ -725,6 +1033,13 @@ static struct qcom_icc_node xm_usb4_0 = {
>  	.name = "xm_usb4_0",
>  	.channels = 1,
>  	.buswidth = 16,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xd000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_aggre_usb_south_snoc },
>  };
> @@ -733,6 +1048,13 @@ static struct qcom_icc_node xm_usb4_1 = {
>  	.name = "xm_usb4_1",
>  	.channels = 1,
>  	.buswidth = 16,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xe000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_aggre_usb_south_snoc },
>  };
> @@ -741,6 +1063,13 @@ static struct qcom_icc_node xm_usb4_2 = {
>  	.name = "xm_usb4_2",
>  	.channels = 1,
>  	.buswidth = 16,
> +	.qosbox = &(const struct qcom_icc_qosbox) {
> +		.num_ports = 1,
> +		.port_offsets = { 0xf000 },
> +		.prio = 2,
> +		.urg_fwd = 0,
> +		.prio_fwd_disable = 1,
> +	},
>  	.num_links = 1,
>  	.link_nodes = { &qns_aggre_usb_south_snoc },
>  };
> @@ -1466,11 +1795,21 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
>  	[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
>  };
>  
> +static const struct regmap_config x1e80100_aggre1_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x14400,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_aggre1_noc = {
> +	.config = &x1e80100_aggre1_noc_regmap_config,
>  	.nodes = aggre1_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
>  	.bcms = aggre1_noc_bcms,
>  	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
> +	.qos_requires_clocks = true,
>  };
>  
>  static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
> @@ -1488,7 +1827,16 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
>  	[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
>  };
>  
> +static const struct regmap_config x1e80100_aggre2_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x1c400,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_aggre2_noc = {
> +	.config = &x1e80100_aggre2_noc_regmap_config,
>  	.nodes = aggre2_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
>  	.bcms = aggre2_noc_bcms,
> @@ -1573,7 +1921,16 @@ static struct qcom_icc_node * const cnoc_cfg_nodes[] = {
>  	[SLAVE_TCU] = &xs_sys_tcu_cfg,
>  };
>  
> +static const struct regmap_config x1e80100_cnoc_cfg_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x6600,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_cnoc_cfg = {
> +	.config = &x1e80100_cnoc_cfg_regmap_config,
>  	.nodes = cnoc_cfg_nodes,
>  	.num_nodes = ARRAY_SIZE(cnoc_cfg_nodes),
>  	.bcms = cnoc_cfg_bcms,
> @@ -1603,7 +1960,16 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = {
>  	[SLAVE_PCIE_6B] = &xs_pcie_6b,
>  };
>  
> +static const struct regmap_config x1e80100_cnoc_main_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x14400,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_cnoc_main = {
> +	.config = &x1e80100_cnoc_main_regmap_config,
>  	.nodes = cnoc_main_nodes,
>  	.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
>  	.bcms = cnoc_main_bcms,
> @@ -1633,7 +1999,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
>  	[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
>  };
>  
> +static const struct regmap_config x1e80100_gem_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x311200,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_gem_noc = {
> +	.config = &x1e80100_gem_noc_regmap_config,
>  	.nodes = gem_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
>  	.bcms = gem_noc_bcms,
> @@ -1648,7 +2023,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
>  	[SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
>  };
>  
> +static const struct regmap_config x1e80100_lpass_ag_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0xe080,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_lpass_ag_noc = {
> +	.config = &x1e80100_lpass_ag_noc_regmap_config,
>  	.nodes = lpass_ag_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
>  	.bcms = lpass_ag_noc_bcms,
> @@ -1664,7 +2048,16 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
>  	[SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
>  };
>  
> +static const struct regmap_config x1e80100_lpass_lpiaon_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x19080,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc = {
> +	.config = &x1e80100_lpass_lpiaon_noc_regmap_config,
>  	.nodes = lpass_lpiaon_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
>  	.bcms = lpass_lpiaon_noc_bcms,
> @@ -1679,7 +2072,16 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
>  	[SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
>  };
>  
> +static const struct regmap_config x1e80100_lpass_lpicx_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x3a200,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = {
> +	.config = &x1e80100_lpass_lpicx_noc_regmap_config,
>  	.nodes = lpass_lpicx_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
>  	.bcms = lpass_lpicx_noc_bcms,
> @@ -1724,7 +2126,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
>  	[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
>  };
>  
> +static const struct regmap_config x1e80100_mmss_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x5b800,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_mmss_noc = {
> +	.config = &x1e80100_mmss_noc_regmap_config,
>  	.nodes = mmss_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
>  	.bcms = mmss_noc_bcms,
> @@ -1740,7 +2151,16 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
>  	[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
>  };
>  
> +static const struct regmap_config x1e80100_nsp_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0xe080,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_nsp_noc = {
> +	.config = &x1e80100_nsp_noc_regmap_config,
>  	.nodes = nsp_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
>  	.bcms = nsp_noc_bcms,
> @@ -1757,7 +2177,16 @@ static struct qcom_icc_node * const pcie_center_anoc_nodes[] = {
>  	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
>  };
>  
> +static const struct regmap_config x1e80100_pcie_center_anoc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x7000,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_pcie_center_anoc = {
> +	.config = &x1e80100_pcie_center_anoc_regmap_config,
>  	.nodes = pcie_center_anoc_nodes,
>  	.num_nodes = ARRAY_SIZE(pcie_center_anoc_nodes),
>  	.bcms = pcie_center_anoc_bcms,
> @@ -1774,7 +2203,16 @@ static struct qcom_icc_node * const pcie_north_anoc_nodes[] = {
>  	[SLAVE_PCIE_NORTH] = &qns_pcie_north_gem_noc,
>  };
>  
> +static const struct regmap_config x1e80100_pcie_north_anoc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x9080,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_pcie_north_anoc = {
> +	.config = &x1e80100_pcie_north_anoc_regmap_config,
>  	.nodes = pcie_north_anoc_nodes,
>  	.num_nodes = ARRAY_SIZE(pcie_north_anoc_nodes),
>  	.bcms = pcie_north_anoc_bcms,
> @@ -1793,7 +2231,16 @@ static struct qcom_icc_node * const pcie_south_anoc_nodes[] = {
>  	[SLAVE_PCIE_SOUTH] = &qns_pcie_south_gem_noc,
>  };
>  
> +static const struct regmap_config x1e80100_pcie_south_anoc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0xd080,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_pcie_south_anoc = {
> +	.config = &x1e80100_pcie_south_anoc_regmap_config,
>  	.nodes = pcie_south_anoc_nodes,
>  	.num_nodes = ARRAY_SIZE(pcie_south_anoc_nodes),
>  	.bcms = pcie_south_anoc_bcms,
> @@ -1815,7 +2262,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
>  	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
>  };
>  
> +static const struct regmap_config x1e80100_system_noc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x1c080,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_system_noc = {
> +	.config = &x1e80100_system_noc_regmap_config,
>  	.nodes = system_noc_nodes,
>  	.num_nodes = ARRAY_SIZE(system_noc_nodes),
>  	.bcms = system_noc_bcms,
> @@ -1831,7 +2287,16 @@ static struct qcom_icc_node * const usb_center_anoc_nodes[] = {
>  	[SLAVE_USB_NOC_SNOC] = &qns_aggre_usb_snoc,
>  };
>  
> +static const struct regmap_config x1e80100_usb_center_anoc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x8800,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_usb_center_anoc = {
> +	.config = &x1e80100_usb_center_anoc_regmap_config,
>  	.nodes = usb_center_anoc_nodes,
>  	.num_nodes = ARRAY_SIZE(usb_center_anoc_nodes),
>  	.bcms = usb_center_anoc_bcms,
> @@ -1847,11 +2312,21 @@ static struct qcom_icc_node * const usb_north_anoc_nodes[] = {
>  	[SLAVE_AGGRE_USB_NORTH] = &qns_aggre_usb_north_snoc,
>  };
>  
> +static const struct regmap_config x1e80100_usb_north_anoc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x7080,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_usb_north_anoc = {
> +	.config = &x1e80100_usb_north_anoc_regmap_config,
>  	.nodes = usb_north_anoc_nodes,
>  	.num_nodes = ARRAY_SIZE(usb_north_anoc_nodes),
>  	.bcms = usb_north_anoc_bcms,
>  	.num_bcms = ARRAY_SIZE(usb_north_anoc_bcms),
> +	.qos_requires_clocks = true,
>  };
>  
>  static struct qcom_icc_bcm * const usb_south_anoc_bcms[] = {
> @@ -1867,11 +2342,21 @@ static struct qcom_icc_node * const usb_south_anoc_nodes[] = {
>  	[SLAVE_AGGRE_USB_SOUTH] = &qns_aggre_usb_south_snoc,
>  };
>  
> +static const struct regmap_config x1e80100_usb_south_anoc_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0xf080,
> +	.fast_io = true,
> +};
> +
>  static const struct qcom_icc_desc x1e80100_usb_south_anoc = {
> +	.config = &x1e80100_usb_south_anoc_regmap_config,
>  	.nodes = usb_south_anoc_nodes,
>  	.num_nodes = ARRAY_SIZE(usb_south_anoc_nodes),
>  	.bcms = usb_south_anoc_bcms,
>  	.num_bcms = ARRAY_SIZE(usb_south_anoc_bcms),
> +	.qos_requires_clocks = true,
>  };
>  
>  static const struct of_device_id qnoc_of_match[] = {
> 
> -- 
> 2.43.0
> 

Re: [PATCH v2 2/3] interconnect: qcom: x1e80100: enable QoS configuration

[Marc Zyngier]

On Wed, 02 Sep 2026 14:00:52 +0100,
Mostafa Saleh <smostafa@google.com> wrote:
> 
> On Wed, May 27, 2026 at 05:37:10AM +0000, Raviteja Laggyshetty wrote:
> > Enable QoS configuration for master ports with predefined priority
> > and urgency forwarding.
> > 
> > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> 
> Testing with Linus's tree, this patch broke my Lenovo IdeaCenter Mini X
> booting, the board resets very early during boot.
> I see that the last patch (device tree) is missing from the tree, I
> included it, but that doesn't fix it, disabling the driver also
> doesn't help. I can boot again by reverting this patch.
> 
> I have my own device tree as my device is Purwa based [1]
> 
> [1] https://lore.kernel.org/all/20260429141815.827157-1-smostafa@google.com/

Same here. My Mini-X hard reboots after 2.45s in the kernel. Example
from the serial console:

<quote>
[    2.280289] VFIO - User Level meta-driver version: 0.3
[    2.286872] usbcore: registered new interface driver usb-storage
[    2.307218] i2c_dev: i2c /dev entries driver
[    2.316386] efifb: probing for efifb
[    2.320065] efifb: framebuffer at 0xe4800000, using 8100k, total 8100k
[    2.326768] efifb: mode is 1920x1080x32, linelength=7680, pages=1
[    2.333026] efifb: scrolling: redraw
[    2.336704] efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0
[    2.346518] Console: switching to colour frame buffer device 240x67
[    2.356787] fb0: EFI VGA frame buffer device
[    2.361793] clocksource: arch_mmio_counter: mask: 0xffffffffffffff max_cycles: 0x46d987e47, max_idle_ns: 440795202767 ns
[    2.372947] arch-timer-mmio 17800000.timer: mmio timer running at 19.20MHz (virt)
[    2.380860] usbcore: registered new interface driver usbhid
[    2.386577] usbhid: USB HID core driver
[    2.391899] hw perfevents: enabled with armv8_pmuv3 PMU driver, 13 (0,80000fff) counters available
[    2.403182] NET: Registered PF_INET6 protocol family
[    2.408516] Segment Routing with IPv6
[    2.412289] In-situ OAM (IOAM) with IPv6
[    2.416326] NET: Registered PF_PACKET protocol family
[    2.421533] 9pnet: Installing 9P2000 support
[    2.425923] Key type dns_resolver registered
[    2.430357] NET: Registered PF_VSOCK protocol family
[    2.440369] registered taskstats version 1
[    2.444633] Loading compiled-in X.509 certificates
[    2.451480] Demotion targets for Node 0: null
Format: Log Type - Time(microsec) - Message - Optional Info
Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
S - QC_IMAGE_VERSION_STRING=BOOT.MXF.2.4-00541-HAMOA-1
S - IMAGE_VARIANT_STRING=SocHamoaWP
S - OEM_IMAGE_VERSION_STRING=ip-10-195-202-30
S - Boot Interface: SPI
S - Secure Boot: On
S - Boot Config @ 0x221c8600 = 0x00000001
S - JTAG ID @ 0x221c8744 = 0x002ad0e1
S - OEM ID @ 0x221c8700 = 0x00000040
S - Serial Number @ 0x221c8610 = 0x00000460d5171bbb
S - Feature Config Row 0 @ 0x221c21e0 = 0x0000000000000000
S - Feature Config Row 1 @ 0x221c21e8 = 0x0000000000000000
S - Core 0 Frequency, 1363 MHz
S - PBL Patch Ver: 0
S - PBL freq: 600 MHZ
S - Cluster: 0, Core: 0
</quote>

I'm also seeing spurious resets on my "X1E001DE Snapdragon Devkit for
Windows" when doing large file transfers over the network (30GB+).
With this patch reverted on top of 7.3-rc1, both machines are as solid
as they were before it.

It appears that the Surface Pro 12" is equally affected (IRC reports),
so something is amiss with this particular patch.

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v2 2/3] interconnect: qcom: x1e80100: enable QoS configuration

[Raviteja Laggyshetty]

On 9/7/2026 1:39 PM, Marc Zyngier wrote:
> On Wed, 02 Sep 2026 14:00:52 +0100,
> Mostafa Saleh <smostafa@google.com> wrote:
>>
>> On Wed, May 27, 2026 at 05:37:10AM +0000, Raviteja Laggyshetty wrote:
>>> Enable QoS configuration for master ports with predefined priority
>>> and urgency forwarding.
>>>
>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>>> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
>>
>> Testing with Linus's tree, this patch broke my Lenovo IdeaCenter Mini X
>> booting, the board resets very early during boot.
>> I see that the last patch (device tree) is missing from the tree, I
>> included it, but that doesn't fix it, disabling the driver also
>> doesn't help. I can boot again by reverting this patch.
>>
>> I have my own device tree as my device is Purwa based [1]
>>
>> [1] https://lore.kernel.org/all/20260429141815.827157-1-smostafa@google.com/
> 
> Same here. My Mini-X hard reboots after 2.45s in the kernel. Example
> from the serial console:

Is the Mini-X based on Purwa ? 

> 
> <quote>
> [    2.280289] VFIO - User Level meta-driver version: 0.3
> [    2.286872] usbcore: registered new interface driver usb-storage
> [    2.307218] i2c_dev: i2c /dev entries driver
> [    2.316386] efifb: probing for efifb
> [    2.320065] efifb: framebuffer at 0xe4800000, using 8100k, total 8100k
> [    2.326768] efifb: mode is 1920x1080x32, linelength=7680, pages=1
> [    2.333026] efifb: scrolling: redraw
> [    2.336704] efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0
> [    2.346518] Console: switching to colour frame buffer device 240x67
> [    2.356787] fb0: EFI VGA frame buffer device
> [    2.361793] clocksource: arch_mmio_counter: mask: 0xffffffffffffff max_cycles: 0x46d987e47, max_idle_ns: 440795202767 ns
> [    2.372947] arch-timer-mmio 17800000.timer: mmio timer running at 19.20MHz (virt)
> [    2.380860] usbcore: registered new interface driver usbhid
> [    2.386577] usbhid: USB HID core driver
> [    2.391899] hw perfevents: enabled with armv8_pmuv3 PMU driver, 13 (0,80000fff) counters available
> [    2.403182] NET: Registered PF_INET6 protocol family
> [    2.408516] Segment Routing with IPv6
> [    2.412289] In-situ OAM (IOAM) with IPv6
> [    2.416326] NET: Registered PF_PACKET protocol family
> [    2.421533] 9pnet: Installing 9P2000 support
> [    2.425923] Key type dns_resolver registered
> [    2.430357] NET: Registered PF_VSOCK protocol family
> [    2.440369] registered taskstats version 1
> [    2.444633] Loading compiled-in X.509 certificates
> [    2.451480] Demotion targets for Node 0: null
> Format: Log Type - Time(microsec) - Message - Optional Info
> Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
> S - QC_IMAGE_VERSION_STRING=BOOT.MXF.2.4-00541-HAMOA-1
> S - IMAGE_VARIANT_STRING=SocHamoaWP
> S - OEM_IMAGE_VERSION_STRING=ip-10-195-202-30
> S - Boot Interface: SPI
> S - Secure Boot: On
> S - Boot Config @ 0x221c8600 = 0x00000001
> S - JTAG ID @ 0x221c8744 = 0x002ad0e1
> S - OEM ID @ 0x221c8700 = 0x00000040
> S - Serial Number @ 0x221c8610 = 0x00000460d5171bbb
> S - Feature Config Row 0 @ 0x221c21e0 = 0x0000000000000000
> S - Feature Config Row 1 @ 0x221c21e8 = 0x0000000000000000
> S - Core 0 Frequency, 1363 MHz
> S - PBL Patch Ver: 0
> S - PBL freq: 600 MHZ
> S - Cluster: 0, Core: 0
> </quote>
> 
> I'm also seeing spurious resets on my "X1E001DE Snapdragon Devkit for
> Windows" when doing large file transfers over the network (30GB+).
> With this patch reverted on top of 7.3-rc1, both machines are as solid
> as they were before it.
>
The current patch enable QoS for Hamoa SoC, which get programmed only during
driver probe. This shouldn't impact or cause any spurious resets once the 
device is booted up and probe is successful.
 

> It appears that the Surface Pro 12" is equally affected (IRC reports),
> so something is amiss with this particular patch.
> 
> 	M.
> 

Re: [PATCH v2 2/3] interconnect: qcom: x1e80100: enable QoS configuration

[Marc Zyngier]

On Mon, 07 Sep 2026 09:18:38 +0100,
Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> wrote:
> 
> 
> 
> On 9/7/2026 1:39 PM, Marc Zyngier wrote:
> > On Wed, 02 Sep 2026 14:00:52 +0100,
> > Mostafa Saleh <smostafa@google.com> wrote:
> >>
> >> On Wed, May 27, 2026 at 05:37:10AM +0000, Raviteja Laggyshetty wrote:
> >>> Enable QoS configuration for master ports with predefined priority
> >>> and urgency forwarding.
> >>>
> >>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> >>> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> >>
> >> Testing with Linus's tree, this patch broke my Lenovo IdeaCenter Mini X
> >> booting, the board resets very early during boot.
> >> I see that the last patch (device tree) is missing from the tree, I
> >> included it, but that doesn't fix it, disabling the driver also
> >> doesn't help. I can boot again by reverting this patch.
> >>
> >> I have my own device tree as my device is Purwa based [1]
> >>
> >> [1] https://lore.kernel.org/all/20260429141815.827157-1-smostafa@google.com/
> > 
> > Same here. My Mini-X hard reboots after 2.45s in the kernel. Example
> > from the serial console:
> 
> Is the Mini-X based on Purwa ?

Yes. At least the one I have in the rack.

> 
> > 
> > <quote>
> > [    2.280289] VFIO - User Level meta-driver version: 0.3
> > [    2.286872] usbcore: registered new interface driver usb-storage
> > [    2.307218] i2c_dev: i2c /dev entries driver
> > [    2.316386] efifb: probing for efifb
> > [    2.320065] efifb: framebuffer at 0xe4800000, using 8100k, total 8100k
> > [    2.326768] efifb: mode is 1920x1080x32, linelength=7680, pages=1
> > [    2.333026] efifb: scrolling: redraw
> > [    2.336704] efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0
> > [    2.346518] Console: switching to colour frame buffer device 240x67
> > [    2.356787] fb0: EFI VGA frame buffer device
> > [    2.361793] clocksource: arch_mmio_counter: mask: 0xffffffffffffff max_cycles: 0x46d987e47, max_idle_ns: 440795202767 ns
> > [    2.372947] arch-timer-mmio 17800000.timer: mmio timer running at 19.20MHz (virt)
> > [    2.380860] usbcore: registered new interface driver usbhid
> > [    2.386577] usbhid: USB HID core driver
> > [    2.391899] hw perfevents: enabled with armv8_pmuv3 PMU driver, 13 (0,80000fff) counters available
> > [    2.403182] NET: Registered PF_INET6 protocol family
> > [    2.408516] Segment Routing with IPv6
> > [    2.412289] In-situ OAM (IOAM) with IPv6
> > [    2.416326] NET: Registered PF_PACKET protocol family
> > [    2.421533] 9pnet: Installing 9P2000 support
> > [    2.425923] Key type dns_resolver registered
> > [    2.430357] NET: Registered PF_VSOCK protocol family
> > [    2.440369] registered taskstats version 1
> > [    2.444633] Loading compiled-in X.509 certificates
> > [    2.451480] Demotion targets for Node 0: null
> > Format: Log Type - Time(microsec) - Message - Optional Info
> > Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
> > S - QC_IMAGE_VERSION_STRING=BOOT.MXF.2.4-00541-HAMOA-1
> > S - IMAGE_VARIANT_STRING=SocHamoaWP
> > S - OEM_IMAGE_VERSION_STRING=ip-10-195-202-30
> > S - Boot Interface: SPI
> > S - Secure Boot: On
> > S - Boot Config @ 0x221c8600 = 0x00000001
> > S - JTAG ID @ 0x221c8744 = 0x002ad0e1
> > S - OEM ID @ 0x221c8700 = 0x00000040
> > S - Serial Number @ 0x221c8610 = 0x00000460d5171bbb
> > S - Feature Config Row 0 @ 0x221c21e0 = 0x0000000000000000
> > S - Feature Config Row 1 @ 0x221c21e8 = 0x0000000000000000
> > S - Core 0 Frequency, 1363 MHz
> > S - PBL Patch Ver: 0
> > S - PBL freq: 600 MHZ
> > S - Cluster: 0, Core: 0
> > </quote>
> > 
> > I'm also seeing spurious resets on my "X1E001DE Snapdragon Devkit for
> > Windows" when doing large file transfers over the network (30GB+).
> > With this patch reverted on top of 7.3-rc1, both machines are as solid
> > as they were before it.
> >
> The current patch enable QoS for Hamoa SoC, which get programmed only during
> driver probe. This shouldn't impact or cause any spurious resets once the 
> device is booted up and probe is successful.

And yet it absolutely does break things.

With this patch applied, the box resets within 5GB of heavy network
traffic, probably because some transaction get delayed, and a watchdog
fires. With the patch reverted, the box keeps receiving packets, and
everything is hunky dory (100GB+ so far).

Which makes me think that the set of hardcoded parameters in this
patch is not universal at all.

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v2 2/3] interconnect: qcom: x1e80100: enable QoS configuration

[Konrad Dybcio]

On 9/7/26 10:49 AM, Marc Zyngier wrote:
> On Mon, 07 Sep 2026 09:18:38 +0100,
> Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> wrote:
>>
>>
>>
>> On 9/7/2026 1:39 PM, Marc Zyngier wrote:
>>> On Wed, 02 Sep 2026 14:00:52 +0100,
>>> Mostafa Saleh <smostafa@google.com> wrote:
>>>>
>>>> On Wed, May 27, 2026 at 05:37:10AM +0000, Raviteja Laggyshetty wrote:
>>>>> Enable QoS configuration for master ports with predefined priority
>>>>> and urgency forwarding.

[...]

>>> I'm also seeing spurious resets on my "X1E001DE Snapdragon Devkit for
>>> Windows" when doing large file transfers over the network (30GB+).
>>> With this patch reverted on top of 7.3-rc1, both machines are as solid
>>> as they were before it.
>>>
>> The current patch enable QoS for Hamoa SoC, which get programmed only during
>> driver probe. This shouldn't impact or cause any spurious resets once the 
>> device is booted up and probe is successful.
> 
> And yet it absolutely does break things.
> 
> With this patch applied, the box resets within 5GB of heavy network
> traffic, probably because some transaction get delayed, and a watchdog
> fires. With the patch reverted, the box keeps receiving packets, and
> everything is hunky dory (100GB+ so far).
> 
> Which makes me think that the set of hardcoded parameters in this
> patch is not universal at all.

They are, provided the configuration is for the right SoC..
Turns out Purwa has a slightly different topology and that went
unnoticed as the platform was brought up upstream.

I'll send a fix.

Konrad

Re: [PATCH v2 2/3] interconnect: qcom: x1e80100: enable QoS configuration

[Marc Zyngier]

On Mon, 07 Sep 2026 14:20:26 +0100,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> wrote:
> 
> On 9/7/26 10:49 AM, Marc Zyngier wrote:
> > On Mon, 07 Sep 2026 09:18:38 +0100,
> > Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> wrote:
> >>
> >>
> >>
> >> On 9/7/2026 1:39 PM, Marc Zyngier wrote:
> >>> On Wed, 02 Sep 2026 14:00:52 +0100,
> >>> Mostafa Saleh <smostafa@google.com> wrote:
> >>>>
> >>>> On Wed, May 27, 2026 at 05:37:10AM +0000, Raviteja Laggyshetty wrote:
> >>>>> Enable QoS configuration for master ports with predefined priority
> >>>>> and urgency forwarding.
> 
> [...]
> 
> >>> I'm also seeing spurious resets on my "X1E001DE Snapdragon Devkit for
> >>> Windows" when doing large file transfers over the network (30GB+).
> >>> With this patch reverted on top of 7.3-rc1, both machines are as solid
> >>> as they were before it.
> >>>
> >> The current patch enable QoS for Hamoa SoC, which get programmed only during
> >> driver probe. This shouldn't impact or cause any spurious resets once the 
> >> device is booted up and probe is successful.
> > 
> > And yet it absolutely does break things.
> > 
> > With this patch applied, the box resets within 5GB of heavy network
> > traffic, probably because some transaction get delayed, and a watchdog
> > fires. With the patch reverted, the box keeps receiving packets, and
> > everything is hunky dory (100GB+ so far).
> > 
> > Which makes me think that the set of hardcoded parameters in this
> > patch is not universal at all.
> 
> They are, provided the configuration is for the right SoC..

Is x1e001de different from x1e80100? AFAIK, it is only a binned
version of the same SoC. How do you explain the above regression?

> Turns out Purwa has a slightly different topology and that went
> unnoticed as the platform was brought up upstream.
> 
> I'll send a fix.

That'd be good.

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v2 2/3] interconnect: qcom: x1e80100: enable QoS configuration

[Konrad Dybcio]

On 9/7/26 3:34 PM, Marc Zyngier wrote:
> On Mon, 07 Sep 2026 14:20:26 +0100,
> Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> wrote:
>>
>> On 9/7/26 10:49 AM, Marc Zyngier wrote:
>>> On Mon, 07 Sep 2026 09:18:38 +0100,
>>> Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> wrote:

[...]

>>>> The current patch enable QoS for Hamoa SoC, which get programmed only during
>>>> driver probe. This shouldn't impact or cause any spurious resets once the 
>>>> device is booted up and probe is successful.
>>>
>>> And yet it absolutely does break things.
>>>
>>> With this patch applied, the box resets within 5GB of heavy network
>>> traffic, probably because some transaction get delayed, and a watchdog
>>> fires. With the patch reverted, the box keeps receiving packets, and
>>> everything is hunky dory (100GB+ so far).
>>>
>>> Which makes me think that the set of hardcoded parameters in this
>>> patch is not universal at all.
>>
>> They are, provided the configuration is for the right SoC..
> 
> Is x1e001de different from x1e80100? AFAIK, it is only a binned
> version of the same SoC. How do you explain the above regression?

I somehow skimmed over the fact you said it's on the devkit and not
on the mini-x mentioned before.

I pulled the Hamoa settings I could find, there are some updates but
none seem particularly related (maybe the PCIe one? I don't know how
the network card is connected), please give the attached patch a try.

If nothing else, please "bisect" the QoS additions until it stops
crashing. Although perhaps applying only some of the settings may
have its own set of dragons..

Compile-tested only
https://github.com/quic-kdybcio/linux/commits/topic/hamoa_purwa_qos

The Purwa icc patch is a bit of a mess because some nodes seem to have
moved around buses..

Konrad

Re: [PATCH v2 2/3] interconnect: qcom: x1e80100: enable QoS configuration

[Marc Zyngier]

On Mon, 07 Sep 2026 15:34:35 +0100,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> wrote:
> 
> On 9/7/26 3:34 PM, Marc Zyngier wrote:
> > On Mon, 07 Sep 2026 14:20:26 +0100,
> > Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> wrote:
> >>
> >> On 9/7/26 10:49 AM, Marc Zyngier wrote:
> >>> On Mon, 07 Sep 2026 09:18:38 +0100,
> >>> Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> wrote:
> 
> [...]
> 
> >>>> The current patch enable QoS for Hamoa SoC, which get programmed only during
> >>>> driver probe. This shouldn't impact or cause any spurious resets once the 
> >>>> device is booted up and probe is successful.
> >>>
> >>> And yet it absolutely does break things.
> >>>
> >>> With this patch applied, the box resets within 5GB of heavy network
> >>> traffic, probably because some transaction get delayed, and a watchdog
> >>> fires. With the patch reverted, the box keeps receiving packets, and
> >>> everything is hunky dory (100GB+ so far).
> >>>
> >>> Which makes me think that the set of hardcoded parameters in this
> >>> patch is not universal at all.
> >>
> >> They are, provided the configuration is for the right SoC..
> > 
> > Is x1e001de different from x1e80100? AFAIK, it is only a binned
> > version of the same SoC. How do you explain the above regression?
> 
> I somehow skimmed over the fact you said it's on the devkit and not
> on the mini-x mentioned before.
> 
> I pulled the Hamoa settings I could find, there are some updates but
> none seem particularly related (maybe the PCIe one? I don't know how
> the network card is connected), please give the attached patch a try.

I cherry-picked the Hamoa-specific patch, and gave it a go. Same
result (hard reset while synchronising a bunch of files), but this
time with a nice little message:

[  272.468031] nvme nvme0: controller is down; will reset: CSTS=0xffffffff, PCI_STATUS=0xffff
[  272.468039] nvme nvme0: Does your device have a faulty power saving mode enabled?
[  272.468039] nvme nvme0: Try "nvme_core.default_ps_max_latency_us=0 pcie_aspm=off pcie_port_pm=off" and report a bug

indicating that PCIe has died.

None of that happens without the QoS stuff.

> If nothing else, please "bisect" the QoS additions until it stops
> crashing. Although perhaps applying only some of the settings may
> have its own set of dragons..

That's not exactly encouraging, is it? And if the "recommended" set of
tunables is not up to scratch, surely there should be a way to opt-out
until someone figures out what's wrong. Something like this:

diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c
index 3b445acefece7..3a4743c364dac 100644
--- a/drivers/interconnect/qcom/icc-rpmh.c
+++ b/drivers/interconnect/qcom/icc-rpmh.c
@@ -224,6 +224,9 @@ static int qcom_icc_rpmh_configure_qos(struct qcom_icc_provider *qp)
 	return ret;
 }
 
+static bool enable_qos = true;
+module_param(enable_qos, bool, 0660);
+
 int qcom_icc_rpmh_probe(struct platform_device *pdev)
 {
 	const struct qcom_icc_desc *desc;
@@ -308,6 +311,11 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
 		struct resource *res;
 		void __iomem *base;
 
+		if (!enable_qos) {
+			dev_info(dev, "Skipping QoS (command line)\n");
+			goto skip_qos_config;
+		}
+
 		/* Try parent's regmap first */
 		qp->regmap = dev_get_regmap(dev->parent, NULL);
 		if (!qp->regmap) {

At least people stuck with Purwa or other abandonware (such as the
devkit) would still have a usable machine.

	M.


-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v2 2/3] interconnect: qcom: x1e80100: enable QoS configuration

[Raviteja Laggyshetty]

On 9/7/2026 10:20 PM, Marc Zyngier wrote:
> On Mon, 07 Sep 2026 15:34:35 +0100,
> Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> wrote:
>>
>> On 9/7/26 3:34 PM, Marc Zyngier wrote:
>>> On Mon, 07 Sep 2026 14:20:26 +0100,
>>> Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> wrote:
>>>>
>>>> On 9/7/26 10:49 AM, Marc Zyngier wrote:
>>>>> On Mon, 07 Sep 2026 09:18:38 +0100,
>>>>> Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> wrote:
>>
>> [...]
>>
>>>>>> The current patch enable QoS for Hamoa SoC, which get programmed only during
>>>>>> driver probe. This shouldn't impact or cause any spurious resets once the 
>>>>>> device is booted up and probe is successful.
>>>>>
>>>>> And yet it absolutely does break things.
>>>>>
>>>>> With this patch applied, the box resets within 5GB of heavy network
>>>>> traffic, probably because some transaction get delayed, and a watchdog
>>>>> fires. With the patch reverted, the box keeps receiving packets, and
>>>>> everything is hunky dory (100GB+ so far).
>>>>>
>>>>> Which makes me think that the set of hardcoded parameters in this
>>>>> patch is not universal at all.
>>>>
>>>> They are, provided the configuration is for the right SoC..
>>>
>>> Is x1e001de different from x1e80100? AFAIK, it is only a binned
>>> version of the same SoC. How do you explain the above regression?
>>
>> I somehow skimmed over the fact you said it's on the devkit and not
>> on the mini-x mentioned before.
>>
>> I pulled the Hamoa settings I could find, there are some updates but
>> none seem particularly related (maybe the PCIe one? I don't know how
>> the network card is connected), please give the attached patch a try.
> 
> I cherry-picked the Hamoa-specific patch, and gave it a go. Same
> result (hard reset while synchronising a bunch of files), but this
> time with a nice little message:
> 
> [  272.468031] nvme nvme0: controller is down; will reset: CSTS=0xffffffff, PCI_STATUS=0xffff
> [  272.468039] nvme nvme0: Does your device have a faulty power saving mode enabled?
> [  272.468039] nvme nvme0: Try "nvme_core.default_ps_max_latency_us=0 pcie_aspm=off pcie_port_pm=off" and report a bug
> 
> indicating that PCIe has died.
> 
> None of that happens without the QoS stuff.
> 
>> If nothing else, please "bisect" the QoS additions until it stops
>> crashing. Although perhaps applying only some of the settings may
>> have its own set of dragons..
> 
> That's not exactly encouraging, is it? And if the "recommended" set of
> tunables is not up to scratch, surely there should be a way to opt-out
> until someone figures out what's wrong. Something like this:
> 
Compared to Hamoa, some PCIe ports are removed on Purwa.
Let me share you an updated patch to try.

> diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c
> index 3b445acefece7..3a4743c364dac 100644
> --- a/drivers/interconnect/qcom/icc-rpmh.c
> +++ b/drivers/interconnect/qcom/icc-rpmh.c
> @@ -224,6 +224,9 @@ static int qcom_icc_rpmh_configure_qos(struct qcom_icc_provider *qp)
>  	return ret;
>  }
>  
> +static bool enable_qos = true;
> +module_param(enable_qos, bool, 0660);
> +
>  int qcom_icc_rpmh_probe(struct platform_device *pdev)
>  {
>  	const struct qcom_icc_desc *desc;
> @@ -308,6 +311,11 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
>  		struct resource *res;
>  		void __iomem *base;
>  
> +		if (!enable_qos) {
> +			dev_info(dev, "Skipping QoS (command line)\n");
> +			goto skip_qos_config;
> +		}
> +
>  		/* Try parent's regmap first */
>  		qp->regmap = dev_get_regmap(dev->parent, NULL);
>  		if (!qp->regmap) {
> 
> At least people stuck with Purwa or other abandonware (such as the
> devkit) would still have a usable machine.
> 
> 	M.
> 
> 

[PATCH v2 3/3] arm64: dts: qcom: x1e80100: Add clocks for QoS configuration

[Raviteja Laggyshetty]

Add clocks which need to be enabled for configuring QoS on
x1e80100 SoC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/hamoa.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index 4ba751a65142..1a2d9b3f7a70 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -3132,6 +3132,7 @@ aggre1_noc: interconnect@16e0000 {
 			qcom,bcm-voters = <&apps_bcm_voter>;
 
 			#interconnect-cells = <2>;
+			clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
 		};
 
 		aggre2_noc: interconnect@1700000 {
@@ -3168,6 +3169,8 @@ usb_north_anoc: interconnect@1760000 {
 			qcom,bcm-voters = <&apps_bcm_voter>;
 
 			#interconnect-cells = <2>;
+			clocks = <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>;
 		};
 
 		usb_south_anoc: interconnect@1770000 {
@@ -3177,6 +3180,12 @@ usb_south_anoc: interconnect@1770000 {
 			qcom,bcm-voters = <&apps_bcm_voter>;
 
 			#interconnect-cells = <2>;
+			clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB4_0_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB4_1_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB4_2_AXI_CLK>;
 		};
 
 		mmss_noc: interconnect@1780000 {

-- 
2.43.0

Re: (subset) [PATCH v2 0/3] Enable QoS configuration on X1E80100

[Bjorn Andersson]

On Wed, 27 May 2026 05:37:08 +0000, Raviteja Laggyshetty wrote:
> This series enables QoS configuration for QNOC type device which
> can be found on X1E80100 platform. It enables QoS configuration
> for master ports with predefined priority and urgency forwarding.
> This helps in prioritizing the traffic originating from different
> interconnect masters at NOC (Network On Chip).
> 
> The system may function normally without this feature. However,
> enabling QoS helps optimize latency and bandwidth across subsystems
> like CPU, GPU, and multimedia engines, which becomes important in
> high-throughput scenarios. This is a feature aimed at performance
> enhancement to improve system performance under concurrent workloads.
> 
> [...]

Applied, thanks!

[3/3] arm64: dts: qcom: x1e80100: Add clocks for QoS configuration
      commit: f49d819c89876f882a9f1b9ac6ae020fd7e92152

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>